1 /* $NetBSD: amdgpu_dcn20_dsc.c,v 1.2 2021/12/18 23:45:03 riastradh Exp $ */ 2 3 /* 4 * Copyright 2017 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: AMD 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: amdgpu_dcn20_dsc.c,v 1.2 2021/12/18 23:45:03 riastradh Exp $"); 30 31 #include "reg_helper.h" 32 #include "dcn20_dsc.h" 33 #include "dsc/dscc_types.h" 34 35 static void dsc_log_pps(struct display_stream_compressor *dsc, struct drm_dsc_config *pps); 36 static bool dsc_prepare_config(const struct dsc_config *dsc_cfg, struct dsc_reg_values *dsc_reg_vals, 37 struct dsc_optc_config *dsc_optc_cfg); 38 static void dsc_init_reg_values(struct dsc_reg_values *reg_vals); 39 static void dsc_update_from_dsc_parameters(struct dsc_reg_values *reg_vals, const struct dsc_parameters *dsc_params); 40 static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_values *reg_vals); 41 static enum dsc_pixel_format dsc_dc_pixel_encoding_to_dsc_pixel_format(enum dc_pixel_encoding dc_pix_enc, bool is_ycbcr422_simple); 42 static enum dsc_bits_per_comp dsc_dc_color_depth_to_dsc_bits_per_comp(enum dc_color_depth); 43 44 /* Object I/F functions */ 45 static void dsc2_get_enc_caps(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock_100Hz); 46 static void dsc2_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s); 47 static bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg); 48 static void dsc2_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, 49 struct dsc_optc_config *dsc_optc_cfg); 50 static bool dsc2_get_packed_pps(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, uint8_t *dsc_packed_pps); 51 static void dsc2_enable(struct display_stream_compressor *dsc, int opp_pipe); 52 static void dsc2_disable(struct display_stream_compressor *dsc); 53 54 const struct dsc_funcs dcn20_dsc_funcs = { 55 .dsc_get_enc_caps = dsc2_get_enc_caps, 56 .dsc_read_state = dsc2_read_state, 57 .dsc_validate_stream = dsc2_validate_stream, 58 .dsc_set_config = dsc2_set_config, 59 .dsc_get_packed_pps = dsc2_get_packed_pps, 60 .dsc_enable = dsc2_enable, 61 .dsc_disable = dsc2_disable, 62 }; 63 64 /* Macro definitios for REG_SET macros*/ 65 #define CTX \ 66 dsc20->base.ctx 67 68 #define REG(reg)\ 69 dsc20->dsc_regs->reg 70 71 #undef FN 72 #define FN(reg_name, field_name) \ 73 dsc20->dsc_shift->field_name, dsc20->dsc_mask->field_name 74 #define DC_LOGGER \ 75 dsc->ctx->logger 76 77 enum dsc_bits_per_comp { 78 DSC_BPC_8 = 8, 79 DSC_BPC_10 = 10, 80 DSC_BPC_12 = 12, 81 DSC_BPC_UNKNOWN 82 }; 83 84 /* API functions (external or via structure->function_pointer) */ 85 86 void dsc2_construct(struct dcn20_dsc *dsc, 87 struct dc_context *ctx, 88 int inst, 89 const struct dcn20_dsc_registers *dsc_regs, 90 const struct dcn20_dsc_shift *dsc_shift, 91 const struct dcn20_dsc_mask *dsc_mask) 92 { 93 dsc->base.ctx = ctx; 94 dsc->base.inst = inst; 95 dsc->base.funcs = &dcn20_dsc_funcs; 96 97 dsc->dsc_regs = dsc_regs; 98 dsc->dsc_shift = dsc_shift; 99 dsc->dsc_mask = dsc_mask; 100 101 dsc->max_image_width = 5184; 102 } 103 104 105 #define DCN20_MAX_PIXEL_CLOCK_Mhz 1188 106 #define DCN20_MAX_DISPLAY_CLOCK_Mhz 1200 107 108 /* This returns the capabilities for a single DSC encoder engine. Number of slices and total throughput 109 * can be doubled, tripled etc. by using additional DSC engines. 110 */ 111 static void dsc2_get_enc_caps(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock_100Hz) 112 { 113 dsc_enc_caps->dsc_version = 0x21; /* v1.2 - DP spec defined it in reverse order and we kept it */ 114 115 dsc_enc_caps->slice_caps.bits.NUM_SLICES_1 = 1; 116 dsc_enc_caps->slice_caps.bits.NUM_SLICES_2 = 1; 117 dsc_enc_caps->slice_caps.bits.NUM_SLICES_3 = 1; 118 dsc_enc_caps->slice_caps.bits.NUM_SLICES_4 = 1; 119 120 dsc_enc_caps->lb_bit_depth = 13; 121 dsc_enc_caps->is_block_pred_supported = true; 122 123 dsc_enc_caps->color_formats.bits.RGB = 1; 124 dsc_enc_caps->color_formats.bits.YCBCR_444 = 1; 125 dsc_enc_caps->color_formats.bits.YCBCR_SIMPLE_422 = 1; 126 dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 0; 127 dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_420 = 1; 128 129 dsc_enc_caps->color_depth.bits.COLOR_DEPTH_8_BPC = 1; 130 dsc_enc_caps->color_depth.bits.COLOR_DEPTH_10_BPC = 1; 131 dsc_enc_caps->color_depth.bits.COLOR_DEPTH_12_BPC = 1; 132 133 /* Maximum total throughput with all the slices combined. This is different from how DP spec specifies it. 134 * Our decoder's total throughput in Pix/s is equal to DISPCLK. This is then shared between slices. 135 * The value below is the absolute maximum value. The actual throughput may be lower, but it'll always 136 * be sufficient to process the input pixel rate fed into a single DSC engine. 137 */ 138 dsc_enc_caps->max_total_throughput_mps = DCN20_MAX_DISPLAY_CLOCK_Mhz; 139 140 /* For pixel clock bigger than a single-pipe limit we'll need two engines, which then doubles our 141 * throughput and number of slices, but also introduces a lower limit of 2 slices 142 */ 143 if (pixel_clock_100Hz >= DCN20_MAX_PIXEL_CLOCK_Mhz*10000) { 144 dsc_enc_caps->slice_caps.bits.NUM_SLICES_1 = 0; 145 dsc_enc_caps->slice_caps.bits.NUM_SLICES_8 = 1; 146 dsc_enc_caps->max_total_throughput_mps = DCN20_MAX_DISPLAY_CLOCK_Mhz * 2; 147 } 148 149 // TODO DSC: This is actually image width limitation, not a slice width. This should be added to the criteria to use ODM. 150 dsc_enc_caps->max_slice_width = 5184; /* (including 64 overlap pixels for eDP MSO mode) */ 151 dsc_enc_caps->bpp_increment_div = 16; /* 1/16th of a bit */ 152 } 153 154 155 /* this function read dsc related register fields to be logged later in dcn10_log_hw_state 156 * into a dcn_dsc_state struct. 157 */ 158 static void dsc2_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s) 159 { 160 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); 161 162 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &s->dsc_clock_en); 163 REG_GET(DSCC_PPS_CONFIG3, SLICE_WIDTH, &s->dsc_slice_width); 164 REG_GET(DSCC_PPS_CONFIG1, BITS_PER_PIXEL, &s->dsc_bytes_per_pixel); 165 } 166 167 168 static bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg) 169 { 170 struct dsc_optc_config dsc_optc_cfg; 171 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); 172 173 if (dsc_cfg->pic_width > dsc20->max_image_width) 174 return false; 175 176 return dsc_prepare_config(dsc_cfg, &dsc20->reg_vals, &dsc_optc_cfg); 177 } 178 179 180 static void dsc_config_log(struct display_stream_compressor *dsc, const struct dsc_config *config) 181 { 182 DC_LOG_DSC("\tnum_slices_h %d", config->dc_dsc_cfg.num_slices_h); 183 DC_LOG_DSC("\tnum_slices_v %d", config->dc_dsc_cfg.num_slices_v); 184 DC_LOG_DSC("\tbits_per_pixel %d (%d.%04d)", 185 config->dc_dsc_cfg.bits_per_pixel, 186 config->dc_dsc_cfg.bits_per_pixel / 16, 187 ((config->dc_dsc_cfg.bits_per_pixel % 16) * 10000) / 16); 188 DC_LOG_DSC("\tcolor_depth %d", config->color_depth); 189 } 190 191 static void dsc2_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, 192 struct dsc_optc_config *dsc_optc_cfg) 193 { 194 bool is_config_ok; 195 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); 196 197 DC_LOG_DSC(" "); 198 DC_LOG_DSC("Setting DSC Config at DSC inst %d", dsc->inst); 199 dsc_config_log(dsc, dsc_cfg); 200 is_config_ok = dsc_prepare_config(dsc_cfg, &dsc20->reg_vals, dsc_optc_cfg); 201 ASSERT(is_config_ok); 202 DC_LOG_DSC("programming DSC Picture Parameter Set (PPS):"); 203 dsc_log_pps(dsc, &dsc20->reg_vals.pps); 204 dsc_write_to_registers(dsc, &dsc20->reg_vals); 205 } 206 207 208 static bool dsc2_get_packed_pps(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, uint8_t *dsc_packed_pps) 209 { 210 bool is_config_ok; 211 struct dsc_reg_values dsc_reg_vals; 212 struct dsc_optc_config dsc_optc_cfg; 213 214 memset(&dsc_reg_vals, 0, sizeof(dsc_reg_vals)); 215 memset(&dsc_optc_cfg, 0, sizeof(dsc_optc_cfg)); 216 217 DC_LOG_DSC("Getting packed DSC PPS for DSC Config:"); 218 dsc_config_log(dsc, dsc_cfg); 219 DC_LOG_DSC("DSC Picture Parameter Set (PPS):"); 220 is_config_ok = dsc_prepare_config(dsc_cfg, &dsc_reg_vals, &dsc_optc_cfg); 221 ASSERT(is_config_ok); 222 drm_dsc_pps_payload_pack((struct drm_dsc_picture_parameter_set *)dsc_packed_pps, &dsc_reg_vals.pps); 223 dsc_log_pps(dsc, &dsc_reg_vals.pps); 224 225 return is_config_ok; 226 } 227 228 229 static void dsc2_enable(struct display_stream_compressor *dsc, int opp_pipe) 230 { 231 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); 232 int dsc_clock_en; 233 int dsc_fw_config; 234 int enabled_opp_pipe; 235 236 DC_LOG_DSC("enable DSC %d at opp pipe %d", dsc->inst, opp_pipe); 237 238 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en); 239 REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &dsc_fw_config, DSCRM_DSC_OPP_PIPE_SOURCE, &enabled_opp_pipe); 240 if ((dsc_clock_en || dsc_fw_config) && enabled_opp_pipe != opp_pipe) { 241 DC_LOG_DSC("ERROR: DSC %d at opp pipe %d already enabled!", dsc->inst, enabled_opp_pipe); 242 ASSERT(0); 243 } 244 245 REG_UPDATE(DSC_TOP_CONTROL, 246 DSC_CLOCK_EN, 1); 247 248 REG_UPDATE_2(DSCRM_DSC_FORWARD_CONFIG, 249 DSCRM_DSC_FORWARD_EN, 1, 250 DSCRM_DSC_OPP_PIPE_SOURCE, opp_pipe); 251 } 252 253 254 static void dsc2_disable(struct display_stream_compressor *dsc) 255 { 256 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); 257 int dsc_clock_en; 258 int dsc_fw_config; 259 int enabled_opp_pipe; 260 261 DC_LOG_DSC("disable DSC %d", dsc->inst); 262 263 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en); 264 REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &dsc_fw_config, DSCRM_DSC_OPP_PIPE_SOURCE, &enabled_opp_pipe); 265 if (!dsc_clock_en || !dsc_fw_config) { 266 DC_LOG_DSC("ERROR: DSC %d at opp pipe %d already disabled!", dsc->inst, enabled_opp_pipe); 267 ASSERT(0); 268 } 269 270 REG_UPDATE(DSCRM_DSC_FORWARD_CONFIG, 271 DSCRM_DSC_FORWARD_EN, 0); 272 273 REG_UPDATE(DSC_TOP_CONTROL, 274 DSC_CLOCK_EN, 0); 275 } 276 277 278 /* This module's internal functions */ 279 static void dsc_log_pps(struct display_stream_compressor *dsc, struct drm_dsc_config *pps) 280 { 281 int i; 282 int bits_per_pixel = pps->bits_per_pixel; 283 284 DC_LOG_DSC("\tdsc_version_major %d", pps->dsc_version_major); 285 DC_LOG_DSC("\tdsc_version_minor %d", pps->dsc_version_minor); 286 DC_LOG_DSC("\tbits_per_component %d", pps->bits_per_component); 287 DC_LOG_DSC("\tline_buf_depth %d", pps->line_buf_depth); 288 DC_LOG_DSC("\tblock_pred_enable %d", pps->block_pred_enable); 289 DC_LOG_DSC("\tconvert_rgb %d", pps->convert_rgb); 290 DC_LOG_DSC("\tsimple_422 %d", pps->simple_422); 291 DC_LOG_DSC("\tvbr_enable %d", pps->vbr_enable); 292 DC_LOG_DSC("\tbits_per_pixel %d (%d.%04d)", bits_per_pixel, bits_per_pixel / 16, ((bits_per_pixel % 16) * 10000) / 16); 293 DC_LOG_DSC("\tpic_height %d", pps->pic_height); 294 DC_LOG_DSC("\tpic_width %d", pps->pic_width); 295 DC_LOG_DSC("\tslice_height %d", pps->slice_height); 296 DC_LOG_DSC("\tslice_width %d", pps->slice_width); 297 DC_LOG_DSC("\tslice_chunk_size %d", pps->slice_chunk_size); 298 DC_LOG_DSC("\tinitial_xmit_delay %d", pps->initial_xmit_delay); 299 DC_LOG_DSC("\tinitial_dec_delay %d", pps->initial_dec_delay); 300 DC_LOG_DSC("\tinitial_scale_value %d", pps->initial_scale_value); 301 DC_LOG_DSC("\tscale_increment_interval %d", pps->scale_increment_interval); 302 DC_LOG_DSC("\tscale_decrement_interval %d", pps->scale_decrement_interval); 303 DC_LOG_DSC("\tfirst_line_bpg_offset %d", pps->first_line_bpg_offset); 304 DC_LOG_DSC("\tnfl_bpg_offset %d", pps->nfl_bpg_offset); 305 DC_LOG_DSC("\tslice_bpg_offset %d", pps->slice_bpg_offset); 306 DC_LOG_DSC("\tinitial_offset %d", pps->initial_offset); 307 DC_LOG_DSC("\tfinal_offset %d", pps->final_offset); 308 DC_LOG_DSC("\tflatness_min_qp %d", pps->flatness_min_qp); 309 DC_LOG_DSC("\tflatness_max_qp %d", pps->flatness_max_qp); 310 /* DC_LOG_DSC("\trc_parameter_set %d", pps->rc_parameter_set); */ 311 DC_LOG_DSC("\tnative_420 %d", pps->native_420); 312 DC_LOG_DSC("\tnative_422 %d", pps->native_422); 313 DC_LOG_DSC("\tsecond_line_bpg_offset %d", pps->second_line_bpg_offset); 314 DC_LOG_DSC("\tnsl_bpg_offset %d", pps->nsl_bpg_offset); 315 DC_LOG_DSC("\tsecond_line_offset_adj %d", pps->second_line_offset_adj); 316 DC_LOG_DSC("\trc_model_size %d", pps->rc_model_size); 317 DC_LOG_DSC("\trc_edge_factor %d", pps->rc_edge_factor); 318 DC_LOG_DSC("\trc_quant_incr_limit0 %d", pps->rc_quant_incr_limit0); 319 DC_LOG_DSC("\trc_quant_incr_limit1 %d", pps->rc_quant_incr_limit1); 320 DC_LOG_DSC("\trc_tgt_offset_high %d", pps->rc_tgt_offset_high); 321 DC_LOG_DSC("\trc_tgt_offset_low %d", pps->rc_tgt_offset_low); 322 323 for (i = 0; i < NUM_BUF_RANGES - 1; i++) 324 DC_LOG_DSC("\trc_buf_thresh[%d] %d", i, pps->rc_buf_thresh[i]); 325 326 for (i = 0; i < NUM_BUF_RANGES; i++) { 327 DC_LOG_DSC("\trc_range_parameters[%d].range_min_qp %d", i, pps->rc_range_params[i].range_min_qp); 328 DC_LOG_DSC("\trc_range_parameters[%d].range_max_qp %d", i, pps->rc_range_params[i].range_max_qp); 329 DC_LOG_DSC("\trc_range_parameters[%d].range_bpg_offset %d", i, pps->rc_range_params[i].range_bpg_offset); 330 } 331 } 332 333 static bool dsc_prepare_config(const struct dsc_config *dsc_cfg, struct dsc_reg_values *dsc_reg_vals, 334 struct dsc_optc_config *dsc_optc_cfg) 335 { 336 struct dsc_parameters dsc_params; 337 338 /* Validate input parameters */ 339 ASSERT(dsc_cfg->dc_dsc_cfg.num_slices_h); 340 ASSERT(dsc_cfg->dc_dsc_cfg.num_slices_v); 341 ASSERT(dsc_cfg->dc_dsc_cfg.version_minor == 1 || dsc_cfg->dc_dsc_cfg.version_minor == 2); 342 ASSERT(dsc_cfg->pic_width); 343 ASSERT(dsc_cfg->pic_height); 344 ASSERT((dsc_cfg->dc_dsc_cfg.version_minor == 1 && 345 (8 <= dsc_cfg->dc_dsc_cfg.linebuf_depth && dsc_cfg->dc_dsc_cfg.linebuf_depth <= 13)) || 346 (dsc_cfg->dc_dsc_cfg.version_minor == 2 && 347 ((8 <= dsc_cfg->dc_dsc_cfg.linebuf_depth && dsc_cfg->dc_dsc_cfg.linebuf_depth <= 15) || 348 dsc_cfg->dc_dsc_cfg.linebuf_depth == 0))); 349 ASSERT(96 <= dsc_cfg->dc_dsc_cfg.bits_per_pixel && dsc_cfg->dc_dsc_cfg.bits_per_pixel <= 0x3ff); // 6.0 <= bits_per_pixel <= 63.9375 350 351 if (!dsc_cfg->dc_dsc_cfg.num_slices_v || !dsc_cfg->dc_dsc_cfg.num_slices_h || 352 !(dsc_cfg->dc_dsc_cfg.version_minor == 1 || dsc_cfg->dc_dsc_cfg.version_minor == 2) || 353 !dsc_cfg->pic_width || !dsc_cfg->pic_height || 354 !((dsc_cfg->dc_dsc_cfg.version_minor == 1 && // v1.1 line buffer depth range: 355 8 <= dsc_cfg->dc_dsc_cfg.linebuf_depth && dsc_cfg->dc_dsc_cfg.linebuf_depth <= 13) || 356 (dsc_cfg->dc_dsc_cfg.version_minor == 2 && // v1.2 line buffer depth range: 357 ((8 <= dsc_cfg->dc_dsc_cfg.linebuf_depth && dsc_cfg->dc_dsc_cfg.linebuf_depth <= 15) || 358 dsc_cfg->dc_dsc_cfg.linebuf_depth == 0))) || 359 !(96 <= dsc_cfg->dc_dsc_cfg.bits_per_pixel && dsc_cfg->dc_dsc_cfg.bits_per_pixel <= 0x3ff)) { 360 dm_output_to_console("%s: Invalid parameters\n", __func__); 361 return false; 362 } 363 364 dsc_init_reg_values(dsc_reg_vals); 365 366 /* Copy input config */ 367 dsc_reg_vals->pixel_format = dsc_dc_pixel_encoding_to_dsc_pixel_format(dsc_cfg->pixel_encoding, dsc_cfg->dc_dsc_cfg.ycbcr422_simple); 368 dsc_reg_vals->num_slices_h = dsc_cfg->dc_dsc_cfg.num_slices_h; 369 dsc_reg_vals->num_slices_v = dsc_cfg->dc_dsc_cfg.num_slices_v; 370 dsc_reg_vals->pps.dsc_version_minor = dsc_cfg->dc_dsc_cfg.version_minor; 371 dsc_reg_vals->pps.pic_width = dsc_cfg->pic_width; 372 dsc_reg_vals->pps.pic_height = dsc_cfg->pic_height; 373 dsc_reg_vals->pps.bits_per_component = dsc_dc_color_depth_to_dsc_bits_per_comp(dsc_cfg->color_depth); 374 dsc_reg_vals->pps.block_pred_enable = dsc_cfg->dc_dsc_cfg.block_pred_enable; 375 dsc_reg_vals->pps.line_buf_depth = dsc_cfg->dc_dsc_cfg.linebuf_depth; 376 dsc_reg_vals->alternate_ich_encoding_en = dsc_reg_vals->pps.dsc_version_minor == 1 ? 0 : 1; 377 378 // TODO: in addition to validating slice height (pic height must be divisible by slice height), 379 // see what happens when the same condition doesn't apply for slice_width/pic_width. 380 dsc_reg_vals->pps.slice_width = dsc_cfg->pic_width / dsc_cfg->dc_dsc_cfg.num_slices_h; 381 dsc_reg_vals->pps.slice_height = dsc_cfg->pic_height / dsc_cfg->dc_dsc_cfg.num_slices_v; 382 383 ASSERT(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height); 384 if (!(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height)) { 385 dm_output_to_console("%s: pix height %d not divisible by num_slices_v %d\n\n", __func__, dsc_cfg->pic_height, dsc_cfg->dc_dsc_cfg.num_slices_v); 386 return false; 387 } 388 389 dsc_reg_vals->bpp_x32 = dsc_cfg->dc_dsc_cfg.bits_per_pixel << 1; 390 if (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420 || dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422) 391 dsc_reg_vals->pps.bits_per_pixel = dsc_reg_vals->bpp_x32; 392 else 393 dsc_reg_vals->pps.bits_per_pixel = dsc_reg_vals->bpp_x32 >> 1; 394 395 dsc_reg_vals->pps.convert_rgb = dsc_reg_vals->pixel_format == DSC_PIXFMT_RGB ? 1 : 0; 396 dsc_reg_vals->pps.native_422 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422); 397 dsc_reg_vals->pps.native_420 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420); 398 dsc_reg_vals->pps.simple_422 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422); 399 400 if (dscc_compute_dsc_parameters(&dsc_reg_vals->pps, &dsc_params)) { 401 dm_output_to_console("%s: DSC config failed\n", __func__); 402 return false; 403 } 404 405 dsc_update_from_dsc_parameters(dsc_reg_vals, &dsc_params); 406 407 dsc_optc_cfg->bytes_per_pixel = dsc_params.bytes_per_pixel; 408 dsc_optc_cfg->slice_width = dsc_reg_vals->pps.slice_width; 409 dsc_optc_cfg->is_pixel_format_444 = dsc_reg_vals->pixel_format == DSC_PIXFMT_RGB || 410 dsc_reg_vals->pixel_format == DSC_PIXFMT_YCBCR444 || 411 dsc_reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422; 412 413 return true; 414 } 415 416 417 static enum dsc_pixel_format dsc_dc_pixel_encoding_to_dsc_pixel_format(enum dc_pixel_encoding dc_pix_enc, bool is_ycbcr422_simple) 418 { 419 enum dsc_pixel_format dsc_pix_fmt = DSC_PIXFMT_UNKNOWN; 420 421 /* NOTE: We don't support DSC_PIXFMT_SIMPLE_YCBCR422 */ 422 423 switch (dc_pix_enc) { 424 case PIXEL_ENCODING_RGB: 425 dsc_pix_fmt = DSC_PIXFMT_RGB; 426 break; 427 case PIXEL_ENCODING_YCBCR422: 428 if (is_ycbcr422_simple) 429 dsc_pix_fmt = DSC_PIXFMT_SIMPLE_YCBCR422; 430 else 431 dsc_pix_fmt = DSC_PIXFMT_NATIVE_YCBCR422; 432 break; 433 case PIXEL_ENCODING_YCBCR444: 434 dsc_pix_fmt = DSC_PIXFMT_YCBCR444; 435 break; 436 case PIXEL_ENCODING_YCBCR420: 437 dsc_pix_fmt = DSC_PIXFMT_NATIVE_YCBCR420; 438 break; 439 default: 440 dsc_pix_fmt = DSC_PIXFMT_UNKNOWN; 441 break; 442 } 443 444 ASSERT(dsc_pix_fmt != DSC_PIXFMT_UNKNOWN); 445 return dsc_pix_fmt; 446 } 447 448 449 static enum dsc_bits_per_comp dsc_dc_color_depth_to_dsc_bits_per_comp(enum dc_color_depth dc_color_depth) 450 { 451 enum dsc_bits_per_comp bpc = DSC_BPC_UNKNOWN; 452 453 switch (dc_color_depth) { 454 case COLOR_DEPTH_888: 455 bpc = DSC_BPC_8; 456 break; 457 case COLOR_DEPTH_101010: 458 bpc = DSC_BPC_10; 459 break; 460 case COLOR_DEPTH_121212: 461 bpc = DSC_BPC_12; 462 break; 463 default: 464 bpc = DSC_BPC_UNKNOWN; 465 break; 466 } 467 468 return bpc; 469 } 470 471 472 static void dsc_init_reg_values(struct dsc_reg_values *reg_vals) 473 { 474 int i; 475 476 memset(reg_vals, 0, sizeof(struct dsc_reg_values)); 477 478 /* Non-PPS values */ 479 reg_vals->dsc_clock_enable = 1; 480 reg_vals->dsc_clock_gating_disable = 0; 481 reg_vals->underflow_recovery_en = 0; 482 reg_vals->underflow_occurred_int_en = 0; 483 reg_vals->underflow_occurred_status = 0; 484 reg_vals->ich_reset_at_eol = 0; 485 reg_vals->alternate_ich_encoding_en = 0; 486 reg_vals->rc_buffer_model_size = 0; 487 /*reg_vals->disable_ich = 0;*/ 488 reg_vals->dsc_dbg_en = 0; 489 490 for (i = 0; i < 4; i++) 491 reg_vals->rc_buffer_model_overflow_int_en[i] = 0; 492 493 /* PPS values */ 494 reg_vals->pps.dsc_version_minor = 2; 495 reg_vals->pps.dsc_version_major = 1; 496 reg_vals->pps.line_buf_depth = 9; 497 reg_vals->pps.bits_per_component = 8; 498 reg_vals->pps.block_pred_enable = 1; 499 reg_vals->pps.slice_chunk_size = 0; 500 reg_vals->pps.pic_width = 0; 501 reg_vals->pps.pic_height = 0; 502 reg_vals->pps.slice_width = 0; 503 reg_vals->pps.slice_height = 0; 504 reg_vals->pps.initial_xmit_delay = 170; 505 reg_vals->pps.initial_dec_delay = 0; 506 reg_vals->pps.initial_scale_value = 0; 507 reg_vals->pps.scale_increment_interval = 0; 508 reg_vals->pps.scale_decrement_interval = 0; 509 reg_vals->pps.nfl_bpg_offset = 0; 510 reg_vals->pps.slice_bpg_offset = 0; 511 reg_vals->pps.nsl_bpg_offset = 0; 512 reg_vals->pps.initial_offset = 6144; 513 reg_vals->pps.final_offset = 0; 514 reg_vals->pps.flatness_min_qp = 3; 515 reg_vals->pps.flatness_max_qp = 12; 516 reg_vals->pps.rc_model_size = 8192; 517 reg_vals->pps.rc_edge_factor = 6; 518 reg_vals->pps.rc_quant_incr_limit0 = 11; 519 reg_vals->pps.rc_quant_incr_limit1 = 11; 520 reg_vals->pps.rc_tgt_offset_low = 3; 521 reg_vals->pps.rc_tgt_offset_high = 3; 522 } 523 524 /* Updates dsc_reg_values::reg_vals::xxx fields based on the values from computed params. 525 * This is required because dscc_compute_dsc_parameters returns a modified PPS, which in turn 526 * affects non-PPS register values. 527 */ 528 static void dsc_update_from_dsc_parameters(struct dsc_reg_values *reg_vals, const struct dsc_parameters *dsc_params) 529 { 530 int i; 531 532 reg_vals->pps = dsc_params->pps; 533 534 // pps_computed will have the "expanded" values; need to shift them to make them fit for regs. 535 for (i = 0; i < NUM_BUF_RANGES - 1; i++) 536 reg_vals->pps.rc_buf_thresh[i] = reg_vals->pps.rc_buf_thresh[i] >> 6; 537 538 reg_vals->rc_buffer_model_size = dsc_params->rc_buffer_model_size; 539 reg_vals->ich_reset_at_eol = reg_vals->num_slices_h == 1 ? 0 : 0xf; 540 } 541 542 static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_values *reg_vals) 543 { 544 uint32_t temp_int; 545 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); 546 547 REG_SET(DSC_DEBUG_CONTROL, 0, 548 DSC_DBG_EN, reg_vals->dsc_dbg_en); 549 550 // dsccif registers 551 REG_SET_5(DSCCIF_CONFIG0, 0, 552 INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN, reg_vals->underflow_recovery_en, 553 INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN, reg_vals->underflow_occurred_int_en, 554 INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS, reg_vals->underflow_occurred_status, 555 INPUT_PIXEL_FORMAT, reg_vals->pixel_format, 556 DSCCIF_CONFIG0__BITS_PER_COMPONENT, reg_vals->pps.bits_per_component); 557 558 REG_SET_2(DSCCIF_CONFIG1, 0, 559 PIC_WIDTH, reg_vals->pps.pic_width, 560 PIC_HEIGHT, reg_vals->pps.pic_height); 561 562 // dscc registers 563 REG_SET_4(DSCC_CONFIG0, 0, 564 ICH_RESET_AT_END_OF_LINE, reg_vals->ich_reset_at_eol, 565 NUMBER_OF_SLICES_PER_LINE, reg_vals->num_slices_h - 1, 566 ALTERNATE_ICH_ENCODING_EN, reg_vals->alternate_ich_encoding_en, 567 NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION, reg_vals->num_slices_v - 1); 568 569 REG_SET(DSCC_CONFIG1, 0, 570 DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, reg_vals->rc_buffer_model_size); 571 /*REG_SET_2(DSCC_CONFIG1, 0, 572 DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, reg_vals->rc_buffer_model_size, 573 DSCC_DISABLE_ICH, reg_vals->disable_ich);*/ 574 575 REG_SET_4(DSCC_INTERRUPT_CONTROL_STATUS, 0, 576 DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN, reg_vals->rc_buffer_model_overflow_int_en[0], 577 DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN, reg_vals->rc_buffer_model_overflow_int_en[1], 578 DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN, reg_vals->rc_buffer_model_overflow_int_en[2], 579 DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN, reg_vals->rc_buffer_model_overflow_int_en[3]); 580 581 REG_SET_3(DSCC_PPS_CONFIG0, 0, 582 DSC_VERSION_MINOR, reg_vals->pps.dsc_version_minor, 583 LINEBUF_DEPTH, reg_vals->pps.line_buf_depth, 584 DSCC_PPS_CONFIG0__BITS_PER_COMPONENT, reg_vals->pps.bits_per_component); 585 586 if (reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420 || reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422) 587 temp_int = reg_vals->bpp_x32; 588 else 589 temp_int = reg_vals->bpp_x32 >> 1; 590 591 REG_SET_7(DSCC_PPS_CONFIG1, 0, 592 BITS_PER_PIXEL, temp_int, 593 SIMPLE_422, reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422, 594 CONVERT_RGB, reg_vals->pixel_format == DSC_PIXFMT_RGB, 595 BLOCK_PRED_ENABLE, reg_vals->pps.block_pred_enable, 596 NATIVE_422, reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422, 597 NATIVE_420, reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420, 598 CHUNK_SIZE, reg_vals->pps.slice_chunk_size); 599 600 REG_SET_2(DSCC_PPS_CONFIG2, 0, 601 PIC_WIDTH, reg_vals->pps.pic_width, 602 PIC_HEIGHT, reg_vals->pps.pic_height); 603 604 REG_SET_2(DSCC_PPS_CONFIG3, 0, 605 SLICE_WIDTH, reg_vals->pps.slice_width, 606 SLICE_HEIGHT, reg_vals->pps.slice_height); 607 608 REG_SET(DSCC_PPS_CONFIG4, 0, 609 INITIAL_XMIT_DELAY, reg_vals->pps.initial_xmit_delay); 610 611 REG_SET_2(DSCC_PPS_CONFIG5, 0, 612 INITIAL_SCALE_VALUE, reg_vals->pps.initial_scale_value, 613 SCALE_INCREMENT_INTERVAL, reg_vals->pps.scale_increment_interval); 614 615 REG_SET_3(DSCC_PPS_CONFIG6, 0, 616 SCALE_DECREMENT_INTERVAL, reg_vals->pps.scale_decrement_interval, 617 FIRST_LINE_BPG_OFFSET, reg_vals->pps.first_line_bpg_offset, 618 SECOND_LINE_BPG_OFFSET, reg_vals->pps.second_line_bpg_offset); 619 620 REG_SET_2(DSCC_PPS_CONFIG7, 0, 621 NFL_BPG_OFFSET, reg_vals->pps.nfl_bpg_offset, 622 SLICE_BPG_OFFSET, reg_vals->pps.slice_bpg_offset); 623 624 REG_SET_2(DSCC_PPS_CONFIG8, 0, 625 NSL_BPG_OFFSET, reg_vals->pps.nsl_bpg_offset, 626 SECOND_LINE_OFFSET_ADJ, reg_vals->pps.second_line_offset_adj); 627 628 REG_SET_2(DSCC_PPS_CONFIG9, 0, 629 INITIAL_OFFSET, reg_vals->pps.initial_offset, 630 FINAL_OFFSET, reg_vals->pps.final_offset); 631 632 REG_SET_3(DSCC_PPS_CONFIG10, 0, 633 FLATNESS_MIN_QP, reg_vals->pps.flatness_min_qp, 634 FLATNESS_MAX_QP, reg_vals->pps.flatness_max_qp, 635 RC_MODEL_SIZE, reg_vals->pps.rc_model_size); 636 637 REG_SET_5(DSCC_PPS_CONFIG11, 0, 638 RC_EDGE_FACTOR, reg_vals->pps.rc_edge_factor, 639 RC_QUANT_INCR_LIMIT0, reg_vals->pps.rc_quant_incr_limit0, 640 RC_QUANT_INCR_LIMIT1, reg_vals->pps.rc_quant_incr_limit1, 641 RC_TGT_OFFSET_LO, reg_vals->pps.rc_tgt_offset_low, 642 RC_TGT_OFFSET_HI, reg_vals->pps.rc_tgt_offset_high); 643 644 REG_SET_4(DSCC_PPS_CONFIG12, 0, 645 RC_BUF_THRESH0, reg_vals->pps.rc_buf_thresh[0], 646 RC_BUF_THRESH1, reg_vals->pps.rc_buf_thresh[1], 647 RC_BUF_THRESH2, reg_vals->pps.rc_buf_thresh[2], 648 RC_BUF_THRESH3, reg_vals->pps.rc_buf_thresh[3]); 649 650 REG_SET_4(DSCC_PPS_CONFIG13, 0, 651 RC_BUF_THRESH4, reg_vals->pps.rc_buf_thresh[4], 652 RC_BUF_THRESH5, reg_vals->pps.rc_buf_thresh[5], 653 RC_BUF_THRESH6, reg_vals->pps.rc_buf_thresh[6], 654 RC_BUF_THRESH7, reg_vals->pps.rc_buf_thresh[7]); 655 656 REG_SET_4(DSCC_PPS_CONFIG14, 0, 657 RC_BUF_THRESH8, reg_vals->pps.rc_buf_thresh[8], 658 RC_BUF_THRESH9, reg_vals->pps.rc_buf_thresh[9], 659 RC_BUF_THRESH10, reg_vals->pps.rc_buf_thresh[10], 660 RC_BUF_THRESH11, reg_vals->pps.rc_buf_thresh[11]); 661 662 REG_SET_5(DSCC_PPS_CONFIG15, 0, 663 RC_BUF_THRESH12, reg_vals->pps.rc_buf_thresh[12], 664 RC_BUF_THRESH13, reg_vals->pps.rc_buf_thresh[13], 665 RANGE_MIN_QP0, reg_vals->pps.rc_range_params[0].range_min_qp, 666 RANGE_MAX_QP0, reg_vals->pps.rc_range_params[0].range_max_qp, 667 RANGE_BPG_OFFSET0, reg_vals->pps.rc_range_params[0].range_bpg_offset); 668 669 REG_SET_6(DSCC_PPS_CONFIG16, 0, 670 RANGE_MIN_QP1, reg_vals->pps.rc_range_params[1].range_min_qp, 671 RANGE_MAX_QP1, reg_vals->pps.rc_range_params[1].range_max_qp, 672 RANGE_BPG_OFFSET1, reg_vals->pps.rc_range_params[1].range_bpg_offset, 673 RANGE_MIN_QP2, reg_vals->pps.rc_range_params[2].range_min_qp, 674 RANGE_MAX_QP2, reg_vals->pps.rc_range_params[2].range_max_qp, 675 RANGE_BPG_OFFSET2, reg_vals->pps.rc_range_params[2].range_bpg_offset); 676 677 REG_SET_6(DSCC_PPS_CONFIG17, 0, 678 RANGE_MIN_QP3, reg_vals->pps.rc_range_params[3].range_min_qp, 679 RANGE_MAX_QP3, reg_vals->pps.rc_range_params[3].range_max_qp, 680 RANGE_BPG_OFFSET3, reg_vals->pps.rc_range_params[3].range_bpg_offset, 681 RANGE_MIN_QP4, reg_vals->pps.rc_range_params[4].range_min_qp, 682 RANGE_MAX_QP4, reg_vals->pps.rc_range_params[4].range_max_qp, 683 RANGE_BPG_OFFSET4, reg_vals->pps.rc_range_params[4].range_bpg_offset); 684 685 REG_SET_6(DSCC_PPS_CONFIG18, 0, 686 RANGE_MIN_QP5, reg_vals->pps.rc_range_params[5].range_min_qp, 687 RANGE_MAX_QP5, reg_vals->pps.rc_range_params[5].range_max_qp, 688 RANGE_BPG_OFFSET5, reg_vals->pps.rc_range_params[5].range_bpg_offset, 689 RANGE_MIN_QP6, reg_vals->pps.rc_range_params[6].range_min_qp, 690 RANGE_MAX_QP6, reg_vals->pps.rc_range_params[6].range_max_qp, 691 RANGE_BPG_OFFSET6, reg_vals->pps.rc_range_params[6].range_bpg_offset); 692 693 REG_SET_6(DSCC_PPS_CONFIG19, 0, 694 RANGE_MIN_QP7, reg_vals->pps.rc_range_params[7].range_min_qp, 695 RANGE_MAX_QP7, reg_vals->pps.rc_range_params[7].range_max_qp, 696 RANGE_BPG_OFFSET7, reg_vals->pps.rc_range_params[7].range_bpg_offset, 697 RANGE_MIN_QP8, reg_vals->pps.rc_range_params[8].range_min_qp, 698 RANGE_MAX_QP8, reg_vals->pps.rc_range_params[8].range_max_qp, 699 RANGE_BPG_OFFSET8, reg_vals->pps.rc_range_params[8].range_bpg_offset); 700 701 REG_SET_6(DSCC_PPS_CONFIG20, 0, 702 RANGE_MIN_QP9, reg_vals->pps.rc_range_params[9].range_min_qp, 703 RANGE_MAX_QP9, reg_vals->pps.rc_range_params[9].range_max_qp, 704 RANGE_BPG_OFFSET9, reg_vals->pps.rc_range_params[9].range_bpg_offset, 705 RANGE_MIN_QP10, reg_vals->pps.rc_range_params[10].range_min_qp, 706 RANGE_MAX_QP10, reg_vals->pps.rc_range_params[10].range_max_qp, 707 RANGE_BPG_OFFSET10, reg_vals->pps.rc_range_params[10].range_bpg_offset); 708 709 REG_SET_6(DSCC_PPS_CONFIG21, 0, 710 RANGE_MIN_QP11, reg_vals->pps.rc_range_params[11].range_min_qp, 711 RANGE_MAX_QP11, reg_vals->pps.rc_range_params[11].range_max_qp, 712 RANGE_BPG_OFFSET11, reg_vals->pps.rc_range_params[11].range_bpg_offset, 713 RANGE_MIN_QP12, reg_vals->pps.rc_range_params[12].range_min_qp, 714 RANGE_MAX_QP12, reg_vals->pps.rc_range_params[12].range_max_qp, 715 RANGE_BPG_OFFSET12, reg_vals->pps.rc_range_params[12].range_bpg_offset); 716 717 REG_SET_6(DSCC_PPS_CONFIG22, 0, 718 RANGE_MIN_QP13, reg_vals->pps.rc_range_params[13].range_min_qp, 719 RANGE_MAX_QP13, reg_vals->pps.rc_range_params[13].range_max_qp, 720 RANGE_BPG_OFFSET13, reg_vals->pps.rc_range_params[13].range_bpg_offset, 721 RANGE_MIN_QP14, reg_vals->pps.rc_range_params[14].range_min_qp, 722 RANGE_MAX_QP14, reg_vals->pps.rc_range_params[14].range_max_qp, 723 RANGE_BPG_OFFSET14, reg_vals->pps.rc_range_params[14].range_bpg_offset); 724 725 if (IS_FPGA_MAXIMUS_DC(dsc20->base.ctx->dce_environment)) { 726 /* It's safe to do this as long as debug bus is not being used in DAL Diag environment. 727 * 728 * This is because DSCC_PPS_CONFIG4.INITIAL_DEC_DELAY is a read-only register field (because it's a decoder 729 * value not required by DSC encoder). However, since decoding fails when this value is missing from PPS, it's 730 * required to communicate this value to the PPS header. When testing on FPGA, the values for PPS header are 731 * being read from Diag register dump. The register below is used in place of a scratch register to make 732 * 'initial_dec_delay' available. 733 */ 734 735 temp_int = reg_vals->pps.initial_dec_delay; 736 REG_SET_4(DSCC_TEST_DEBUG_BUS_ROTATE, 0, 737 DSCC_TEST_DEBUG_BUS0_ROTATE, temp_int & 0x1f, 738 DSCC_TEST_DEBUG_BUS1_ROTATE, temp_int >> 5 & 0x1f, 739 DSCC_TEST_DEBUG_BUS2_ROTATE, temp_int >> 10 & 0x1f, 740 DSCC_TEST_DEBUG_BUS3_ROTATE, temp_int >> 15 & 0x1); 741 } 742 } 743 744
Indexes created Sat Sep 20 22:09:52 GMT 2025