1 /* $NetBSD: dcn10_dwb.c,v 1.2 2021/12/18 23:45:03 riastradh Exp $ */ 2 3 /* 4 * Copyright 2012-17 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: AMD 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: dcn10_dwb.c,v 1.2 2021/12/18 23:45:03 riastradh Exp $"); 30 31 #if defined(CONFIG_DRM_AMD_DC_DCN) 32 33 #include "reg_helper.h" 34 #include "resource.h" 35 #include "dwb.h" 36 #include "dcn10_dwb.h" 37 38 39 #define REG(reg)\ 40 dwbc10->dwbc_regs->reg 41 42 #define CTX \ 43 dwbc10->base.ctx 44 45 #undef FN 46 #define FN(reg_name, field_name) \ 47 dwbc10->dwbc_shift->field_name, dwbc10->dwbc_mask->field_name 48 49 #define TO_DCN10_DWBC(dwbc_base) \ 50 container_of(dwbc_base, struct dcn10_dwbc, base) 51 52 static bool dwb1_get_caps(struct dwbc *dwbc, struct dwb_caps *caps) 53 { 54 if (caps) { 55 caps->adapter_id = 0; /* we only support 1 adapter currently */ 56 caps->hw_version = DCN_VERSION_1_0; 57 caps->num_pipes = 2; 58 memset(&caps->reserved, 0, sizeof(caps->reserved)); 59 memset(&caps->reserved2, 0, sizeof(caps->reserved2)); 60 caps->sw_version = dwb_ver_1_0; 61 caps->caps.support_dwb = true; 62 caps->caps.support_ogam = false; 63 caps->caps.support_wbscl = true; 64 caps->caps.support_ocsc = false; 65 return true; 66 } else { 67 return false; 68 } 69 } 70 71 static bool dwb1_enable(struct dwbc *dwbc, struct dc_dwb_params *params) 72 { 73 struct dcn10_dwbc *dwbc10 = TO_DCN10_DWBC(dwbc); 74 75 /* disable first. */ 76 dwbc->funcs->disable(dwbc); 77 78 /* disable power gating */ 79 REG_UPDATE_5(WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, 1, 80 DISPCLK_G_WB_GATE_DIS, 1, DISPCLK_G_WBSCL_GATE_DIS, 1, 81 WB_LB_LS_DIS, 1, WB_LUT_LS_DIS, 1); 82 83 REG_UPDATE(WB_ENABLE, WB_ENABLE, 1); 84 85 return true; 86 } 87 88 static bool dwb1_disable(struct dwbc *dwbc) 89 { 90 struct dcn10_dwbc *dwbc10 = TO_DCN10_DWBC(dwbc); 91 92 /* disable CNV */ 93 REG_UPDATE(CNV_MODE, CNV_FRAME_CAPTURE_EN, 0); 94 95 /* disable WB */ 96 REG_UPDATE(WB_ENABLE, WB_ENABLE, 0); 97 98 /* soft reset */ 99 REG_UPDATE(WB_SOFT_RESET, WB_SOFT_RESET, 1); 100 REG_UPDATE(WB_SOFT_RESET, WB_SOFT_RESET, 0); 101 102 /* enable power gating */ 103 REG_UPDATE_5(WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, 0, 104 DISPCLK_G_WB_GATE_DIS, 0, DISPCLK_G_WBSCL_GATE_DIS, 0, 105 WB_LB_LS_DIS, 0, WB_LUT_LS_DIS, 0); 106 107 return true; 108 } 109 110 const struct dwbc_funcs dcn10_dwbc_funcs = { 111 .get_caps = dwb1_get_caps, 112 .enable = dwb1_enable, 113 .disable = dwb1_disable, 114 .update = NULL, 115 .set_stereo = NULL, 116 .set_new_content = NULL, 117 .set_warmup = NULL, 118 .dwb_set_scaler = NULL, 119 }; 120 121 void dcn10_dwbc_construct(struct dcn10_dwbc *dwbc10, 122 struct dc_context *ctx, 123 const struct dcn10_dwbc_registers *dwbc_regs, 124 const struct dcn10_dwbc_shift *dwbc_shift, 125 const struct dcn10_dwbc_mask *dwbc_mask, 126 int inst) 127 { 128 dwbc10->base.ctx = ctx; 129 130 dwbc10->base.inst = inst; 131 dwbc10->base.funcs = &dcn10_dwbc_funcs; 132 133 dwbc10->dwbc_regs = dwbc_regs; 134 dwbc10->dwbc_shift = dwbc_shift; 135 dwbc10->dwbc_mask = dwbc_mask; 136 } 137 138 139 #endif 140