1 /* $NetBSD: dwc2_hcdintr.c,v 1.16 2025/04/12 08:22:31 mlelstv Exp $ */ 2 3 /* 4 * hcd_intr.c - DesignWare HS OTG Controller host-mode interrupt handling 5 * 6 * Copyright (C) 2004-2013 Synopsys, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The names of the above-listed copyright holders may not be used 18 * to endorse or promote products derived from this software without 19 * specific prior written permission. 20 * 21 * ALTERNATIVELY, this software may be distributed under the terms of the 22 * GNU General Public License ("GPL") as published by the Free Software 23 * Foundation; either version 2 of the License, or (at your option) any 24 * later version. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * This file contains the interrupt handlers for Host mode 41 */ 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: dwc2_hcdintr.c,v 1.16 2025/04/12 08:22:31 mlelstv Exp $"); 44 45 #include <sys/types.h> 46 #include <sys/pool.h> 47 48 #include <dev/usb/usb.h> 49 #include <dev/usb/usbdi.h> 50 #include <dev/usb/usbdivar.h> 51 #include <dev/usb/usb_mem.h> 52 53 #include <machine/param.h> 54 55 #include <linux/kernel.h> 56 57 #include <dwc2/dwc2.h> 58 #include <dwc2/dwc2var.h> 59 60 #include "dwc2_core.h" 61 #include "dwc2_hcd.h" 62 63 /* 64 * If we get this many NAKs on a split transaction we'll slow down 65 * retransmission. A 1 here means delay after the first NAK. 66 */ 67 #define DWC2_NAKS_BEFORE_DELAY 3 68 int dwc2_naks_before_delay = DWC2_NAKS_BEFORE_DELAY; 69 70 #define DWC2_OUT_NAKS_BEFORE_DELAY 1 71 int dwc2_out_naks_before_delay = DWC2_OUT_NAKS_BEFORE_DELAY; 72 73 /* This function is for debug only */ 74 static void dwc2_track_missed_sofs(struct dwc2_hsotg *hsotg) 75 { 76 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 77 u16 curr_frame_number = hsotg->frame_number; 78 79 if (hsotg->frame_num_idx < FRAME_NUM_ARRAY_SIZE) { 80 if (((hsotg->last_frame_num + 1) & HFNUM_MAX_FRNUM) != 81 curr_frame_number) { 82 hsotg->frame_num_array[hsotg->frame_num_idx] = 83 curr_frame_number; 84 hsotg->last_frame_num_array[hsotg->frame_num_idx] = 85 hsotg->last_frame_num; 86 hsotg->frame_num_idx++; 87 } 88 } else if (!hsotg->dumped_frame_num_array) { 89 int i; 90 91 dev_info(hsotg->dev, "Frame Last Frame\n"); 92 dev_info(hsotg->dev, "----- ----------\n"); 93 for (i = 0; i < FRAME_NUM_ARRAY_SIZE; i++) { 94 dev_info(hsotg->dev, "0x%04x 0x%04x\n", 95 hsotg->frame_num_array[i], 96 hsotg->last_frame_num_array[i]); 97 } 98 hsotg->dumped_frame_num_array = 1; 99 } 100 hsotg->last_frame_num = curr_frame_number; 101 #endif 102 } 103 104 static void dwc2_hc_handle_tt_clear(struct dwc2_hsotg *hsotg, 105 struct dwc2_host_chan *chan, 106 struct dwc2_qtd *qtd) 107 { 108 // struct urb *usb_urb; 109 110 if (!chan->qh) 111 return; 112 113 if (chan->qh->dev_speed == USB_SPEED_HIGH) 114 return; 115 116 if (!qtd->urb) 117 return; 118 119 120 if (qtd->urb->status != -EPIPE && qtd->urb->status != -EREMOTEIO) { 121 chan->qh->tt_buffer_dirty = 1; 122 chan->qh->tt_buffer_dirty = 0; 123 } 124 } 125 126 /* 127 * Handles the start-of-frame interrupt in host mode. Non-periodic 128 * transactions may be queued to the DWC_otg controller for the current 129 * (micro)frame. Periodic transactions may be queued to the controller 130 * for the next (micro)frame. 131 */ 132 static void dwc2_sof_intr(struct dwc2_hsotg *hsotg) 133 { 134 struct list_head *qh_entry; 135 struct dwc2_qh *qh; 136 enum dwc2_transaction_type tr_type; 137 138 /* Clear interrupt */ 139 DWC2_WRITE_4(hsotg, GINTSTS, GINTSTS_SOF); 140 141 #ifdef DEBUG_SOF 142 dev_vdbg(hsotg->dev, "--Start of Frame Interrupt--\n"); 143 #endif 144 145 hsotg->frame_number = dwc2_hcd_get_frame_number(hsotg); 146 147 dwc2_track_missed_sofs(hsotg); 148 149 /* Determine whether any periodic QHs should be executed */ 150 qh_entry = hsotg->periodic_sched_inactive.next; 151 while (qh_entry != &hsotg->periodic_sched_inactive) { 152 qh = list_entry(qh_entry, struct dwc2_qh, qh_list_entry); 153 qh_entry = qh_entry->next; 154 if (dwc2_frame_num_le(qh->sched_frame, hsotg->frame_number)) 155 /* 156 * Move QH to the ready list to be executed next 157 * (micro)frame 158 */ 159 list_move(&qh->qh_list_entry, 160 &hsotg->periodic_sched_ready); 161 } 162 tr_type = dwc2_hcd_select_transactions(hsotg); 163 if (tr_type != DWC2_TRANSACTION_NONE) 164 dwc2_hcd_queue_transactions(hsotg, tr_type); 165 } 166 167 /* 168 * Handles the Rx FIFO Level Interrupt, which indicates that there is 169 * at least one packet in the Rx FIFO. The packets are moved from the FIFO to 170 * memory if the DWC_otg controller is operating in Slave mode. 171 */ 172 static void dwc2_rx_fifo_level_intr(struct dwc2_hsotg *hsotg) 173 { 174 u32 grxsts, chnum, bcnt, pktsts; 175 struct dwc2_host_chan *chan; 176 177 if (dbg_perio()) 178 dev_vdbg(hsotg->dev, "--RxFIFO Level Interrupt--\n"); 179 180 grxsts = DWC2_READ_4(hsotg, GRXSTSP); 181 chnum = (grxsts & GRXSTS_HCHNUM_MASK) >> GRXSTS_HCHNUM_SHIFT; 182 chan = hsotg->hc_ptr_array[chnum]; 183 if (!chan) { 184 dev_err(hsotg->dev, "Unable to get corresponding channel\n"); 185 return; 186 } 187 188 bcnt = (grxsts & GRXSTS_BYTECNT_MASK) >> GRXSTS_BYTECNT_SHIFT; 189 pktsts = (grxsts & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT; 190 191 /* Packet Status */ 192 if (dbg_perio()) { 193 dev_vdbg(hsotg->dev, " Ch num = %d\n", chnum); 194 dev_vdbg(hsotg->dev, " Count = %d\n", bcnt); 195 dev_vdbg(hsotg->dev, " DPID = %d, chan.dpid = %d\n", 196 (grxsts & GRXSTS_DPID_MASK) >> GRXSTS_DPID_SHIFT, 197 chan->data_pid_start); 198 dev_vdbg(hsotg->dev, " PStatus = %d\n", pktsts); 199 } 200 201 switch (pktsts) { 202 case GRXSTS_PKTSTS_HCHIN: 203 /* Read the data into the host buffer */ 204 if (bcnt > 0) { 205 dwc2_read_packet(hsotg, chan->xfer_buf, bcnt); 206 207 /* Update the HC fields for the next packet received */ 208 chan->xfer_count += bcnt; 209 chan->xfer_buf += bcnt; 210 } 211 break; 212 case GRXSTS_PKTSTS_HCHIN_XFER_COMP: 213 case GRXSTS_PKTSTS_DATATOGGLEERR: 214 case GRXSTS_PKTSTS_HCHHALTED: 215 /* Handled in interrupt, just ignore data */ 216 break; 217 default: 218 dev_err(hsotg->dev, 219 "RxFIFO Level Interrupt: Unknown status %d\n", pktsts); 220 break; 221 } 222 } 223 224 /* 225 * This interrupt occurs when the non-periodic Tx FIFO is half-empty. More 226 * data packets may be written to the FIFO for OUT transfers. More requests 227 * may be written to the non-periodic request queue for IN transfers. This 228 * interrupt is enabled only in Slave mode. 229 */ 230 static void dwc2_np_tx_fifo_empty_intr(struct dwc2_hsotg *hsotg) 231 { 232 dev_vdbg(hsotg->dev, "--Non-Periodic TxFIFO Empty Interrupt--\n"); 233 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_NON_PERIODIC); 234 } 235 236 /* 237 * This interrupt occurs when the periodic Tx FIFO is half-empty. More data 238 * packets may be written to the FIFO for OUT transfers. More requests may be 239 * written to the periodic request queue for IN transfers. This interrupt is 240 * enabled only in Slave mode. 241 */ 242 static void dwc2_perio_tx_fifo_empty_intr(struct dwc2_hsotg *hsotg) 243 { 244 if (dbg_perio()) 245 dev_vdbg(hsotg->dev, "--Periodic TxFIFO Empty Interrupt--\n"); 246 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_PERIODIC); 247 } 248 249 static void dwc2_hprt0_enable(struct dwc2_hsotg *hsotg, u32 hprt0, 250 u32 *hprt0_modify) 251 { 252 struct dwc2_core_params *params = hsotg->core_params; 253 int do_reset = 0; 254 u32 usbcfg; 255 u32 prtspd; 256 u32 hcfg; 257 u32 fslspclksel; 258 u32 hfir; 259 260 dev_vdbg(hsotg->dev, "%s(%p)\n", __func__, hsotg); 261 262 /* Every time when port enables calculate HFIR.FrInterval */ 263 hfir = DWC2_READ_4(hsotg, HFIR); 264 hfir &= ~HFIR_FRINT_MASK; 265 hfir |= dwc2_calc_frame_interval(hsotg) << HFIR_FRINT_SHIFT & 266 HFIR_FRINT_MASK; 267 DWC2_WRITE_4(hsotg, HFIR, hfir); 268 269 /* Check if we need to adjust the PHY clock speed for low power */ 270 if (!params->host_support_fs_ls_low_power) { 271 /* Port has been enabled, set the reset change flag */ 272 hsotg->flags.b.port_reset_change = 1; 273 274 dwc2_root_intr(hsotg->hsotg_sc); 275 return; 276 } 277 278 usbcfg = DWC2_READ_4(hsotg, GUSBCFG); 279 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; 280 281 if (prtspd == HPRT0_SPD_LOW_SPEED || prtspd == HPRT0_SPD_FULL_SPEED) { 282 /* Low power */ 283 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL)) { 284 /* Set PHY low power clock select for FS/LS devices */ 285 usbcfg |= GUSBCFG_PHY_LP_CLK_SEL; 286 DWC2_WRITE_4(hsotg, GUSBCFG, usbcfg); 287 do_reset = 1; 288 } 289 290 hcfg = DWC2_READ_4(hsotg, HCFG); 291 fslspclksel = (hcfg & HCFG_FSLSPCLKSEL_MASK) >> 292 HCFG_FSLSPCLKSEL_SHIFT; 293 294 if (prtspd == HPRT0_SPD_LOW_SPEED && 295 params->host_ls_low_power_phy_clk == 296 DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ) { 297 /* 6 MHZ */ 298 dev_vdbg(hsotg->dev, 299 "FS_PHY programming HCFG to 6 MHz\n"); 300 if (fslspclksel != HCFG_FSLSPCLKSEL_6_MHZ) { 301 fslspclksel = HCFG_FSLSPCLKSEL_6_MHZ; 302 hcfg &= ~HCFG_FSLSPCLKSEL_MASK; 303 hcfg |= fslspclksel << HCFG_FSLSPCLKSEL_SHIFT; 304 DWC2_WRITE_4(hsotg, HCFG, hcfg); 305 do_reset = 1; 306 } 307 } else { 308 /* 48 MHZ */ 309 dev_vdbg(hsotg->dev, 310 "FS_PHY programming HCFG to 48 MHz\n"); 311 if (fslspclksel != HCFG_FSLSPCLKSEL_48_MHZ) { 312 fslspclksel = HCFG_FSLSPCLKSEL_48_MHZ; 313 hcfg &= ~HCFG_FSLSPCLKSEL_MASK; 314 hcfg |= fslspclksel << HCFG_FSLSPCLKSEL_SHIFT; 315 DWC2_WRITE_4(hsotg, HCFG, hcfg); 316 do_reset = 1; 317 } 318 } 319 } else { 320 /* Not low power */ 321 if (usbcfg & GUSBCFG_PHY_LP_CLK_SEL) { 322 usbcfg &= ~GUSBCFG_PHY_LP_CLK_SEL; 323 DWC2_WRITE_4(hsotg, GUSBCFG, usbcfg); 324 do_reset = 1; 325 } 326 } 327 328 if (do_reset) { 329 *hprt0_modify |= HPRT0_RST; 330 DWC2_WRITE_4(hsotg, HPRT0, *hprt0_modify); 331 queue_delayed_work(hsotg->wq_otg, &hsotg->reset_work, 332 msecs_to_jiffies(60)); 333 } else { 334 /* Port has been enabled, set the reset change flag */ 335 hsotg->flags.b.port_reset_change = 1; 336 dwc2_root_intr(hsotg->hsotg_sc); 337 338 } 339 } 340 341 /* 342 * There are multiple conditions that can cause a port interrupt. This function 343 * determines which interrupt conditions have occurred and handles them 344 * appropriately. 345 */ 346 static void dwc2_port_intr(struct dwc2_hsotg *hsotg) 347 { 348 u32 hprt0; 349 u32 hprt0_modify; 350 351 dev_vdbg(hsotg->dev, "--Port Interrupt--\n"); 352 353 hprt0 = DWC2_READ_4(hsotg, HPRT0); 354 hprt0_modify = hprt0; 355 356 /* 357 * Clear appropriate bits in HPRT0 to clear the interrupt bit in 358 * GINTSTS 359 */ 360 hprt0_modify &= ~(HPRT0_ENA | HPRT0_CONNDET | HPRT0_ENACHG | 361 HPRT0_OVRCURRCHG); 362 363 /* 364 * Port Connect Detected 365 * Set flag and clear if detected 366 */ 367 if (hprt0 & HPRT0_CONNDET) { 368 DWC2_WRITE_4(hsotg, HPRT0, hprt0_modify | HPRT0_CONNDET); 369 370 dev_vdbg(hsotg->dev, 371 "--Port Interrupt HPRT0=0x%08x Port Connect Detected--\n", 372 hprt0); 373 dwc2_hcd_connect(hsotg); 374 375 /* 376 * The Hub driver asserts a reset when it sees port connect 377 * status change flag 378 */ 379 } 380 381 /* 382 * Port Enable Changed 383 * Clear if detected - Set internal flag if disabled 384 */ 385 if (hprt0 & HPRT0_ENACHG) { 386 DWC2_WRITE_4(hsotg, HPRT0, hprt0_modify | HPRT0_ENACHG); 387 dev_vdbg(hsotg->dev, 388 " --Port Interrupt HPRT0=0x%08x Port Enable Changed (now %d)--\n", 389 hprt0, !!(hprt0 & HPRT0_ENA)); 390 if (hprt0 & HPRT0_ENA) { 391 hsotg->new_connection = true; 392 dwc2_hprt0_enable(hsotg, hprt0, &hprt0_modify); 393 } else { 394 hsotg->flags.b.port_enable_change = 1; 395 if (hsotg->core_params->dma_desc_fs_enable) { 396 u32 hcfg; 397 398 hsotg->core_params->dma_desc_enable = 0; 399 hsotg->new_connection = false; 400 hcfg = DWC2_READ_4(hsotg, HCFG); 401 hcfg &= ~HCFG_DESCDMA; 402 DWC2_WRITE_4(hsotg, HCFG, hcfg); 403 } 404 } 405 } 406 407 /* Overcurrent Change Interrupt */ 408 if (hprt0 & HPRT0_OVRCURRCHG) { 409 DWC2_WRITE_4(hsotg, HPRT0, hprt0_modify | HPRT0_OVRCURRCHG); 410 dev_vdbg(hsotg->dev, 411 " --Port Interrupt HPRT0=0x%08x Port Overcurrent Changed--\n", 412 hprt0); 413 hsotg->flags.b.port_over_current_change = 1; 414 } 415 416 if (hsotg->flags.b.port_connect_status_change || 417 hsotg->flags.b.port_enable_change || 418 hsotg->flags.b.port_over_current_change) 419 dwc2_root_intr(hsotg->hsotg_sc); 420 } 421 422 /* 423 * Gets the actual length of a transfer after the transfer halts. halt_status 424 * holds the reason for the halt. 425 * 426 * For IN transfers where halt_status is DWC2_HC_XFER_COMPLETE, *short_read 427 * is set to 1 upon return if less than the requested number of bytes were 428 * transferred. short_read may also be NULL on entry, in which case it remains 429 * unchanged. 430 */ 431 static u32 dwc2_get_actual_xfer_length(struct dwc2_hsotg *hsotg, 432 struct dwc2_host_chan *chan, int chnum, 433 struct dwc2_qtd *qtd, 434 enum dwc2_halt_status halt_status, 435 int *short_read) 436 { 437 u32 hctsiz, count, length; 438 439 hctsiz = DWC2_READ_4(hsotg, HCTSIZ(chnum)); 440 441 if (halt_status == DWC2_HC_XFER_COMPLETE) { 442 if (chan->ep_is_in) { 443 count = (hctsiz & TSIZ_XFERSIZE_MASK) >> 444 TSIZ_XFERSIZE_SHIFT; 445 length = chan->xfer_len - count; 446 if (short_read != NULL) 447 *short_read = (count != 0); 448 } else if (chan->qh->do_split) { 449 length = qtd->ssplit_out_xfer_count; 450 } else { 451 length = chan->xfer_len; 452 } 453 } else { 454 /* 455 * Must use the hctsiz.pktcnt field to determine how much data 456 * has been transferred. This field reflects the number of 457 * packets that have been transferred via the USB. This is 458 * always an integral number of packets if the transfer was 459 * halted before its normal completion. (Can't use the 460 * hctsiz.xfersize field because that reflects the number of 461 * bytes transferred via the AHB, not the USB). 462 */ 463 count = (hctsiz & TSIZ_PKTCNT_MASK) >> TSIZ_PKTCNT_SHIFT; 464 length = (chan->start_pkt_count - count) * chan->max_packet; 465 } 466 467 return length; 468 } 469 470 /** 471 * dwc2_update_urb_state() - Updates the state of the URB after a Transfer 472 * Complete interrupt on the host channel. Updates the actual_length field 473 * of the URB based on the number of bytes transferred via the host channel. 474 * Sets the URB status if the data transfer is finished. 475 * 476 * Return: 1 if the data transfer specified by the URB is completely finished, 477 * 0 otherwise 478 */ 479 static int dwc2_update_urb_state(struct dwc2_hsotg *hsotg, 480 struct dwc2_host_chan *chan, int chnum, 481 struct dwc2_hcd_urb *urb, 482 struct dwc2_qtd *qtd) 483 { 484 int xfer_done = 0; 485 int short_read = 0; 486 int xfer_length = dwc2_get_actual_xfer_length(hsotg, chan, chnum, qtd, 487 DWC2_HC_XFER_COMPLETE, 488 &short_read); 489 490 if (urb->actual_length + xfer_length > urb->length) { 491 dev_warn(hsotg->dev, "%s(): trimming xfer length\n", __func__); 492 xfer_length = urb->length - urb->actual_length; 493 } 494 495 /* Non DWORD-aligned buffer case handling */ 496 if (chan->align_buf && xfer_length) { 497 dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n", __func__); 498 usb_syncmem(urb->usbdma, 0, chan->qh->dw_align_buf_size, 499 chan->ep_is_in ? 500 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 501 if (chan->ep_is_in) 502 memcpy(urb->buf + urb->actual_length, 503 chan->qh->dw_align_buf, xfer_length); 504 usb_syncmem(urb->usbdma, 0, chan->qh->dw_align_buf_size, 505 chan->ep_is_in ? 506 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 507 } 508 509 dev_vdbg(hsotg->dev, "urb->actual_length=%d xfer_length=%d\n", 510 urb->actual_length, xfer_length); 511 urb->actual_length += xfer_length; 512 513 if (xfer_length && chan->ep_type == USB_ENDPOINT_XFER_BULK && 514 (urb->flags & URB_SEND_ZERO_PACKET) && 515 urb->actual_length >= urb->length && 516 !(urb->length % chan->max_packet)) { 517 xfer_done = 0; 518 } else if (short_read || urb->actual_length >= urb->length) { 519 xfer_done = 1; 520 urb->status = 0; 521 } 522 523 dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n", 524 __func__, (chan->ep_is_in ? "IN" : "OUT"), chnum); 525 dev_vdbg(hsotg->dev, " chan->xfer_len %d\n", chan->xfer_len); 526 dev_vdbg(hsotg->dev, " hctsiz.xfersize %d\n", 527 (DWC2_READ_4(hsotg, HCTSIZ(chnum)) & TSIZ_XFERSIZE_MASK) >> TSIZ_XFERSIZE_SHIFT); 528 dev_vdbg(hsotg->dev, " urb->transfer_buffer_length %d\n", urb->length); 529 dev_vdbg(hsotg->dev, " urb->actual_length %d\n", urb->actual_length); 530 dev_vdbg(hsotg->dev, " short_read %d, xfer_done %d\n", short_read, 531 xfer_done); 532 533 return xfer_done; 534 } 535 536 /* 537 * Save the starting data toggle for the next transfer. The data toggle is 538 * saved in the QH for non-control transfers and it's saved in the QTD for 539 * control transfers. 540 */ 541 void dwc2_hcd_save_data_toggle(struct dwc2_hsotg *hsotg, 542 struct dwc2_host_chan *chan, int chnum, 543 struct dwc2_qtd *qtd) 544 { 545 u32 hctsiz = DWC2_READ_4(hsotg, HCTSIZ(chnum)); 546 u32 pid = (hctsiz & TSIZ_SC_MC_PID_MASK) >> TSIZ_SC_MC_PID_SHIFT; 547 548 if (chan->ep_type != USB_ENDPOINT_XFER_CONTROL) { 549 if (pid == TSIZ_SC_MC_PID_DATA0) 550 chan->qh->data_toggle = DWC2_HC_PID_DATA0; 551 else 552 chan->qh->data_toggle = DWC2_HC_PID_DATA1; 553 } else { 554 if (pid == TSIZ_SC_MC_PID_DATA0) 555 qtd->data_toggle = DWC2_HC_PID_DATA0; 556 else 557 qtd->data_toggle = DWC2_HC_PID_DATA1; 558 } 559 } 560 561 /** 562 * dwc2_update_isoc_urb_state() - Updates the state of an Isochronous URB when 563 * the transfer is stopped for any reason. The fields of the current entry in 564 * the frame descriptor array are set based on the transfer state and the input 565 * halt_status. Completes the Isochronous URB if all the URB frames have been 566 * completed. 567 * 568 * Return: DWC2_HC_XFER_COMPLETE if there are more frames remaining to be 569 * transferred in the URB. Otherwise return DWC2_HC_XFER_URB_COMPLETE. 570 */ 571 static enum dwc2_halt_status dwc2_update_isoc_urb_state( 572 struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan, 573 int chnum, struct dwc2_qtd *qtd, 574 enum dwc2_halt_status halt_status) 575 { 576 struct dwc2_hcd_iso_packet_desc *frame_desc; 577 struct dwc2_hcd_urb *urb = qtd->urb; 578 u32 len; 579 580 if (!urb) 581 return DWC2_HC_XFER_NO_HALT_STATUS; 582 583 frame_desc = &urb->iso_descs[qtd->isoc_frame_index]; 584 585 switch (halt_status) { 586 case DWC2_HC_XFER_COMPLETE: 587 frame_desc->status = 0; 588 len = dwc2_get_actual_xfer_length(hsotg, 589 chan, chnum, qtd, halt_status, NULL); 590 591 /* Non DWORD-aligned buffer case handling */ 592 if (chan->align_buf && len) { 593 dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n", 594 __func__); 595 usb_dma_t *ud = &chan->qh->dw_align_buf_usbdma; 596 597 usb_syncmem(ud, 0, chan->qh->dw_align_buf_size, 598 chan->ep_is_in ? 599 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 600 if (chan->ep_is_in) 601 memcpy(urb->buf + frame_desc->offset + 602 qtd->isoc_split_offset, 603 chan->qh->dw_align_buf, 604 len); 605 usb_syncmem(ud, 0, chan->qh->dw_align_buf_size, 606 chan->ep_is_in ? 607 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 608 } 609 610 frame_desc->actual_length += len; 611 612 if (qtd->isoc_split_pos != DWC2_HCSPLT_XACTPOS_ALL) 613 return DWC2_HC_XFER_COMPLETE; 614 615 break; 616 case DWC2_HC_XFER_FRAME_OVERRUN: 617 urb->error_count++; 618 if (chan->ep_is_in) 619 frame_desc->status = -ENOSR; 620 else 621 frame_desc->status = -ECOMM; 622 frame_desc->actual_length = 0; 623 break; 624 case DWC2_HC_XFER_BABBLE_ERR: 625 urb->error_count++; 626 frame_desc->status = -EOVERFLOW; 627 /* Don't need to update actual_length in this case */ 628 break; 629 case DWC2_HC_XFER_XACT_ERR: 630 urb->error_count++; 631 frame_desc->status = -EPROTO; 632 frame_desc->actual_length = dwc2_get_actual_xfer_length(hsotg, 633 chan, chnum, qtd, halt_status, NULL); 634 635 /* Non DWORD-aligned buffer case handling */ 636 if (chan->align_buf && frame_desc->actual_length) { 637 dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n", 638 __func__); 639 usb_dma_t *ud = &chan->qh->dw_align_buf_usbdma; 640 641 usb_syncmem(ud, 0, chan->qh->dw_align_buf_size, 642 chan->ep_is_in ? 643 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 644 if (chan->ep_is_in) 645 memcpy(urb->buf + frame_desc->offset + 646 qtd->isoc_split_offset, 647 chan->qh->dw_align_buf, 648 frame_desc->actual_length); 649 usb_syncmem(ud, 0, chan->qh->dw_align_buf_size, 650 chan->ep_is_in ? 651 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 652 } 653 654 /* Skip whole frame */ 655 if (chan->qh->do_split && 656 chan->ep_type == USB_ENDPOINT_XFER_ISOC && chan->ep_is_in && 657 hsotg->core_params->dma_enable > 0) { 658 qtd->complete_split = 0; 659 qtd->isoc_split_offset = 0; 660 } 661 662 break; 663 default: 664 dev_err(hsotg->dev, "Unhandled halt_status (%d)\n", 665 halt_status); 666 break; 667 } 668 669 if (++qtd->isoc_frame_index == urb->packet_count) { 670 /* 671 * urb->status is not used for isoc transfers. The individual 672 * frame_desc statuses are used instead. 673 */ 674 dwc2_host_complete(hsotg, qtd, 0); 675 halt_status = DWC2_HC_XFER_URB_COMPLETE; 676 } else { 677 halt_status = DWC2_HC_XFER_COMPLETE; 678 } 679 680 return halt_status; 681 } 682 683 /* 684 * Frees the first QTD in the QH's list if free_qtd is 1. For non-periodic 685 * QHs, removes the QH from the active non-periodic schedule. If any QTDs are 686 * still linked to the QH, the QH is added to the end of the inactive 687 * non-periodic schedule. For periodic QHs, removes the QH from the periodic 688 * schedule if no more QTDs are linked to the QH. 689 */ 690 static void dwc2_deactivate_qh(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 691 int free_qtd) 692 { 693 int continue_split = 0; 694 struct dwc2_qtd *qtd; 695 696 if (dbg_qh(qh)) 697 dev_vdbg(hsotg->dev, " %s(%p,%p,%d)\n", __func__, 698 hsotg, qh, free_qtd); 699 700 if (list_empty(&qh->qtd_list)) { 701 dev_dbg(hsotg->dev, "## QTD list empty ##\n"); 702 goto no_qtd; 703 } 704 705 qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry); 706 707 if (qtd->complete_split) 708 continue_split = 1; 709 else if (qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_MID || 710 qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_END) 711 continue_split = 1; 712 713 if (free_qtd) { 714 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 715 continue_split = 0; 716 } 717 718 no_qtd: 719 if (qh->channel) 720 qh->channel->align_buf = 0; 721 qh->channel = NULL; 722 dwc2_hcd_qh_deactivate(hsotg, qh, continue_split); 723 } 724 725 /** 726 * dwc2_release_channel() - Releases a host channel for use by other transfers 727 * 728 * @hsotg: The HCD state structure 729 * @chan: The host channel to release 730 * @qtd: The QTD associated with the host channel. This QTD may be 731 * freed if the transfer is complete or an error has occurred. 732 * @halt_status: Reason the channel is being released. This status 733 * determines the actions taken by this function. 734 * 735 * Also attempts to select and queue more transactions since at least one host 736 * channel is available. 737 */ 738 static void dwc2_release_channel(struct dwc2_hsotg *hsotg, 739 struct dwc2_host_chan *chan, 740 struct dwc2_qtd *qtd, 741 enum dwc2_halt_status halt_status) 742 { 743 enum dwc2_transaction_type tr_type; 744 u32 haintmsk; 745 int free_qtd = 0; 746 747 if (dbg_hc(chan)) 748 dev_vdbg(hsotg->dev, " %s: channel %d, halt_status %d\n", 749 __func__, chan->hc_num, halt_status); 750 751 switch (halt_status) { 752 case DWC2_HC_XFER_URB_COMPLETE: 753 free_qtd = 1; 754 break; 755 case DWC2_HC_XFER_AHB_ERR: 756 case DWC2_HC_XFER_STALL: 757 case DWC2_HC_XFER_BABBLE_ERR: 758 free_qtd = 1; 759 break; 760 case DWC2_HC_XFER_XACT_ERR: 761 if (qtd && qtd->error_count >= 3) { 762 dev_vdbg(hsotg->dev, 763 " Complete URB with transaction error\n"); 764 free_qtd = 1; 765 dwc2_host_complete(hsotg, qtd, -EPROTO); 766 } 767 break; 768 case DWC2_HC_XFER_URB_DEQUEUE: 769 /* 770 * The QTD has already been removed and the QH has been 771 * deactivated. Don't want to do anything except release the 772 * host channel and try to queue more transfers. 773 */ 774 goto cleanup; 775 case DWC2_HC_XFER_PERIODIC_INCOMPLETE: 776 dev_vdbg(hsotg->dev, " Complete URB with I/O error\n"); 777 free_qtd = 1; 778 dwc2_host_complete(hsotg, qtd, -EIO); 779 break; 780 case DWC2_HC_XFER_NO_HALT_STATUS: 781 default: 782 break; 783 } 784 785 dwc2_deactivate_qh(hsotg, chan->qh, free_qtd); 786 787 cleanup: 788 /* 789 * Release the host channel for use by other transfers. The cleanup 790 * function clears the channel interrupt enables and conditions, so 791 * there's no need to clear the Channel Halted interrupt separately. 792 */ 793 if (!list_empty(&chan->hc_list_entry)) 794 list_del(&chan->hc_list_entry); 795 dwc2_hc_cleanup(hsotg, chan); 796 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list); 797 798 if (hsotg->core_params->uframe_sched > 0) { 799 hsotg->available_host_channels++; 800 } else { 801 switch (chan->ep_type) { 802 case USB_ENDPOINT_XFER_CONTROL: 803 case USB_ENDPOINT_XFER_BULK: 804 hsotg->non_periodic_channels--; 805 break; 806 default: 807 /* 808 * Don't release reservations for periodic channels 809 * here. That's done when a periodic transfer is 810 * descheduled (i.e. when the QH is removed from the 811 * periodic schedule). 812 */ 813 break; 814 } 815 } 816 817 haintmsk = DWC2_READ_4(hsotg, HAINTMSK); 818 haintmsk &= ~(1 << chan->hc_num); 819 DWC2_WRITE_4(hsotg, HAINTMSK, haintmsk); 820 821 /* Try to queue more transfers now that there's a free channel */ 822 tr_type = dwc2_hcd_select_transactions(hsotg); 823 if (tr_type != DWC2_TRANSACTION_NONE) 824 dwc2_hcd_queue_transactions(hsotg, tr_type); 825 } 826 827 /* 828 * Halts a host channel. If the channel cannot be halted immediately because 829 * the request queue is full, this function ensures that the FIFO empty 830 * interrupt for the appropriate queue is enabled so that the halt request can 831 * be queued when there is space in the request queue. 832 * 833 * This function may also be called in DMA mode. In that case, the channel is 834 * simply released since the core always halts the channel automatically in 835 * DMA mode. 836 */ 837 static void dwc2_halt_channel(struct dwc2_hsotg *hsotg, 838 struct dwc2_host_chan *chan, struct dwc2_qtd *qtd, 839 enum dwc2_halt_status halt_status) 840 { 841 if (dbg_hc(chan)) 842 dev_vdbg(hsotg->dev, "%s()\n", __func__); 843 844 if (hsotg->core_params->dma_enable > 0) { 845 if (dbg_hc(chan)) 846 dev_vdbg(hsotg->dev, "DMA enabled\n"); 847 dwc2_release_channel(hsotg, chan, qtd, halt_status); 848 return; 849 } 850 851 /* Slave mode processing */ 852 dwc2_hc_halt(hsotg, chan, halt_status); 853 854 if (chan->halt_on_queue) { 855 u32 gintmsk; 856 857 dev_vdbg(hsotg->dev, "Halt on queue\n"); 858 if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL || 859 chan->ep_type == USB_ENDPOINT_XFER_BULK) { 860 dev_vdbg(hsotg->dev, "control/bulk\n"); 861 /* 862 * Make sure the Non-periodic Tx FIFO empty interrupt 863 * is enabled so that the non-periodic schedule will 864 * be processed 865 */ 866 gintmsk = DWC2_READ_4(hsotg, GINTMSK); 867 gintmsk |= GINTSTS_NPTXFEMP; 868 DWC2_WRITE_4(hsotg, GINTMSK, gintmsk); 869 } else { 870 dev_vdbg(hsotg->dev, "isoc/intr\n"); 871 /* 872 * Move the QH from the periodic queued schedule to 873 * the periodic assigned schedule. This allows the 874 * halt to be queued when the periodic schedule is 875 * processed. 876 */ 877 list_move(&chan->qh->qh_list_entry, 878 &hsotg->periodic_sched_assigned); 879 880 /* 881 * Make sure the Periodic Tx FIFO Empty interrupt is 882 * enabled so that the periodic schedule will be 883 * processed 884 */ 885 gintmsk = DWC2_READ_4(hsotg, GINTMSK); 886 gintmsk |= GINTSTS_PTXFEMP; 887 DWC2_WRITE_4(hsotg, GINTMSK, gintmsk); 888 } 889 } 890 } 891 892 /* 893 * Performs common cleanup for non-periodic transfers after a Transfer 894 * Complete interrupt. This function should be called after any endpoint type 895 * specific handling is finished to release the host channel. 896 */ 897 static void dwc2_complete_non_periodic_xfer(struct dwc2_hsotg *hsotg, 898 struct dwc2_host_chan *chan, 899 int chnum, struct dwc2_qtd *qtd, 900 enum dwc2_halt_status halt_status) 901 { 902 dev_vdbg(hsotg->dev, "%s()\n", __func__); 903 904 qtd->error_count = 0; 905 906 if (chan->hcint & HCINTMSK_NYET) { 907 /* 908 * Got a NYET on the last transaction of the transfer. This 909 * means that the endpoint should be in the PING state at the 910 * beginning of the next transfer. 911 */ 912 dev_vdbg(hsotg->dev, "got NYET\n"); 913 chan->qh->ping_state = 1; 914 } 915 916 /* 917 * Always halt and release the host channel to make it available for 918 * more transfers. There may still be more phases for a control 919 * transfer or more data packets for a bulk transfer at this point, 920 * but the host channel is still halted. A channel will be reassigned 921 * to the transfer when the non-periodic schedule is processed after 922 * the channel is released. This allows transactions to be queued 923 * properly via dwc2_hcd_queue_transactions, which also enables the 924 * Tx FIFO Empty interrupt if necessary. 925 */ 926 if (chan->ep_is_in) { 927 /* 928 * IN transfers in Slave mode require an explicit disable to 929 * halt the channel. (In DMA mode, this call simply releases 930 * the channel.) 931 */ 932 dwc2_halt_channel(hsotg, chan, qtd, halt_status); 933 } else { 934 /* 935 * The channel is automatically disabled by the core for OUT 936 * transfers in Slave mode 937 */ 938 dwc2_release_channel(hsotg, chan, qtd, halt_status); 939 } 940 } 941 942 /* 943 * Performs common cleanup for periodic transfers after a Transfer Complete 944 * interrupt. This function should be called after any endpoint type specific 945 * handling is finished to release the host channel. 946 */ 947 static void dwc2_complete_periodic_xfer(struct dwc2_hsotg *hsotg, 948 struct dwc2_host_chan *chan, int chnum, 949 struct dwc2_qtd *qtd, 950 enum dwc2_halt_status halt_status) 951 { 952 u32 hctsiz = DWC2_READ_4(hsotg, HCTSIZ(chnum)); 953 954 qtd->error_count = 0; 955 956 if (!chan->ep_is_in || (hctsiz & TSIZ_PKTCNT_MASK) == 0) 957 /* Core halts channel in these cases */ 958 dwc2_release_channel(hsotg, chan, qtd, halt_status); 959 else 960 /* Flush any outstanding requests from the Tx queue */ 961 dwc2_halt_channel(hsotg, chan, qtd, halt_status); 962 } 963 964 static int dwc2_xfercomp_isoc_split_in(struct dwc2_hsotg *hsotg, 965 struct dwc2_host_chan *chan, int chnum, 966 struct dwc2_qtd *qtd) 967 { 968 struct dwc2_hcd_iso_packet_desc *frame_desc; 969 u32 len; 970 971 if (!qtd->urb) 972 return 0; 973 974 frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index]; 975 len = dwc2_get_actual_xfer_length(hsotg, chan, chnum, qtd, 976 DWC2_HC_XFER_COMPLETE, NULL); 977 if (!len) { 978 qtd->complete_split = 0; 979 qtd->isoc_split_offset = 0; 980 return 0; 981 } 982 983 frame_desc->actual_length += len; 984 985 if (chan->align_buf) { 986 dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n", __func__); 987 usb_syncmem(qtd->urb->usbdma, chan->qh->dw_align_buf_dma, 988 chan->qh->dw_align_buf_size, BUS_DMASYNC_POSTREAD); 989 memcpy(qtd->urb->buf + frame_desc->offset + 990 qtd->isoc_split_offset, chan->qh->dw_align_buf, len); 991 usb_syncmem(qtd->urb->usbdma, chan->qh->dw_align_buf_dma, 992 chan->qh->dw_align_buf_size, BUS_DMASYNC_PREREAD); 993 } 994 995 qtd->isoc_split_offset += len; 996 997 if (frame_desc->actual_length >= frame_desc->length) { 998 frame_desc->status = 0; 999 qtd->isoc_frame_index++; 1000 qtd->complete_split = 0; 1001 qtd->isoc_split_offset = 0; 1002 } 1003 1004 if (qtd->isoc_frame_index == qtd->urb->packet_count) { 1005 dwc2_host_complete(hsotg, qtd, 0); 1006 dwc2_release_channel(hsotg, chan, qtd, 1007 DWC2_HC_XFER_URB_COMPLETE); 1008 } else { 1009 dwc2_release_channel(hsotg, chan, qtd, 1010 DWC2_HC_XFER_NO_HALT_STATUS); 1011 } 1012 1013 return 1; /* Indicates that channel released */ 1014 } 1015 1016 /* 1017 * Handles a host channel Transfer Complete interrupt. This handler may be 1018 * called in either DMA mode or Slave mode. 1019 */ 1020 static void dwc2_hc_xfercomp_intr(struct dwc2_hsotg *hsotg, 1021 struct dwc2_host_chan *chan, int chnum, 1022 struct dwc2_qtd *qtd) 1023 { 1024 struct dwc2_hcd_urb *urb = qtd->urb; 1025 enum dwc2_halt_status halt_status = DWC2_HC_XFER_COMPLETE; 1026 int pipe_type; 1027 int urb_xfer_done; 1028 1029 if (dbg_hc(chan)) 1030 dev_vdbg(hsotg->dev, 1031 "--Host Channel %d Interrupt: Transfer Complete--\n", 1032 chnum); 1033 1034 if (!urb) 1035 goto handle_xfercomp_done; 1036 1037 pipe_type = dwc2_hcd_get_pipe_type(&urb->pipe_info); 1038 1039 if (hsotg->core_params->dma_desc_enable > 0) { 1040 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum, halt_status); 1041 if (pipe_type == USB_ENDPOINT_XFER_ISOC) 1042 /* Do not disable the interrupt, just clear it */ 1043 return; 1044 goto handle_xfercomp_done; 1045 } 1046 1047 /* Handle xfer complete on CSPLIT */ 1048 if (chan->qh->do_split) { 1049 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC && chan->ep_is_in && 1050 hsotg->core_params->dma_enable > 0) { 1051 if (qtd->complete_split && 1052 dwc2_xfercomp_isoc_split_in(hsotg, chan, chnum, 1053 qtd)) 1054 goto handle_xfercomp_done; 1055 } else { 1056 qtd->complete_split = 0; 1057 } 1058 } 1059 1060 /* Update the QTD and URB states */ 1061 switch (pipe_type) { 1062 case USB_ENDPOINT_XFER_CONTROL: 1063 switch (qtd->control_phase) { 1064 case DWC2_CONTROL_SETUP: 1065 if (urb->length > 0) 1066 qtd->control_phase = DWC2_CONTROL_DATA; 1067 else 1068 qtd->control_phase = DWC2_CONTROL_STATUS; 1069 dev_vdbg(hsotg->dev, 1070 " Control setup transaction done\n"); 1071 halt_status = DWC2_HC_XFER_COMPLETE; 1072 break; 1073 case DWC2_CONTROL_DATA: 1074 urb_xfer_done = dwc2_update_urb_state(hsotg, chan, 1075 chnum, urb, qtd); 1076 if (urb_xfer_done) { 1077 qtd->control_phase = DWC2_CONTROL_STATUS; 1078 dev_vdbg(hsotg->dev, 1079 " Control data transfer done\n"); 1080 } else { 1081 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, 1082 qtd); 1083 } 1084 halt_status = DWC2_HC_XFER_COMPLETE; 1085 break; 1086 case DWC2_CONTROL_STATUS: 1087 dev_vdbg(hsotg->dev, " Control transfer complete\n"); 1088 if (urb->status == -EINPROGRESS) 1089 urb->status = 0; 1090 dwc2_host_complete(hsotg, qtd, urb->status); 1091 halt_status = DWC2_HC_XFER_URB_COMPLETE; 1092 break; 1093 } 1094 1095 dwc2_complete_non_periodic_xfer(hsotg, chan, chnum, qtd, 1096 halt_status); 1097 break; 1098 case USB_ENDPOINT_XFER_BULK: 1099 dev_vdbg(hsotg->dev, " Bulk transfer complete\n"); 1100 urb_xfer_done = dwc2_update_urb_state(hsotg, chan, chnum, urb, 1101 qtd); 1102 if (urb_xfer_done) { 1103 dwc2_host_complete(hsotg, qtd, urb->status); 1104 halt_status = DWC2_HC_XFER_URB_COMPLETE; 1105 } else { 1106 halt_status = DWC2_HC_XFER_COMPLETE; 1107 } 1108 1109 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd); 1110 dwc2_complete_non_periodic_xfer(hsotg, chan, chnum, qtd, 1111 halt_status); 1112 break; 1113 case USB_ENDPOINT_XFER_INT: 1114 dev_vdbg(hsotg->dev, " Interrupt transfer complete\n"); 1115 urb_xfer_done = dwc2_update_urb_state(hsotg, chan, chnum, urb, 1116 qtd); 1117 1118 /* 1119 * Interrupt URB is done on the first transfer complete 1120 * interrupt 1121 */ 1122 if (urb_xfer_done) { 1123 dwc2_host_complete(hsotg, qtd, urb->status); 1124 halt_status = DWC2_HC_XFER_URB_COMPLETE; 1125 } else { 1126 halt_status = DWC2_HC_XFER_COMPLETE; 1127 } 1128 1129 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd); 1130 dwc2_complete_periodic_xfer(hsotg, chan, chnum, qtd, 1131 halt_status); 1132 break; 1133 case USB_ENDPOINT_XFER_ISOC: 1134 if (dbg_perio()) 1135 dev_vdbg(hsotg->dev, " Isochronous transfer complete\n"); 1136 halt_status = dwc2_update_isoc_urb_state(hsotg, chan, 1137 chnum, qtd, DWC2_HC_XFER_COMPLETE); 1138 dwc2_complete_periodic_xfer(hsotg, chan, chnum, qtd, 1139 halt_status); 1140 break; 1141 } 1142 1143 handle_xfercomp_done: 1144 disable_hc_int(hsotg, chnum, HCINTMSK_XFERCOMPL); 1145 } 1146 1147 /* 1148 * Handles a host channel STALL interrupt. This handler may be called in 1149 * either DMA mode or Slave mode. 1150 */ 1151 static void dwc2_hc_stall_intr(struct dwc2_hsotg *hsotg, 1152 struct dwc2_host_chan *chan, int chnum, 1153 struct dwc2_qtd *qtd) 1154 { 1155 struct dwc2_hcd_urb *urb = qtd->urb; 1156 int pipe_type; 1157 1158 dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: STALL Received--\n", 1159 chnum); 1160 1161 if (hsotg->core_params->dma_desc_enable > 0) { 1162 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum, 1163 DWC2_HC_XFER_STALL); 1164 goto handle_stall_done; 1165 } 1166 1167 if (!urb) 1168 goto handle_stall_halt; 1169 1170 pipe_type = dwc2_hcd_get_pipe_type(&urb->pipe_info); 1171 1172 if (pipe_type == USB_ENDPOINT_XFER_CONTROL) 1173 dwc2_host_complete(hsotg, qtd, -EPIPE); 1174 1175 if (pipe_type == USB_ENDPOINT_XFER_BULK || 1176 pipe_type == USB_ENDPOINT_XFER_INT) { 1177 dwc2_host_complete(hsotg, qtd, -EPIPE); 1178 /* 1179 * USB protocol requires resetting the data toggle for bulk 1180 * and interrupt endpoints when a CLEAR_FEATURE(ENDPOINT_HALT) 1181 * setup command is issued to the endpoint. Anticipate the 1182 * CLEAR_FEATURE command since a STALL has occurred and reset 1183 * the data toggle now. 1184 */ 1185 chan->qh->data_toggle = 0; 1186 } 1187 1188 handle_stall_halt: 1189 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_STALL); 1190 1191 handle_stall_done: 1192 disable_hc_int(hsotg, chnum, HCINTMSK_STALL); 1193 } 1194 1195 /* 1196 * Updates the state of the URB when a transfer has been stopped due to an 1197 * abnormal condition before the transfer completes. Modifies the 1198 * actual_length field of the URB to reflect the number of bytes that have 1199 * actually been transferred via the host channel. 1200 */ 1201 static void dwc2_update_urb_state_abn(struct dwc2_hsotg *hsotg, 1202 struct dwc2_host_chan *chan, int chnum, 1203 struct dwc2_hcd_urb *urb, 1204 struct dwc2_qtd *qtd, 1205 enum dwc2_halt_status halt_status) 1206 { 1207 u32 xfer_length = dwc2_get_actual_xfer_length(hsotg, chan, chnum, 1208 qtd, halt_status, NULL); 1209 1210 if (urb->actual_length + xfer_length > urb->length) { 1211 dev_warn(hsotg->dev, "%s(): trimming xfer length\n", __func__); 1212 xfer_length = urb->length - urb->actual_length; 1213 } 1214 1215 /* Non DWORD-aligned buffer case handling */ 1216 if (chan->align_buf && xfer_length && chan->ep_is_in) { 1217 dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n", __func__); 1218 1219 usb_dma_t *ud = &chan->qh->dw_align_buf_usbdma; 1220 1221 usb_syncmem(ud, 0, chan->qh->dw_align_buf_size, 1222 chan->ep_is_in ? 1223 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1224 if (chan->ep_is_in) 1225 memcpy(urb->buf + urb->actual_length, 1226 chan->qh->dw_align_buf, 1227 xfer_length); 1228 usb_syncmem(ud, 0, chan->qh->dw_align_buf_size, 1229 chan->ep_is_in ? 1230 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1231 } 1232 1233 urb->actual_length += xfer_length; 1234 1235 dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n", 1236 __func__, (chan->ep_is_in ? "IN" : "OUT"), chnum); 1237 dev_vdbg(hsotg->dev, " chan->start_pkt_count %d\n", 1238 chan->start_pkt_count); 1239 dev_vdbg(hsotg->dev, " hctsiz.pktcnt %d\n", 1240 (DWC2_READ_4(hsotg, HCTSIZ(chnum)) & TSIZ_PKTCNT_MASK) >> TSIZ_PKTCNT_SHIFT); 1241 dev_vdbg(hsotg->dev, " chan->max_packet %d\n", chan->max_packet); 1242 dev_vdbg(hsotg->dev, " bytes_transferred %d\n", 1243 xfer_length); 1244 dev_vdbg(hsotg->dev, " urb->actual_length %d\n", 1245 urb->actual_length); 1246 dev_vdbg(hsotg->dev, " urb->transfer_buffer_length %d\n", 1247 urb->length); 1248 } 1249 1250 /* 1251 * Handles a host channel NAK interrupt. This handler may be called in either 1252 * DMA mode or Slave mode. 1253 */ 1254 static void dwc2_hc_nak_intr(struct dwc2_hsotg *hsotg, 1255 struct dwc2_host_chan *chan, int chnum, 1256 struct dwc2_qtd *qtd) 1257 { 1258 if (!qtd) { 1259 dev_dbg(hsotg->dev, "%s: qtd is NULL\n", __func__); 1260 return; 1261 } 1262 1263 if (!qtd->urb) { 1264 dev_dbg(hsotg->dev, "%s: qtd->urb is NULL\n", __func__); 1265 return; 1266 } 1267 1268 if (dbg_hc(chan)) 1269 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: NAK Received--\n", 1270 chnum); 1271 1272 /* 1273 * Handle NAK for IN/OUT SSPLIT/CSPLIT transfers, bulk, control, and 1274 * interrupt. Re-start the SSPLIT transfer. 1275 * 1276 * Normally for non-periodic transfers we'll retry right away, but to 1277 * avoid interrupt storms we'll wait before retrying if we've got 1278 * several NAKs. If we didn't do this we'd retry directly from the 1279 * interrupt handler and could end up quickly getting another 1280 * interrupt (another NAK), which we'd retry. 1281 * 1282 * Note that in DMA mode software only gets involved to re-send NAKed 1283 * transfers for split transactions unless the core is missing OUT NAK 1284 * enhancement. 1285 */ 1286 if (chan->do_split) { 1287 /* 1288 * When we get control/bulk NAKs then remember this so we holdoff on 1289 * this qh until the beginning of the next frame 1290 */ 1291 switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) { 1292 case USB_ENDPOINT_XFER_CONTROL: 1293 case USB_ENDPOINT_XFER_BULK: 1294 chan->qh->nak_frame = dwc2_hcd_get_frame_number(hsotg); 1295 break; 1296 } 1297 1298 if (chan->complete_split) 1299 qtd->error_count = 0; 1300 qtd->complete_split = 0; 1301 qtd->num_naks++; 1302 qtd->qh->want_wait = qtd->num_naks >= dwc2_naks_before_delay; 1303 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK); 1304 goto handle_nak_done; 1305 } 1306 1307 switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) { 1308 case USB_ENDPOINT_XFER_CONTROL: 1309 case USB_ENDPOINT_XFER_BULK: 1310 if (hsotg->core_params->dma_enable > 0 && chan->ep_is_in) { 1311 /* 1312 * NAK interrupts are enabled on bulk/control IN 1313 * transfers in DMA mode for the sole purpose of 1314 * resetting the error count after a transaction error 1315 * occurs. The core will continue transferring data. 1316 */ 1317 qtd->error_count = 0; 1318 break; 1319 } 1320 1321 /* 1322 * NAK interrupts normally occur during OUT transfers in DMA 1323 * or Slave mode. For IN transfers, more requests will be 1324 * queued as request queue space is available. 1325 */ 1326 qtd->error_count = 0; 1327 1328 if (hsotg->core_params->dma_enable > 0 && !chan->ep_is_in) { 1329 /* 1330 * Avoid interrupt storms. 1331 */ 1332 qtd->num_naks++; 1333 qtd->qh->want_wait = qtd->num_naks >= dwc2_out_naks_before_delay; 1334 } 1335 if (!chan->qh->ping_state) { 1336 dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb, 1337 qtd, DWC2_HC_XFER_NAK); 1338 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd); 1339 1340 if (chan->speed == USB_SPEED_HIGH) 1341 chan->qh->ping_state = 1; 1342 } 1343 1344 /* 1345 * Halt the channel so the transfer can be re-started from 1346 * the appropriate point or the PING protocol will 1347 * start/continue 1348 */ 1349 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK); 1350 break; 1351 case USB_ENDPOINT_XFER_INT: 1352 qtd->error_count = 0; 1353 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK); 1354 break; 1355 case USB_ENDPOINT_XFER_ISOC: 1356 /* Should never get called for isochronous transfers */ 1357 dev_err(hsotg->dev, "NACK interrupt for ISOC transfer\n"); 1358 break; 1359 } 1360 1361 handle_nak_done: 1362 disable_hc_int(hsotg, chnum, HCINTMSK_NAK); 1363 } 1364 1365 /* 1366 * Handles a host channel ACK interrupt. This interrupt is enabled when 1367 * performing the PING protocol in Slave mode, when errors occur during 1368 * either Slave mode or DMA mode, and during Start Split transactions. 1369 */ 1370 static void dwc2_hc_ack_intr(struct dwc2_hsotg *hsotg, 1371 struct dwc2_host_chan *chan, int chnum, 1372 struct dwc2_qtd *qtd) 1373 { 1374 struct dwc2_hcd_iso_packet_desc *frame_desc; 1375 1376 if (dbg_hc(chan)) 1377 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: ACK Received--\n", 1378 chnum); 1379 1380 if (chan->do_split) { 1381 /* Handle ACK on SSPLIT. ACK should not occur in CSPLIT. */ 1382 if (!chan->ep_is_in && 1383 chan->data_pid_start != DWC2_HC_PID_SETUP) 1384 qtd->ssplit_out_xfer_count = chan->xfer_len; 1385 1386 if (chan->ep_type != USB_ENDPOINT_XFER_ISOC || chan->ep_is_in) { 1387 qtd->complete_split = 1; 1388 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_ACK); 1389 } else { 1390 /* ISOC OUT */ 1391 switch (chan->xact_pos) { 1392 case DWC2_HCSPLT_XACTPOS_ALL: 1393 break; 1394 case DWC2_HCSPLT_XACTPOS_END: 1395 qtd->isoc_split_pos = DWC2_HCSPLT_XACTPOS_ALL; 1396 qtd->isoc_split_offset = 0; 1397 break; 1398 case DWC2_HCSPLT_XACTPOS_BEGIN: 1399 case DWC2_HCSPLT_XACTPOS_MID: 1400 /* 1401 * For BEGIN or MID, calculate the length for 1402 * the next microframe to determine the correct 1403 * SSPLIT token, either MID or END 1404 */ 1405 frame_desc = &qtd->urb->iso_descs[ 1406 qtd->isoc_frame_index]; 1407 qtd->isoc_split_offset += 188; 1408 1409 if (frame_desc->length - qtd->isoc_split_offset 1410 <= 188) 1411 qtd->isoc_split_pos = 1412 DWC2_HCSPLT_XACTPOS_END; 1413 else 1414 qtd->isoc_split_pos = 1415 DWC2_HCSPLT_XACTPOS_MID; 1416 break; 1417 } 1418 } 1419 } else { 1420 qtd->error_count = 0; 1421 1422 if (chan->qh->ping_state) { 1423 chan->qh->ping_state = 0; 1424 /* 1425 * Halt the channel so the transfer can be re-started 1426 * from the appropriate point. This only happens in 1427 * Slave mode. In DMA mode, the ping_state is cleared 1428 * when the transfer is started because the core 1429 * automatically executes the PING, then the transfer. 1430 */ 1431 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_ACK); 1432 } 1433 } 1434 1435 /* 1436 * If the ACK occurred when _not_ in the PING state, let the channel 1437 * continue transferring data after clearing the error count 1438 */ 1439 disable_hc_int(hsotg, chnum, HCINTMSK_ACK); 1440 } 1441 1442 /* 1443 * Handles a host channel NYET interrupt. This interrupt should only occur on 1444 * Bulk and Control OUT endpoints and for complete split transactions. If a 1445 * NYET occurs at the same time as a Transfer Complete interrupt, it is 1446 * handled in the xfercomp interrupt handler, not here. This handler may be 1447 * called in either DMA mode or Slave mode. 1448 */ 1449 static void dwc2_hc_nyet_intr(struct dwc2_hsotg *hsotg, 1450 struct dwc2_host_chan *chan, int chnum, 1451 struct dwc2_qtd *qtd) 1452 { 1453 if (dbg_hc(chan)) 1454 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: NYET Received--\n", 1455 chnum); 1456 1457 /* 1458 * NYET on CSPLIT 1459 * re-do the CSPLIT immediately on non-periodic 1460 */ 1461 if (chan->do_split && chan->complete_split) { 1462 if (chan->ep_is_in && chan->ep_type == USB_ENDPOINT_XFER_ISOC && 1463 hsotg->core_params->dma_enable > 0) { 1464 qtd->complete_split = 0; 1465 qtd->isoc_split_offset = 0; 1466 qtd->isoc_frame_index++; 1467 if (qtd->urb && 1468 qtd->isoc_frame_index == qtd->urb->packet_count) { 1469 dwc2_host_complete(hsotg, qtd, 0); 1470 dwc2_release_channel(hsotg, chan, qtd, 1471 DWC2_HC_XFER_URB_COMPLETE); 1472 } else { 1473 dwc2_release_channel(hsotg, chan, qtd, 1474 DWC2_HC_XFER_NO_HALT_STATUS); 1475 } 1476 goto handle_nyet_done; 1477 } 1478 1479 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1480 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 1481 int frnum = dwc2_hcd_get_frame_number(hsotg); 1482 1483 if (dwc2_full_frame_num(frnum) != 1484 dwc2_full_frame_num(chan->qh->sched_frame)) { 1485 /* 1486 * No longer in the same full speed frame. 1487 * Treat this as a transaction error. 1488 */ 1489 #if 0 1490 /* 1491 * Todo: Fix system performance so this can 1492 * be treated as an error. Right now complete 1493 * splits cannot be scheduled precisely enough 1494 * due to other system activity, so this error 1495 * occurs regularly in Slave mode. 1496 */ 1497 qtd->error_count++; 1498 #endif 1499 qtd->complete_split = 0; 1500 dwc2_halt_channel(hsotg, chan, qtd, 1501 DWC2_HC_XFER_XACT_ERR); 1502 /* Todo: add support for isoc release */ 1503 goto handle_nyet_done; 1504 } 1505 } 1506 1507 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NYET); 1508 goto handle_nyet_done; 1509 } 1510 1511 chan->qh->ping_state = 1; 1512 qtd->error_count = 0; 1513 1514 dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb, qtd, 1515 DWC2_HC_XFER_NYET); 1516 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd); 1517 1518 /* 1519 * Halt the channel and re-start the transfer so the PING protocol 1520 * will start 1521 */ 1522 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NYET); 1523 1524 handle_nyet_done: 1525 disable_hc_int(hsotg, chnum, HCINTMSK_NYET); 1526 } 1527 1528 /* 1529 * Handles a host channel babble interrupt. This handler may be called in 1530 * either DMA mode or Slave mode. 1531 */ 1532 static void dwc2_hc_babble_intr(struct dwc2_hsotg *hsotg, 1533 struct dwc2_host_chan *chan, int chnum, 1534 struct dwc2_qtd *qtd) 1535 { 1536 dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: Babble Error--\n", 1537 chnum); 1538 1539 // dwc2_hc_handle_tt_clear(hsotg, chan, qtd); 1540 1541 if (hsotg->core_params->dma_desc_enable > 0) { 1542 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum, 1543 DWC2_HC_XFER_BABBLE_ERR); 1544 goto disable_int; 1545 } 1546 1547 if (chan->ep_type != USB_ENDPOINT_XFER_ISOC) { 1548 dwc2_host_complete(hsotg, qtd, -EOVERFLOW); 1549 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_BABBLE_ERR); 1550 } else { 1551 enum dwc2_halt_status halt_status; 1552 1553 halt_status = dwc2_update_isoc_urb_state(hsotg, chan, chnum, 1554 qtd, DWC2_HC_XFER_BABBLE_ERR); 1555 dwc2_halt_channel(hsotg, chan, qtd, halt_status); 1556 } 1557 1558 disable_int: 1559 disable_hc_int(hsotg, chnum, HCINTMSK_BBLERR); 1560 } 1561 1562 /* 1563 * Handles a host channel AHB error interrupt. This handler is only called in 1564 * DMA mode. 1565 */ 1566 static void dwc2_hc_ahberr_intr(struct dwc2_hsotg *hsotg, 1567 struct dwc2_host_chan *chan, int chnum, 1568 struct dwc2_qtd *qtd) 1569 { 1570 struct dwc2_hcd_urb *urb = qtd->urb; 1571 1572 dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: AHB Error--\n", 1573 chnum); 1574 1575 if (!urb) 1576 goto handle_ahberr_halt; 1577 1578 // dwc2_hc_handle_tt_clear(hsotg, chan, qtd); 1579 1580 #ifdef DWC2_DEBUG 1581 const char *pipetype, *speed; 1582 1583 u32 hcchar = DWC2_READ_4(hsotg, HCCHAR(chnum)); 1584 u32 hcsplt = DWC2_READ_4(hsotg, HCSPLT(chnum)); 1585 u32 hctsiz = DWC2_READ_4(hsotg, HCTSIZ(chnum)); 1586 u32 hc_dma = DWC2_READ_4(hsotg, HCDMA(chnum)); 1587 1588 dev_err(hsotg->dev, "AHB ERROR, Channel %d\n", chnum); 1589 dev_err(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n", hcchar, hcsplt); 1590 dev_err(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n", hctsiz, hc_dma); 1591 dev_err(hsotg->dev, " Device address: %d\n", 1592 dwc2_hcd_get_dev_addr(&urb->pipe_info)); 1593 dev_err(hsotg->dev, " Endpoint: %d, %s\n", 1594 dwc2_hcd_get_ep_num(&urb->pipe_info), 1595 dwc2_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT"); 1596 1597 switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) { 1598 case USB_ENDPOINT_XFER_CONTROL: 1599 pipetype = "CONTROL"; 1600 break; 1601 case USB_ENDPOINT_XFER_BULK: 1602 pipetype = "BULK"; 1603 break; 1604 case USB_ENDPOINT_XFER_INT: 1605 pipetype = "INTERRUPT"; 1606 break; 1607 case USB_ENDPOINT_XFER_ISOC: 1608 pipetype = "ISOCHRONOUS"; 1609 break; 1610 default: 1611 pipetype = "UNKNOWN"; 1612 break; 1613 } 1614 1615 dev_err(hsotg->dev, " Endpoint type: %s\n", pipetype); 1616 1617 switch (chan->speed) { 1618 case USB_SPEED_HIGH: 1619 speed = "HIGH"; 1620 break; 1621 case USB_SPEED_FULL: 1622 speed = "FULL"; 1623 break; 1624 case USB_SPEED_LOW: 1625 speed = "LOW"; 1626 break; 1627 default: 1628 speed = "UNKNOWN"; 1629 break; 1630 } 1631 1632 dev_err(hsotg->dev, " Speed: %s\n", speed); 1633 1634 dev_err(hsotg->dev, " Max packet size: %d\n", 1635 dwc2_hcd_get_mps(&urb->pipe_info)); 1636 dev_err(hsotg->dev, " Data buffer length: %d\n", urb->length); 1637 dev_err(hsotg->dev, " Transfer buffer: %p, Transfer DMA: %08lx\n", 1638 urb->buf, (unsigned long)urb->dma); 1639 dev_err(hsotg->dev, " Setup buffer: %p, Setup DMA: %08lx\n", 1640 urb->setup_packet, (unsigned long)urb->setup_dma); 1641 dev_err(hsotg->dev, " Interval: %d\n", urb->interval); 1642 #endif 1643 1644 /* Core halts the channel for Descriptor DMA mode */ 1645 if (hsotg->core_params->dma_desc_enable > 0) { 1646 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum, 1647 DWC2_HC_XFER_AHB_ERR); 1648 goto handle_ahberr_done; 1649 } 1650 1651 dwc2_host_complete(hsotg, qtd, -EIO); 1652 1653 handle_ahberr_halt: 1654 /* 1655 * Force a channel halt. Don't call dwc2_halt_channel because that won't 1656 * write to the HCCHARn register in DMA mode to force the halt. 1657 */ 1658 dwc2_hc_halt(hsotg, chan, DWC2_HC_XFER_AHB_ERR); 1659 1660 handle_ahberr_done: 1661 disable_hc_int(hsotg, chnum, HCINTMSK_AHBERR); 1662 } 1663 1664 /* 1665 * Handles a host channel transaction error interrupt. This handler may be 1666 * called in either DMA mode or Slave mode. 1667 */ 1668 static void dwc2_hc_xacterr_intr(struct dwc2_hsotg *hsotg, 1669 struct dwc2_host_chan *chan, int chnum, 1670 struct dwc2_qtd *qtd) 1671 { 1672 dev_dbg(hsotg->dev, 1673 "--Host Channel %d Interrupt: Transaction Error--\n", chnum); 1674 1675 // dwc2_hc_handle_tt_clear(hsotg, chan, qtd); 1676 1677 if (hsotg->core_params->dma_desc_enable > 0) { 1678 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum, 1679 DWC2_HC_XFER_XACT_ERR); 1680 goto handle_xacterr_done; 1681 } 1682 1683 switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) { 1684 case USB_ENDPOINT_XFER_CONTROL: 1685 case USB_ENDPOINT_XFER_BULK: 1686 qtd->error_count++; 1687 if (!chan->qh->ping_state) { 1688 1689 dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb, 1690 qtd, DWC2_HC_XFER_XACT_ERR); 1691 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd); 1692 if (!chan->ep_is_in && chan->speed == USB_SPEED_HIGH) 1693 chan->qh->ping_state = 1; 1694 } 1695 1696 /* 1697 * Halt the channel so the transfer can be re-started from 1698 * the appropriate point or the PING protocol will start 1699 */ 1700 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR); 1701 break; 1702 case USB_ENDPOINT_XFER_INT: 1703 qtd->error_count++; 1704 if (chan->do_split && chan->complete_split) 1705 qtd->complete_split = 0; 1706 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR); 1707 break; 1708 case USB_ENDPOINT_XFER_ISOC: 1709 { 1710 enum dwc2_halt_status halt_status; 1711 1712 halt_status = dwc2_update_isoc_urb_state(hsotg, chan, 1713 chnum, qtd, DWC2_HC_XFER_XACT_ERR); 1714 dwc2_halt_channel(hsotg, chan, qtd, halt_status); 1715 } 1716 break; 1717 } 1718 1719 handle_xacterr_done: 1720 disable_hc_int(hsotg, chnum, HCINTMSK_XACTERR); 1721 } 1722 1723 /* 1724 * Handles a host channel frame overrun interrupt. This handler may be called 1725 * in either DMA mode or Slave mode. 1726 */ 1727 static void dwc2_hc_frmovrun_intr(struct dwc2_hsotg *hsotg, 1728 struct dwc2_host_chan *chan, int chnum, 1729 struct dwc2_qtd *qtd) 1730 { 1731 enum dwc2_halt_status halt_status; 1732 1733 if (dbg_hc(chan)) 1734 dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: Frame Overrun--\n", 1735 chnum); 1736 1737 dwc2_hc_handle_tt_clear(hsotg, chan, qtd); 1738 1739 switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) { 1740 case USB_ENDPOINT_XFER_CONTROL: 1741 case USB_ENDPOINT_XFER_BULK: 1742 break; 1743 case USB_ENDPOINT_XFER_INT: 1744 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_FRAME_OVERRUN); 1745 break; 1746 case USB_ENDPOINT_XFER_ISOC: 1747 halt_status = dwc2_update_isoc_urb_state(hsotg, chan, chnum, 1748 qtd, DWC2_HC_XFER_FRAME_OVERRUN); 1749 dwc2_halt_channel(hsotg, chan, qtd, halt_status); 1750 break; 1751 } 1752 1753 disable_hc_int(hsotg, chnum, HCINTMSK_FRMOVRUN); 1754 } 1755 1756 /* 1757 * Handles a host channel data toggle error interrupt. This handler may be 1758 * called in either DMA mode or Slave mode. 1759 */ 1760 static void dwc2_hc_datatglerr_intr(struct dwc2_hsotg *hsotg, 1761 struct dwc2_host_chan *chan, int chnum, 1762 struct dwc2_qtd *qtd) 1763 { 1764 dev_dbg(hsotg->dev, 1765 "--Host Channel %d Interrupt: Data Toggle Error--\n", chnum); 1766 1767 if (chan->ep_is_in) 1768 qtd->error_count = 0; 1769 else 1770 dev_err(hsotg->dev, 1771 "Data Toggle Error on OUT transfer, channel %d\n", 1772 chnum); 1773 1774 // dwc2_hc_handle_tt_clear(hsotg, chan, qtd); 1775 disable_hc_int(hsotg, chnum, HCINTMSK_DATATGLERR); 1776 } 1777 1778 /* 1779 * For debug only. It checks that a valid halt status is set and that 1780 * HCCHARn.chdis is clear. If there's a problem, corrective action is 1781 * taken and a warning is issued. 1782 * 1783 * Return: true if halt status is ok, false otherwise 1784 */ 1785 static bool dwc2_halt_status_ok(struct dwc2_hsotg *hsotg, 1786 struct dwc2_host_chan *chan, int chnum, 1787 struct dwc2_qtd *qtd) 1788 { 1789 #ifdef DWC2_DEBUG 1790 u32 hcchar; 1791 u32 hctsiz; 1792 u32 hcintmsk; 1793 u32 hcsplt; 1794 1795 if (chan->halt_status == DWC2_HC_XFER_NO_HALT_STATUS) { 1796 /* 1797 * This code is here only as a check. This condition should 1798 * never happen. Ignore the halt if it does occur. 1799 */ 1800 hcchar = DWC2_READ_4(hsotg, HCCHAR(chnum)); 1801 hctsiz = DWC2_READ_4(hsotg, HCTSIZ(chnum)); 1802 hcintmsk = DWC2_READ_4(hsotg, HCINTMSK(chnum)); 1803 hcsplt = DWC2_READ_4(hsotg, HCSPLT(chnum)); 1804 dev_dbg(hsotg->dev, 1805 "%s: chan->halt_status DWC2_HC_XFER_NO_HALT_STATUS,\n", 1806 __func__); 1807 dev_dbg(hsotg->dev, 1808 "channel %d, hcchar 0x%08x, hctsiz 0x%08x,\n", 1809 chnum, hcchar, hctsiz); 1810 dev_dbg(hsotg->dev, 1811 "hcint 0x%08x, hcintmsk 0x%08x, hcsplt 0x%08x,\n", 1812 chan->hcint, hcintmsk, hcsplt); 1813 if (qtd) 1814 dev_dbg(hsotg->dev, "qtd->complete_split %d\n", 1815 qtd->complete_split); 1816 dev_warn(hsotg->dev, 1817 "%s: no halt status, channel %d, ignoring interrupt\n", 1818 __func__, chnum); 1819 return false; 1820 } 1821 1822 /* 1823 * This code is here only as a check. hcchar.chdis should never be set 1824 * when the halt interrupt occurs. Halt the channel again if it does 1825 * occur. 1826 */ 1827 hcchar = DWC2_READ_4(hsotg, HCCHAR(chnum)); 1828 if (hcchar & HCCHAR_CHDIS) { 1829 dev_warn(hsotg->dev, 1830 "%s: hcchar.chdis set unexpectedly, hcchar 0x%08x, trying to halt again\n", 1831 __func__, hcchar); 1832 chan->halt_pending = 0; 1833 dwc2_halt_channel(hsotg, chan, qtd, chan->halt_status); 1834 return false; 1835 } 1836 #endif 1837 1838 return true; 1839 } 1840 1841 /* 1842 * Handles a host Channel Halted interrupt in DMA mode. This handler 1843 * determines the reason the channel halted and proceeds accordingly. 1844 */ 1845 static void dwc2_hc_chhltd_intr_dma(struct dwc2_hsotg *hsotg, 1846 struct dwc2_host_chan *chan, int chnum, 1847 struct dwc2_qtd *qtd) 1848 { 1849 u32 hcintmsk; 1850 int out_nak_enh = 0; 1851 1852 if (dbg_hc(chan)) 1853 dev_vdbg(hsotg->dev, 1854 "--Host Channel %d Interrupt: DMA Channel Halted--\n", 1855 chnum); 1856 1857 /* 1858 * For core with OUT NAK enhancement, the flow for high-speed 1859 * CONTROL/BULK OUT is handled a little differently 1860 */ 1861 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_71a) { 1862 if (chan->speed == USB_SPEED_HIGH && !chan->ep_is_in && 1863 (chan->ep_type == USB_ENDPOINT_XFER_CONTROL || 1864 chan->ep_type == USB_ENDPOINT_XFER_BULK)) { 1865 out_nak_enh = 1; 1866 } 1867 } 1868 1869 if (chan->halt_status == DWC2_HC_XFER_URB_DEQUEUE || 1870 (chan->halt_status == DWC2_HC_XFER_AHB_ERR && 1871 hsotg->core_params->dma_desc_enable <= 0)) { 1872 if (hsotg->core_params->dma_desc_enable > 0) 1873 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum, 1874 chan->halt_status); 1875 else 1876 /* 1877 * Just release the channel. A dequeue can happen on a 1878 * transfer timeout. In the case of an AHB Error, the 1879 * channel was forced to halt because there's no way to 1880 * gracefully recover. 1881 */ 1882 dwc2_release_channel(hsotg, chan, qtd, 1883 chan->halt_status); 1884 return; 1885 } 1886 1887 hcintmsk = DWC2_READ_4(hsotg, HCINTMSK(chnum)); 1888 1889 if (chan->hcint & HCINTMSK_XFERCOMPL) { 1890 /* 1891 * Todo: This is here because of a possible hardware bug. Spec 1892 * says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT 1893 * interrupt w/ACK bit set should occur, but I only see the 1894 * XFERCOMP bit, even with it masked out. This is a workaround 1895 * for that behavior. Should fix this when hardware is fixed. 1896 */ 1897 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC && !chan->ep_is_in) 1898 dwc2_hc_ack_intr(hsotg, chan, chnum, qtd); 1899 dwc2_hc_xfercomp_intr(hsotg, chan, chnum, qtd); 1900 } else if (chan->hcint & HCINTMSK_STALL) { 1901 dwc2_hc_stall_intr(hsotg, chan, chnum, qtd); 1902 } else if ((chan->hcint & HCINTMSK_XACTERR) && 1903 hsotg->core_params->dma_desc_enable <= 0) { 1904 if (out_nak_enh) { 1905 if (chan->hcint & 1906 (HCINTMSK_NYET | HCINTMSK_NAK | HCINTMSK_ACK)) { 1907 dev_vdbg(hsotg->dev, 1908 "XactErr with NYET/NAK/ACK\n"); 1909 qtd->error_count = 0; 1910 } else { 1911 dev_vdbg(hsotg->dev, 1912 "XactErr without NYET/NAK/ACK\n"); 1913 } 1914 } 1915 1916 /* 1917 * Must handle xacterr before nak or ack. Could get a xacterr 1918 * at the same time as either of these on a BULK/CONTROL OUT 1919 * that started with a PING. The xacterr takes precedence. 1920 */ 1921 dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd); 1922 } else if ((chan->hcint & HCINTMSK_XCS_XACT) && 1923 hsotg->core_params->dma_desc_enable > 0) { 1924 dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd); 1925 } else if ((chan->hcint & HCINTMSK_AHBERR) && 1926 hsotg->core_params->dma_desc_enable > 0) { 1927 dwc2_hc_ahberr_intr(hsotg, chan, chnum, qtd); 1928 } else if (chan->hcint & HCINTMSK_BBLERR) { 1929 dwc2_hc_babble_intr(hsotg, chan, chnum, qtd); 1930 } else if (chan->hcint & HCINTMSK_FRMOVRUN) { 1931 dwc2_hc_frmovrun_intr(hsotg, chan, chnum, qtd); 1932 } else if (!out_nak_enh) { 1933 if (chan->hcint & HCINTMSK_NYET) { 1934 /* 1935 * Must handle nyet before nak or ack. Could get a nyet 1936 * at the same time as either of those on a BULK/CONTROL 1937 * OUT that started with a PING. The nyet takes 1938 * precedence. 1939 */ 1940 dwc2_hc_nyet_intr(hsotg, chan, chnum, qtd); 1941 } else if ((chan->hcint & HCINTMSK_NAK) && 1942 !(hcintmsk & HCINTMSK_NAK)) { 1943 /* 1944 * If nak is not masked, it's because a non-split IN 1945 * transfer is in an error state. In that case, the nak 1946 * is handled by the nak interrupt handler, not here. 1947 * Handle nak here for BULK/CONTROL OUT transfers, which 1948 * halt on a NAK to allow rewinding the buffer pointer. 1949 */ 1950 dwc2_hc_nak_intr(hsotg, chan, chnum, qtd); 1951 } else if ((chan->hcint & HCINTMSK_ACK) && 1952 !(hcintmsk & HCINTMSK_ACK)) { 1953 /* 1954 * If ack is not masked, it's because a non-split IN 1955 * transfer is in an error state. In that case, the ack 1956 * is handled by the ack interrupt handler, not here. 1957 * Handle ack here for split transfers. Start splits 1958 * halt on ACK. 1959 */ 1960 dwc2_hc_ack_intr(hsotg, chan, chnum, qtd); 1961 } else { 1962 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1963 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 1964 /* 1965 * A periodic transfer halted with no other 1966 * channel interrupts set. Assume it was halted 1967 * by the core because it could not be completed 1968 * in its scheduled (micro)frame. 1969 */ 1970 dev_dbg(hsotg->dev, 1971 "%s: Halt channel %d (assume incomplete periodic transfer)\n", 1972 __func__, chnum); 1973 dwc2_halt_channel(hsotg, chan, qtd, 1974 DWC2_HC_XFER_PERIODIC_INCOMPLETE); 1975 } else { 1976 dev_err(hsotg->dev, 1977 "%s: Channel %d - ChHltd set, but reason is unknown\n", 1978 __func__, chnum); 1979 dev_err(hsotg->dev, 1980 "hcint 0x%08x, intsts 0x%08x\n", 1981 chan->hcint, 1982 DWC2_READ_4(hsotg, GINTSTS)); 1983 goto error; 1984 } 1985 } 1986 } else { 1987 dev_info(hsotg->dev, 1988 "NYET/NAK/ACK/other in non-error case, 0x%08x\n", 1989 chan->hcint); 1990 error: 1991 /* Failthrough: use 3-strikes rule */ 1992 qtd->error_count++; 1993 dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb, 1994 qtd, DWC2_HC_XFER_XACT_ERR); 1995 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd); 1996 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR); 1997 } 1998 } 1999 2000 /* 2001 * Handles a host channel Channel Halted interrupt 2002 * 2003 * In slave mode, this handler is called only when the driver specifically 2004 * requests a halt. This occurs during handling other host channel interrupts 2005 * (e.g. nak, xacterr, stall, nyet, etc.). 2006 * 2007 * In DMA mode, this is the interrupt that occurs when the core has finished 2008 * processing a transfer on a channel. Other host channel interrupts (except 2009 * ahberr) are disabled in DMA mode. 2010 */ 2011 static void dwc2_hc_chhltd_intr(struct dwc2_hsotg *hsotg, 2012 struct dwc2_host_chan *chan, int chnum, 2013 struct dwc2_qtd *qtd) 2014 { 2015 if (dbg_hc(chan)) 2016 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: Channel Halted--\n", 2017 chnum); 2018 2019 if (hsotg->core_params->dma_enable > 0) { 2020 dwc2_hc_chhltd_intr_dma(hsotg, chan, chnum, qtd); 2021 } else { 2022 if (!dwc2_halt_status_ok(hsotg, chan, chnum, qtd)) 2023 return; 2024 dwc2_release_channel(hsotg, chan, qtd, chan->halt_status); 2025 } 2026 } 2027 2028 /* 2029 * Check if the given qtd is still the top of the list (and thus valid). 2030 * 2031 * If dwc2_hcd_qtd_unlink_and_free() has been called since we grabbed 2032 * the qtd from the top of the list, this will return false (otherwise true). 2033 */ 2034 static bool dwc2_check_qtd_still_ok(struct dwc2_qtd *qtd, struct dwc2_qh *qh) 2035 { 2036 struct dwc2_qtd *cur_head; 2037 2038 if (qh == NULL) 2039 return false; 2040 2041 cur_head = list_first_entry(&qh->qtd_list, struct dwc2_qtd, 2042 qtd_list_entry); 2043 return (cur_head == qtd); 2044 } 2045 2046 /* Handles interrupt for a specific Host Channel */ 2047 static void dwc2_hc_n_intr(struct dwc2_hsotg *hsotg, int chnum) 2048 { 2049 struct dwc2_qtd *qtd; 2050 struct dwc2_host_chan *chan; 2051 u32 hcint, hcintmsk; 2052 2053 chan = hsotg->hc_ptr_array[chnum]; 2054 2055 hcint = DWC2_READ_4(hsotg, HCINT(chnum)); 2056 hcintmsk = DWC2_READ_4(hsotg, HCINTMSK(chnum)); 2057 if (!chan) { 2058 dev_err(hsotg->dev, "## hc_ptr_array for channel is NULL ##\n"); 2059 DWC2_WRITE_4(hsotg, HCINT(chnum), hcint); 2060 return; 2061 } 2062 2063 if (dbg_hc(chan)) { 2064 dev_vdbg(hsotg->dev, "--Host Channel Interrupt--, Channel %d\n", 2065 chnum); 2066 dev_vdbg(hsotg->dev, 2067 " hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n", 2068 hcint, hcintmsk, hcint & hcintmsk); 2069 } 2070 2071 DWC2_WRITE_4(hsotg, HCINT(chnum), hcint); 2072 chan->hcint = hcint; 2073 hcint &= hcintmsk; 2074 2075 /* 2076 * If the channel was halted due to a dequeue, the qtd list might 2077 * be empty or at least the first entry will not be the active qtd. 2078 * In this case, take a shortcut and just release the channel. 2079 */ 2080 if (chan->halt_status == DWC2_HC_XFER_URB_DEQUEUE) { 2081 /* 2082 * If the channel was halted, this should be the only 2083 * interrupt unmasked 2084 */ 2085 WARN_ON(hcint != HCINTMSK_CHHLTD); 2086 if (hsotg->core_params->dma_desc_enable > 0) 2087 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum, 2088 chan->halt_status); 2089 else 2090 dwc2_release_channel(hsotg, chan, NULL, 2091 chan->halt_status); 2092 return; 2093 } 2094 2095 if (list_empty(&chan->qh->qtd_list)) { 2096 /* 2097 * TODO: Will this ever happen with the 2098 * DWC2_HC_XFER_URB_DEQUEUE handling above? 2099 */ 2100 dev_dbg(hsotg->dev, "## no QTD queued for channel %d ##\n", 2101 chnum); 2102 dev_dbg(hsotg->dev, 2103 " hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n", 2104 chan->hcint, hcintmsk, hcint); 2105 chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS; 2106 disable_hc_int(hsotg, chnum, HCINTMSK_CHHLTD); 2107 chan->hcint = 0; 2108 return; 2109 } 2110 2111 qtd = list_first_entry(&chan->qh->qtd_list, struct dwc2_qtd, 2112 qtd_list_entry); 2113 2114 if (hsotg->core_params->dma_enable <= 0) { 2115 if ((hcint & HCINTMSK_CHHLTD) && hcint != HCINTMSK_CHHLTD) 2116 hcint &= ~HCINTMSK_CHHLTD; 2117 } 2118 2119 if (hcint & HCINTMSK_XFERCOMPL) { 2120 dwc2_hc_xfercomp_intr(hsotg, chan, chnum, qtd); 2121 /* 2122 * If NYET occurred at same time as Xfer Complete, the NYET is 2123 * handled by the Xfer Complete interrupt handler. Don't want 2124 * to call the NYET interrupt handler in this case. 2125 */ 2126 hcint &= ~HCINTMSK_NYET; 2127 } 2128 2129 if (hcint & HCINTMSK_CHHLTD) { 2130 dwc2_hc_chhltd_intr(hsotg, chan, chnum, qtd); 2131 if (!dwc2_check_qtd_still_ok(qtd, chan->qh)) 2132 goto exit; 2133 } 2134 if (hcint & HCINTMSK_AHBERR) { 2135 dwc2_hc_ahberr_intr(hsotg, chan, chnum, qtd); 2136 if (!dwc2_check_qtd_still_ok(qtd, chan->qh)) 2137 goto exit; 2138 } 2139 if (hcint & HCINTMSK_STALL) { 2140 dwc2_hc_stall_intr(hsotg, chan, chnum, qtd); 2141 if (!dwc2_check_qtd_still_ok(qtd, chan->qh)) 2142 goto exit; 2143 } 2144 if (hcint & HCINTMSK_NAK) { 2145 dwc2_hc_nak_intr(hsotg, chan, chnum, qtd); 2146 if (!dwc2_check_qtd_still_ok(qtd, chan->qh)) 2147 goto exit; 2148 } 2149 if (hcint & HCINTMSK_ACK) { 2150 dwc2_hc_ack_intr(hsotg, chan, chnum, qtd); 2151 if (!dwc2_check_qtd_still_ok(qtd, chan->qh)) 2152 goto exit; 2153 } 2154 if (hcint & HCINTMSK_NYET) { 2155 dwc2_hc_nyet_intr(hsotg, chan, chnum, qtd); 2156 if (!dwc2_check_qtd_still_ok(qtd, chan->qh)) 2157 goto exit; 2158 } 2159 if (hcint & HCINTMSK_XACTERR) { 2160 dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd); 2161 if (!dwc2_check_qtd_still_ok(qtd, chan->qh)) 2162 goto exit; 2163 } 2164 if (hcint & HCINTMSK_BBLERR) { 2165 dwc2_hc_babble_intr(hsotg, chan, chnum, qtd); 2166 if (!dwc2_check_qtd_still_ok(qtd, chan->qh)) 2167 goto exit; 2168 } 2169 if (hcint & HCINTMSK_FRMOVRUN) { 2170 dwc2_hc_frmovrun_intr(hsotg, chan, chnum, qtd); 2171 if (!dwc2_check_qtd_still_ok(qtd, chan->qh)) 2172 goto exit; 2173 } 2174 if (hcint & HCINTMSK_DATATGLERR) { 2175 dwc2_hc_datatglerr_intr(hsotg, chan, chnum, qtd); 2176 if (!dwc2_check_qtd_still_ok(qtd, chan->qh)) 2177 goto exit; 2178 } 2179 2180 exit: 2181 chan->hcint = 0; 2182 } 2183 2184 /* 2185 * This interrupt indicates that one or more host channels has a pending 2186 * interrupt. There are multiple conditions that can cause each host channel 2187 * interrupt. This function determines which conditions have occurred for each 2188 * host channel interrupt and handles them appropriately. 2189 */ 2190 static void dwc2_hc_intr(struct dwc2_hsotg *hsotg) 2191 { 2192 u32 haint; 2193 int i; 2194 2195 haint = DWC2_READ_4(hsotg, HAINT); 2196 if (dbg_perio()) { 2197 dev_vdbg(hsotg->dev, "%s()\n", __func__); 2198 2199 dev_vdbg(hsotg->dev, "HAINT=%08x\n", haint); 2200 } 2201 2202 for (i = 0; i < hsotg->core_params->host_channels; i++) { 2203 if (haint & (1 << i)) 2204 dwc2_hc_n_intr(hsotg, i); 2205 } 2206 } 2207 2208 /* This function handles interrupts for the HCD */ 2209 irqreturn_t dwc2_handle_hcd_intr(struct dwc2_hsotg *hsotg) 2210 { 2211 u32 gintsts, dbg_gintsts; 2212 irqreturn_t retval = IRQ_NONE; 2213 2214 if (!dwc2_is_controller_alive(hsotg)) { 2215 dev_warn(hsotg->dev, "Controller is dead\n"); 2216 return retval; 2217 } 2218 2219 KASSERT(mutex_owned(&hsotg->lock)); 2220 2221 /* Check if HOST Mode */ 2222 if (dwc2_is_host_mode(hsotg)) { 2223 gintsts = dwc2_read_core_intr(hsotg); 2224 if (!gintsts) { 2225 return retval; 2226 } 2227 2228 retval = IRQ_HANDLED; 2229 2230 dbg_gintsts = gintsts; 2231 #ifndef DEBUG_SOF 2232 dbg_gintsts &= ~GINTSTS_SOF; 2233 #endif 2234 if (!dbg_perio()) 2235 dbg_gintsts &= ~(GINTSTS_HCHINT | GINTSTS_RXFLVL | 2236 GINTSTS_PTXFEMP); 2237 2238 /* Only print if there are any non-suppressed interrupts left */ 2239 if (dbg_gintsts) 2240 dev_vdbg(hsotg->dev, 2241 "DWC OTG HCD Interrupt Detected gintsts&gintmsk=0x%08x\n", 2242 gintsts); 2243 2244 if (gintsts & GINTSTS_SOF) 2245 dwc2_sof_intr(hsotg); 2246 if (gintsts & GINTSTS_RXFLVL) 2247 dwc2_rx_fifo_level_intr(hsotg); 2248 if (gintsts & GINTSTS_NPTXFEMP) 2249 dwc2_np_tx_fifo_empty_intr(hsotg); 2250 if (gintsts & GINTSTS_PRTINT) 2251 dwc2_port_intr(hsotg); 2252 if (gintsts & GINTSTS_HCHINT) 2253 dwc2_hc_intr(hsotg); 2254 if (gintsts & GINTSTS_PTXFEMP) 2255 dwc2_perio_tx_fifo_empty_intr(hsotg); 2256 2257 if (dbg_gintsts) { 2258 dev_vdbg(hsotg->dev, 2259 "DWC OTG HCD Finished Servicing Interrupts\n"); 2260 dev_vdbg(hsotg->dev, 2261 "DWC OTG HCD gintsts=0x%08x gintmsk=0x%08x\n", 2262 DWC2_READ_4(hsotg, GINTSTS), 2263 DWC2_READ_4(hsotg, GINTMSK)); 2264 } 2265 } 2266 2267 return retval; 2268 } 2269
Indexes created Sun Sep 21 20:09:37 GMT 2025