1 /* $NetBSD: dwc2_hcd.c,v 1.26 2021/12/21 09:51:22 skrll Exp $ */ 2 3 /* 4 * hcd.c - DesignWare HS OTG Controller host-mode routines 5 * 6 * Copyright (C) 2004-2013 Synopsys, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The names of the above-listed copyright holders may not be used 18 * to endorse or promote products derived from this software without 19 * specific prior written permission. 20 * 21 * ALTERNATIVELY, this software may be distributed under the terms of the 22 * GNU General Public License ("GPL") as published by the Free Software 23 * Foundation; either version 2 of the License, or (at your option) any 24 * later version. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * This file contains the core HCD code, and implements the Linux hc_driver 41 * API 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: dwc2_hcd.c,v 1.26 2021/12/21 09:51:22 skrll Exp $"); 46 47 #include <sys/types.h> 48 #include <sys/kmem.h> 49 #include <sys/proc.h> 50 #include <sys/pool.h> 51 52 #include <dev/usb/usb.h> 53 #include <dev/usb/usbdi.h> 54 #include <dev/usb/usbdivar.h> 55 #include <dev/usb/usb_mem.h> 56 57 #include <linux/kernel.h> 58 #include <linux/list.h> 59 #include <linux/err.h> 60 #include <linux/workqueue.h> 61 62 #include <dwc2/dwc2.h> 63 #include <dwc2/dwc2var.h> 64 65 #include "dwc2_core.h" 66 #include "dwc2_hcd.h" 67 68 /** 69 * dwc2_dump_channel_info() - Prints the state of a host channel 70 * 71 * @hsotg: Programming view of DWC_otg controller 72 * @chan: Pointer to the channel to dump 73 * 74 * Must be called with interrupt disabled and spinlock held 75 * 76 * NOTE: This function will be removed once the peripheral controller code 77 * is integrated and the driver is stable 78 */ 79 #ifdef VERBOSE_DEBUG 80 static void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg, 81 struct dwc2_host_chan *chan) 82 { 83 int num_channels = hsotg->core_params->host_channels; 84 struct dwc2_qh *qh; 85 u32 hcchar; 86 u32 hcsplt; 87 u32 hctsiz; 88 u32 hc_dma; 89 int i; 90 91 if (chan == NULL) 92 return; 93 94 hcchar = DWC2_READ_4(hsotg, HCCHAR(chan->hc_num)); 95 hcsplt = DWC2_READ_4(hsotg, HCSPLT(chan->hc_num)); 96 hctsiz = DWC2_READ_4(hsotg, HCTSIZ(chan->hc_num)); 97 hc_dma = DWC2_READ_4(hsotg, HCDMA(chan->hc_num)); 98 99 dev_dbg(hsotg->dev, " Assigned to channel %p:\n", chan); 100 dev_dbg(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n", 101 hcchar, hcsplt); 102 dev_dbg(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n", 103 hctsiz, hc_dma); 104 dev_dbg(hsotg->dev, " dev_addr: %d, ep_num: %d, ep_is_in: %d\n", 105 chan->dev_addr, chan->ep_num, chan->ep_is_in); 106 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type); 107 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet); 108 dev_dbg(hsotg->dev, " data_pid_start: %d\n", chan->data_pid_start); 109 dev_dbg(hsotg->dev, " xfer_started: %d\n", chan->xfer_started); 110 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status); 111 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf); 112 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n", 113 (unsigned long)chan->xfer_dma); 114 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len); 115 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh); 116 dev_dbg(hsotg->dev, " NP inactive sched:\n"); 117 list_for_each_entry(qh, &hsotg->non_periodic_sched_inactive, 118 qh_list_entry) 119 dev_dbg(hsotg->dev, " %p\n", qh); 120 dev_dbg(hsotg->dev, " NP waiting sched:\n"); 121 list_for_each_entry(qh, &hsotg->non_periodic_sched_waiting, 122 qh_list_entry) 123 dev_dbg(hsotg->dev, " %p\n", qh); 124 dev_dbg(hsotg->dev, " NP active sched:\n"); 125 list_for_each_entry(qh, &hsotg->non_periodic_sched_active, 126 qh_list_entry) 127 dev_dbg(hsotg->dev, " %p\n", qh); 128 dev_dbg(hsotg->dev, " Channels:\n"); 129 for (i = 0; i < num_channels; i++) { 130 struct dwc2_host_chan *ch = hsotg->hc_ptr_array[i]; 131 132 dev_dbg(hsotg->dev, " %2d: %p\n", i, ch); 133 } 134 } 135 #endif /* VERBOSE_DEBUG */ 136 137 /* 138 * Processes all the URBs in a single list of QHs. Completes them with 139 * -ETIMEDOUT and frees the QTD. 140 * 141 * Must be called with interrupt disabled and spinlock held 142 */ 143 static void dwc2_kill_urbs_in_qh_list(struct dwc2_hsotg *hsotg, 144 struct list_head *qh_list) 145 { 146 struct dwc2_qh *qh, *qh_tmp; 147 struct dwc2_qtd *qtd, *qtd_tmp; 148 149 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) { 150 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, 151 qtd_list_entry) { 152 dwc2_host_complete(hsotg, qtd, -ECONNRESET); 153 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 154 } 155 } 156 } 157 158 static void dwc2_qh_list_free(struct dwc2_hsotg *hsotg, 159 struct list_head *qh_list) 160 { 161 struct dwc2_qtd *qtd, *qtd_tmp; 162 struct dwc2_qh *qh, *qh_tmp; 163 unsigned long flags; 164 165 if (!qh_list->next) 166 /* The list hasn't been initialized yet */ 167 return; 168 169 spin_lock_irqsave(&hsotg->lock, flags); 170 171 /* Ensure there are no QTDs or URBs left */ 172 dwc2_kill_urbs_in_qh_list(hsotg, qh_list); 173 174 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) { 175 dwc2_hcd_qh_unlink(hsotg, qh); 176 177 /* Free each QTD in the QH's QTD list */ 178 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, 179 qtd_list_entry) 180 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 181 182 spin_unlock_irqrestore(&hsotg->lock, flags); 183 dwc2_hcd_qh_free(hsotg, qh); 184 spin_lock_irqsave(&hsotg->lock, flags); 185 } 186 187 spin_unlock_irqrestore(&hsotg->lock, flags); 188 } 189 190 /* 191 * Responds with an error status of -ETIMEDOUT to all URBs in the non-periodic 192 * and periodic schedules. The QTD associated with each URB is removed from 193 * the schedule and freed. This function may be called when a disconnect is 194 * detected or when the HCD is being stopped. 195 * 196 * Must be called with interrupt disabled and spinlock held 197 */ 198 static void dwc2_kill_all_urbs(struct dwc2_hsotg *hsotg) 199 { 200 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_inactive); 201 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_waiting); 202 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_active); 203 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_inactive); 204 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_ready); 205 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_assigned); 206 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_queued); 207 } 208 209 /** 210 * dwc2_hcd_start() - Starts the HCD when switching to Host mode 211 * 212 * @hsotg: Pointer to struct dwc2_hsotg 213 */ 214 void dwc2_hcd_start(struct dwc2_hsotg *hsotg) 215 { 216 u32 hprt0; 217 218 if (hsotg->op_state == OTG_STATE_B_HOST) { 219 /* 220 * Reset the port. During a HNP mode switch the reset 221 * needs to occur within 1ms and have a duration of at 222 * least 50ms. 223 */ 224 hprt0 = dwc2_read_hprt0(hsotg); 225 hprt0 |= HPRT0_RST; 226 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 227 } 228 229 queue_delayed_work(hsotg->wq_otg, &hsotg->start_work, 230 msecs_to_jiffies(50)); 231 } 232 233 /* Must be called with interrupt disabled and spinlock held */ 234 static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg) 235 { 236 int num_channels = hsotg->core_params->host_channels; 237 struct dwc2_host_chan *channel; 238 u32 hcchar; 239 int i; 240 241 if (hsotg->core_params->dma_enable <= 0) { 242 /* Flush out any channel requests in slave mode */ 243 for (i = 0; i < num_channels; i++) { 244 channel = hsotg->hc_ptr_array[i]; 245 if (!list_empty(&channel->hc_list_entry)) 246 continue; 247 hcchar = DWC2_READ_4(hsotg, HCCHAR(i)); 248 if (hcchar & HCCHAR_CHENA) { 249 hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR); 250 hcchar |= HCCHAR_CHDIS; 251 DWC2_WRITE_4(hsotg, HCCHAR(i), hcchar); 252 } 253 } 254 } 255 256 for (i = 0; i < num_channels; i++) { 257 channel = hsotg->hc_ptr_array[i]; 258 if (!list_empty(&channel->hc_list_entry)) 259 continue; 260 hcchar = DWC2_READ_4(hsotg, HCCHAR(i)); 261 if (hcchar & HCCHAR_CHENA) { 262 /* Halt the channel */ 263 hcchar |= HCCHAR_CHDIS; 264 DWC2_WRITE_4(hsotg, HCCHAR(i), hcchar); 265 } 266 267 dwc2_hc_cleanup(hsotg, channel); 268 list_add_tail(&channel->hc_list_entry, &hsotg->free_hc_list); 269 /* 270 * Added for Descriptor DMA to prevent channel double cleanup in 271 * release_channel_ddma(), which is called from ep_disable when 272 * device disconnects 273 */ 274 channel->qh = NULL; 275 } 276 /* All channels have been freed, mark them available */ 277 if (hsotg->core_params->uframe_sched > 0) { 278 hsotg->available_host_channels = 279 hsotg->core_params->host_channels; 280 } else { 281 hsotg->non_periodic_channels = 0; 282 hsotg->periodic_channels = 0; 283 } 284 } 285 286 /** 287 * dwc2_hcd_connect() - Handles connect of the HCD 288 * 289 * @hsotg: Pointer to struct dwc2_hsotg 290 * 291 * Must be called with interrupt disabled and spinlock held 292 */ 293 void dwc2_hcd_connect(struct dwc2_hsotg *hsotg) 294 { 295 if (hsotg->lx_state != DWC2_L0) 296 usb_hcd_resume_root_hub(hsotg->priv); 297 298 hsotg->flags.b.port_connect_status_change = 1; 299 hsotg->flags.b.port_connect_status = 1; 300 } 301 302 /** 303 * dwc2_hcd_disconnect() - Handles disconnect of the HCD 304 * 305 * @hsotg: Pointer to struct dwc2_hsotg 306 * @force: If true, we won't try to reconnect even if we see device connected. 307 * 308 * Must be called with interrupt disabled and spinlock held 309 */ 310 void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) 311 { 312 u32 intr; 313 u32 hprt0; 314 315 /* Set status flags for the hub driver */ 316 hsotg->flags.b.port_connect_status_change = 1; 317 hsotg->flags.b.port_connect_status = 0; 318 319 /* 320 * Shutdown any transfers in process by clearing the Tx FIFO Empty 321 * interrupt mask and status bits and disabling subsequent host 322 * channel interrupts. 323 */ 324 intr = DWC2_READ_4(hsotg, GINTMSK); 325 intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT); 326 DWC2_WRITE_4(hsotg, GINTMSK, intr); 327 intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT; 328 DWC2_WRITE_4(hsotg, GINTSTS, intr); 329 330 /* 331 * Turn off the vbus power only if the core has transitioned to device 332 * mode. If still in host mode, need to keep power on to detect a 333 * reconnection. 334 */ 335 if (dwc2_is_device_mode(hsotg)) { 336 if (hsotg->op_state != OTG_STATE_A_SUSPEND) { 337 dev_dbg(hsotg->dev, "Disconnect: PortPower off\n"); 338 DWC2_WRITE_4(hsotg, HPRT0, 0); 339 } 340 341 dwc2_disable_host_interrupts(hsotg); 342 } 343 344 /* Respond with an error status to all URBs in the schedule */ 345 dwc2_kill_all_urbs(hsotg); 346 347 if (dwc2_is_host_mode(hsotg)) 348 /* Clean up any host channels that were in use */ 349 dwc2_hcd_cleanup_channels(hsotg); 350 351 dwc2_host_disconnect(hsotg); 352 353 dwc2_root_intr(hsotg->hsotg_sc); 354 355 /* 356 * Add an extra check here to see if we're actually connected but 357 * we don't have a detection interrupt pending. This can happen if: 358 * 1. hardware sees connect 359 * 2. hardware sees disconnect 360 * 3. hardware sees connect 361 * 4. dwc2_port_intr() - clears connect interrupt 362 * 5. dwc2_handle_common_intr() - calls here 363 * 364 * Without the extra check here we will end calling disconnect 365 * and won't get any future interrupts to handle the connect. 366 */ 367 if (!force) { 368 hprt0 = DWC2_READ_4(hsotg, HPRT0); 369 if (!(hprt0 & HPRT0_CONNDET) && (hprt0 & HPRT0_CONNSTS)) 370 dwc2_hcd_connect(hsotg); 371 } 372 } 373 374 /** 375 * dwc2_hcd_rem_wakeup() - Handles Remote Wakeup 376 * 377 * @hsotg: Pointer to struct dwc2_hsotg 378 */ 379 static void dwc2_hcd_rem_wakeup(struct dwc2_hsotg *hsotg) 380 { 381 if (hsotg->bus_suspended) { 382 hsotg->flags.b.port_suspend_change = 1; 383 usb_hcd_resume_root_hub(hsotg->priv); 384 } 385 386 if (hsotg->lx_state == DWC2_L1) 387 hsotg->flags.b.port_l1_change = 1; 388 389 dwc2_root_intr(hsotg->hsotg_sc); 390 } 391 392 /** 393 * dwc2_hcd_stop() - Halts the DWC_otg host mode operations in a clean manner 394 * 395 * @hsotg: Pointer to struct dwc2_hsotg 396 * 397 * Must be called with interrupt disabled and spinlock held 398 */ 399 void dwc2_hcd_stop(struct dwc2_hsotg *hsotg) 400 { 401 dev_dbg(hsotg->dev, "DWC OTG HCD STOP\n"); 402 403 /* 404 * The root hub should be disconnected before this function is called. 405 * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue) 406 * and the QH lists (via ..._hcd_endpoint_disable). 407 */ 408 409 /* Turn off all host-specific interrupts */ 410 dwc2_disable_host_interrupts(hsotg); 411 412 /* Turn off the vbus power */ 413 dev_dbg(hsotg->dev, "PortPower off\n"); 414 DWC2_WRITE_4(hsotg, HPRT0, 0); 415 } 416 417 /* Caller must hold driver lock */ 418 int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg, 419 struct dwc2_hcd_urb *urb, struct dwc2_qh *qh, 420 struct dwc2_qtd *qtd) 421 { 422 u32 intr_mask; 423 int retval; 424 int dev_speed; 425 426 if (!hsotg->flags.b.port_connect_status) { 427 /* No longer connected */ 428 dev_err(hsotg->dev, "Not connected\n"); 429 return -ENODEV; 430 } 431 432 dev_speed = dwc2_host_get_speed(hsotg, urb->priv); 433 434 /* Some configurations cannot support LS traffic on a FS root port */ 435 if ((dev_speed == USB_SPEED_LOW) && 436 (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) && 437 (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) { 438 u32 hprt0 = DWC2_READ_4(hsotg, HPRT0); 439 u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; 440 441 if (prtspd == HPRT0_SPD_FULL_SPEED) { 442 dev_err(hsotg->dev, 443 "DWC OTG HCD URB Enqueue unsupported\n"); 444 return -ENODEV; 445 } 446 } 447 448 if (!qtd) 449 return -EINVAL; 450 451 memset(qtd, 0, sizeof(*qtd)); 452 453 dwc2_hcd_qtd_init(qtd, urb); 454 retval = dwc2_hcd_qtd_add(hsotg, qtd, qh); 455 if (retval) { 456 dev_err(hsotg->dev, 457 "DWC OTG HCD URB Enqueue failed adding QTD. Error status %d\n", 458 retval); 459 return retval; 460 } 461 462 intr_mask = DWC2_READ_4(hsotg, GINTMSK); 463 if (!(intr_mask & GINTSTS_SOF)) { 464 enum dwc2_transaction_type tr_type; 465 466 if (qtd->qh->ep_type == USB_ENDPOINT_XFER_BULK && 467 !(qtd->urb->flags & URB_GIVEBACK_ASAP)) 468 /* 469 * Do not schedule SG transactions until qtd has 470 * URB_GIVEBACK_ASAP set 471 */ 472 return 0; 473 474 tr_type = dwc2_hcd_select_transactions(hsotg); 475 if (tr_type != DWC2_TRANSACTION_NONE) 476 dwc2_hcd_queue_transactions(hsotg, tr_type); 477 } 478 479 return 0; 480 } 481 482 /* Must be called with interrupt disabled and spinlock held */ 483 int 484 dwc2_hcd_urb_dequeue(struct dwc2_hsotg *hsotg, 485 struct dwc2_hcd_urb *urb) 486 { 487 struct dwc2_qh *qh; 488 struct dwc2_qtd *urb_qtd; 489 490 urb_qtd = urb->qtd; 491 if (!urb_qtd) { 492 dev_dbg(hsotg->dev, "## Urb QTD is NULL ##\n"); 493 return -EINVAL; 494 } 495 496 qh = urb_qtd->qh; 497 if (!qh) { 498 dev_dbg(hsotg->dev, "## Urb QTD QH is NULL ##\n"); 499 return -EINVAL; 500 } 501 502 urb->priv = NULL; 503 504 if (urb_qtd->in_process && qh->channel) { 505 #ifdef VERBOSE_DEBUG 506 dwc2_dump_channel_info(hsotg, qh->channel); 507 #endif 508 /* The QTD is in process (it has been assigned to a channel) */ 509 if (hsotg->flags.b.port_connect_status) 510 /* 511 * If still connected (i.e. in host mode), halt the 512 * channel so it can be used for other transfers. If 513 * no longer connected, the host registers can't be 514 * written to halt the channel since the core is in 515 * device mode. 516 */ 517 dwc2_hc_halt(hsotg, qh->channel, 518 DWC2_HC_XFER_URB_DEQUEUE); 519 } 520 521 /* 522 * Free the QTD and clean up the associated QH. Leave the QH in the 523 * schedule if it has any remaining QTDs. 524 */ 525 if (hsotg->core_params->dma_desc_enable <= 0) { 526 u8 in_process = urb_qtd->in_process; 527 528 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh); 529 if (in_process) { 530 dwc2_hcd_qh_deactivate(hsotg, qh, 0); 531 qh->channel = NULL; 532 } else if (list_empty(&qh->qtd_list)) { 533 dwc2_hcd_qh_unlink(hsotg, qh); 534 } 535 } else { 536 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh); 537 } 538 539 return 0; 540 } 541 542 543 /* 544 * Initializes dynamic portions of the DWC_otg HCD state 545 * 546 * Must be called with interrupt disabled and spinlock held 547 */ 548 void 549 dwc2_hcd_reinit(struct dwc2_hsotg *hsotg) 550 { 551 struct dwc2_host_chan *chan, *chan_tmp; 552 int num_channels; 553 int i; 554 555 hsotg->flags.d32 = 0; 556 hsotg->non_periodic_qh_ptr = &hsotg->non_periodic_sched_active; 557 558 if (hsotg->core_params->uframe_sched > 0) { 559 hsotg->available_host_channels = 560 hsotg->core_params->host_channels; 561 } else { 562 hsotg->non_periodic_channels = 0; 563 hsotg->periodic_channels = 0; 564 } 565 566 /* 567 * Put all channels in the free channel list and clean up channel 568 * states 569 */ 570 list_for_each_entry_safe(chan, chan_tmp, &hsotg->free_hc_list, 571 hc_list_entry) 572 list_del_init(&chan->hc_list_entry); 573 574 num_channels = hsotg->core_params->host_channels; 575 for (i = 0; i < num_channels; i++) { 576 chan = hsotg->hc_ptr_array[i]; 577 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list); 578 dwc2_hc_cleanup(hsotg, chan); 579 } 580 581 /* Initialize the DWC core for host mode operation */ 582 dwc2_core_host_init(hsotg); 583 } 584 585 static void dwc2_hc_init_split(struct dwc2_hsotg *hsotg, 586 struct dwc2_host_chan *chan, 587 struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb) 588 { 589 int hub_addr, hub_port; 590 591 chan->do_split = 1; 592 chan->xact_pos = qtd->isoc_split_pos; 593 chan->complete_split = qtd->complete_split; 594 dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port); 595 chan->hub_addr = (u8)hub_addr; 596 chan->hub_port = (u8)hub_port; 597 } 598 599 static void *dwc2_hc_init_xfer_data(struct dwc2_hsotg *hsotg, 600 struct dwc2_host_chan *chan, 601 struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb) 602 { 603 if (hsotg->core_params->dma_enable > 0) { 604 chan->xfer_dma = DMAADDR(urb->usbdma, urb->actual_length); 605 606 /* For non-dword aligned case */ 607 if (hsotg->core_params->dma_desc_enable <= 0 && 608 (chan->xfer_dma & 0x3)) 609 return (u8 *)urb->buf + urb->actual_length; 610 } else { 611 chan->xfer_buf = (u8 *)urb->buf + urb->actual_length; 612 } 613 614 return NULL; 615 } 616 617 static void *dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg, 618 struct dwc2_host_chan *chan, 619 struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb) 620 { 621 struct dwc2_hcd_iso_packet_desc *frame_desc; 622 void *bufptr = NULL; 623 624 switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) { 625 case USB_ENDPOINT_XFER_CONTROL: 626 chan->ep_type = USB_ENDPOINT_XFER_CONTROL; 627 628 switch (qtd->control_phase) { 629 case DWC2_CONTROL_SETUP: 630 dev_vdbg(hsotg->dev, " Control setup transaction\n"); 631 chan->do_ping = 0; 632 chan->ep_is_in = 0; 633 chan->data_pid_start = DWC2_HC_PID_SETUP; 634 if (hsotg->core_params->dma_enable > 0) 635 chan->xfer_dma = urb->setup_dma; 636 else 637 chan->xfer_buf = urb->setup_packet; 638 chan->xfer_len = 8; 639 break; 640 641 case DWC2_CONTROL_DATA: 642 dev_vdbg(hsotg->dev, " Control data transaction\n"); 643 chan->data_pid_start = qtd->data_toggle; 644 bufptr = dwc2_hc_init_xfer_data(hsotg, chan, qtd, urb); 645 break; 646 647 case DWC2_CONTROL_STATUS: 648 /* 649 * Direction is opposite of data direction or IN if no 650 * data 651 */ 652 dev_vdbg(hsotg->dev, " Control status transaction\n"); 653 if (urb->length == 0) 654 chan->ep_is_in = 1; 655 else 656 chan->ep_is_in = 657 dwc2_hcd_is_pipe_out(&urb->pipe_info); 658 if (chan->ep_is_in) 659 chan->do_ping = 0; 660 chan->data_pid_start = DWC2_HC_PID_DATA1; 661 chan->xfer_len = 0; 662 if (hsotg->core_params->dma_enable > 0) 663 chan->xfer_dma = hsotg->status_buf_dma; 664 else 665 chan->xfer_buf = hsotg->status_buf; 666 break; 667 } 668 break; 669 670 case USB_ENDPOINT_XFER_BULK: 671 chan->ep_type = USB_ENDPOINT_XFER_BULK; 672 bufptr = dwc2_hc_init_xfer_data(hsotg, chan, qtd, urb); 673 break; 674 675 case USB_ENDPOINT_XFER_INT: 676 chan->ep_type = USB_ENDPOINT_XFER_INT; 677 bufptr = dwc2_hc_init_xfer_data(hsotg, chan, qtd, urb); 678 break; 679 680 case USB_ENDPOINT_XFER_ISOC: 681 chan->ep_type = USB_ENDPOINT_XFER_ISOC; 682 if (hsotg->core_params->dma_desc_enable > 0) 683 break; 684 685 frame_desc = &urb->iso_descs[qtd->isoc_frame_index]; 686 frame_desc->status = 0; 687 688 if (hsotg->core_params->dma_enable > 0) { 689 chan->xfer_dma = urb->dma; 690 chan->xfer_dma += frame_desc->offset + 691 qtd->isoc_split_offset; 692 } else { 693 chan->xfer_buf = urb->buf; 694 chan->xfer_buf += frame_desc->offset + 695 qtd->isoc_split_offset; 696 } 697 698 chan->xfer_len = frame_desc->length - qtd->isoc_split_offset; 699 700 /* For non-dword aligned buffers */ 701 if (hsotg->core_params->dma_enable > 0 && 702 (chan->xfer_dma & 0x3)) 703 bufptr = (u8 *)urb->buf + frame_desc->offset + 704 qtd->isoc_split_offset; 705 706 if (chan->xact_pos == DWC2_HCSPLT_XACTPOS_ALL) { 707 if (chan->xfer_len <= 188) 708 chan->xact_pos = DWC2_HCSPLT_XACTPOS_ALL; 709 else 710 chan->xact_pos = DWC2_HCSPLT_XACTPOS_BEGIN; 711 } 712 break; 713 } 714 715 return bufptr; 716 } 717 718 static int dwc2_hc_setup_align_buf(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 719 struct dwc2_host_chan *chan, 720 struct dwc2_hcd_urb *urb, void *bufptr) 721 { 722 u32 buf_size; 723 724 if (!qh->dw_align_buf) { 725 int err; 726 727 if (chan->ep_type != USB_ENDPOINT_XFER_ISOC) 728 buf_size = hsotg->core_params->max_transfer_size; 729 else 730 /* 3072 = 3 max-size Isoc packets */ 731 buf_size = 3072; 732 733 qh->dw_align_buf = NULL; 734 qh->dw_align_buf_dma = 0; 735 err = usb_allocmem(hsotg->hsotg_sc->sc_bus.ub_dmatag, 736 buf_size, 0, USBMALLOC_COHERENT, &qh->dw_align_buf_usbdma); 737 if (!err) { 738 usb_dma_t *ud = &qh->dw_align_buf_usbdma; 739 740 qh->dw_align_buf = KERNADDR(ud, 0); 741 qh->dw_align_buf_dma = DMAADDR(ud, 0); 742 } 743 if (!qh->dw_align_buf) 744 return -ENOMEM; 745 qh->dw_align_buf_size = buf_size; 746 } 747 748 if (chan->xfer_len) { 749 dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n", __func__); 750 void *usb_urb = urb->priv; 751 752 if (usb_urb) { 753 if (!chan->ep_is_in) { 754 memcpy(qh->dw_align_buf, bufptr, 755 chan->xfer_len); 756 } 757 } else { 758 dev_warn(hsotg->dev, "no URB in dwc2_urb\n"); 759 } 760 } 761 762 usb_syncmem(&qh->dw_align_buf_usbdma, 0, qh->dw_align_buf_size, 763 chan->ep_is_in ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 764 765 chan->align_buf = qh->dw_align_buf_dma; 766 return 0; 767 } 768 769 /** 770 * dwc2_assign_and_init_hc() - Assigns transactions from a QTD to a free host 771 * channel and initializes the host channel to perform the transactions. The 772 * host channel is removed from the free list. 773 * 774 * @hsotg: The HCD state structure 775 * @qh: Transactions from the first QTD for this QH are selected and assigned 776 * to a free host channel 777 */ 778 static int dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 779 { 780 struct dwc2_host_chan *chan; 781 struct dwc2_hcd_urb *urb; 782 struct dwc2_qtd *qtd; 783 void *bufptr = NULL; 784 785 if (dbg_qh(qh)) 786 dev_vdbg(hsotg->dev, "%s(%p,%p)\n", __func__, hsotg, qh); 787 788 if (list_empty(&qh->qtd_list)) { 789 dev_dbg(hsotg->dev, "No QTDs in QH list\n"); 790 return -ENOMEM; 791 } 792 793 if (list_empty(&hsotg->free_hc_list)) { 794 dev_dbg(hsotg->dev, "No free channel to assign\n"); 795 return -ENOMEM; 796 } 797 798 chan = list_first_entry(&hsotg->free_hc_list, struct dwc2_host_chan, 799 hc_list_entry); 800 801 /* Remove host channel from free list */ 802 list_del_init(&chan->hc_list_entry); 803 804 qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry); 805 urb = qtd->urb; 806 qh->channel = chan; 807 qtd->in_process = 1; 808 809 /* 810 * Use usb_pipedevice to determine device address. This address is 811 * 0 before the SET_ADDRESS command and the correct address afterward. 812 */ 813 chan->dev_addr = dwc2_hcd_get_dev_addr(&urb->pipe_info); 814 chan->ep_num = dwc2_hcd_get_ep_num(&urb->pipe_info); 815 chan->speed = qh->dev_speed; 816 chan->max_packet = dwc2_max_packet(qh->maxp); 817 818 chan->xfer_started = 0; 819 chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS; 820 chan->error_state = (qtd->error_count > 0); 821 chan->halt_on_queue = 0; 822 chan->halt_pending = 0; 823 chan->requests = 0; 824 825 /* 826 * The following values may be modified in the transfer type section 827 * below. The xfer_len value may be reduced when the transfer is 828 * started to accommodate the max widths of the XferSize and PktCnt 829 * fields in the HCTSIZn register. 830 */ 831 832 chan->ep_is_in = (dwc2_hcd_is_pipe_in(&urb->pipe_info) != 0); 833 if (chan->ep_is_in) 834 chan->do_ping = 0; 835 else 836 chan->do_ping = qh->ping_state; 837 838 chan->data_pid_start = qh->data_toggle; 839 chan->multi_count = 1; 840 841 if (urb->actual_length > urb->length && 842 !dwc2_hcd_is_pipe_in(&urb->pipe_info)) 843 urb->actual_length = urb->length; 844 845 chan->xfer_len = urb->length - urb->actual_length; 846 chan->xfer_count = 0; 847 848 /* Set the split attributes if required */ 849 if (qh->do_split) 850 dwc2_hc_init_split(hsotg, chan, qtd, urb); 851 else 852 chan->do_split = 0; 853 854 /* Set the transfer attributes */ 855 bufptr = dwc2_hc_init_xfer(hsotg, chan, qtd, urb); 856 857 /* Non DWORD-aligned buffer case */ 858 if (bufptr) { 859 dev_vdbg(hsotg->dev, "Non-aligned buffer\n"); 860 if (dwc2_hc_setup_align_buf(hsotg, qh, chan, urb, bufptr)) { 861 dev_err(hsotg->dev, 862 "%s: Failed to allocate memory to handle non-dword aligned buffer\n", 863 __func__); 864 /* Add channel back to free list */ 865 chan->align_buf = 0; 866 chan->multi_count = 0; 867 list_add_tail(&chan->hc_list_entry, 868 &hsotg->free_hc_list); 869 qtd->in_process = 0; 870 qh->channel = NULL; 871 return -ENOMEM; 872 } 873 } else { 874 chan->align_buf = 0; 875 } 876 877 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 878 chan->ep_type == USB_ENDPOINT_XFER_ISOC) 879 /* 880 * This value may be modified when the transfer is started 881 * to reflect the actual transfer length 882 */ 883 chan->multi_count = dwc2_hb_mult(qh->maxp); 884 885 if (hsotg->core_params->dma_desc_enable > 0) { 886 chan->desc_list_usbdma = qh->desc_list_usbdma; 887 chan->desc_list_addr = qh->desc_list_dma; 888 chan->desc_list_sz = qh->desc_list_sz; 889 } 890 891 dwc2_hc_init(hsotg, chan); 892 chan->qh = qh; 893 894 return 0; 895 } 896 897 /** 898 * dwc2_hcd_select_transactions() - Selects transactions from the HCD transfer 899 * schedule and assigns them to available host channels. Called from the HCD 900 * interrupt handler functions. 901 * 902 * @hsotg: The HCD state structure 903 * 904 * Return: The types of new transactions that were assigned to host channels 905 */ 906 enum dwc2_transaction_type dwc2_hcd_select_transactions( 907 struct dwc2_hsotg *hsotg) 908 { 909 enum dwc2_transaction_type ret_val = DWC2_TRANSACTION_NONE; 910 struct list_head *qh_ptr; 911 struct dwc2_qh *qh; 912 int num_channels; 913 914 #ifdef DWC2_DEBUG_SOF 915 dev_vdbg(hsotg->dev, " Select Transactions\n"); 916 #endif 917 918 /* Process entries in the periodic ready list */ 919 qh_ptr = hsotg->periodic_sched_ready.next; 920 while (qh_ptr != &hsotg->periodic_sched_ready) { 921 if (list_empty(&hsotg->free_hc_list)) 922 break; 923 if (hsotg->core_params->uframe_sched > 0) { 924 if (hsotg->available_host_channels <= 1) 925 break; 926 hsotg->available_host_channels--; 927 } 928 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 929 if (dwc2_assign_and_init_hc(hsotg, qh)) 930 break; 931 932 /* 933 * Move the QH from the periodic ready schedule to the 934 * periodic assigned schedule 935 */ 936 qh_ptr = qh_ptr->next; 937 list_move(&qh->qh_list_entry, &hsotg->periodic_sched_assigned); 938 ret_val = DWC2_TRANSACTION_PERIODIC; 939 } 940 941 /* 942 * Process entries in the inactive portion of the non-periodic 943 * schedule. Some free host channels may not be used if they are 944 * reserved for periodic transfers. 945 */ 946 num_channels = hsotg->core_params->host_channels; 947 qh_ptr = hsotg->non_periodic_sched_inactive.next; 948 while (qh_ptr != &hsotg->non_periodic_sched_inactive) { 949 if (hsotg->core_params->uframe_sched <= 0 && 950 hsotg->non_periodic_channels >= num_channels - 951 hsotg->periodic_channels) 952 break; 953 if (list_empty(&hsotg->free_hc_list)) 954 break; 955 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 956 957 /* 958 * Check to see if this is a NAK'd retransmit, in which case 959 * ignore for retransmission. We hold off on bulk/control 960 * retransmissions to reduce NAK interrupt overhead for 961 * cheeky devices that just hold off using NAKs. 962 */ 963 if (qh->nak_frame != 0xffff && 964 dwc2_full_frame_num(qh->nak_frame) == 965 dwc2_full_frame_num(dwc2_hcd_get_frame_number(hsotg))) { 966 qh_ptr = qh_ptr->next; 967 continue; 968 } else { 969 qh->nak_frame = 0xffff; 970 } 971 972 if (hsotg->core_params->uframe_sched > 0) { 973 if (hsotg->available_host_channels < 1) 974 break; 975 hsotg->available_host_channels--; 976 } 977 978 if (dwc2_assign_and_init_hc(hsotg, qh)) 979 break; 980 981 /* 982 * Move the QH from the non-periodic inactive schedule to the 983 * non-periodic active schedule 984 */ 985 qh_ptr = qh_ptr->next; 986 list_move(&qh->qh_list_entry, 987 &hsotg->non_periodic_sched_active); 988 989 if (ret_val == DWC2_TRANSACTION_NONE) 990 ret_val = DWC2_TRANSACTION_NON_PERIODIC; 991 else 992 ret_val = DWC2_TRANSACTION_ALL; 993 994 if (hsotg->core_params->uframe_sched <= 0) 995 hsotg->non_periodic_channels++; 996 } 997 998 return ret_val; 999 } 1000 1001 /** 1002 * dwc2_queue_transaction() - Attempts to queue a single transaction request for 1003 * a host channel associated with either a periodic or non-periodic transfer 1004 * 1005 * @hsotg: The HCD state structure 1006 * @chan: Host channel descriptor associated with either a periodic or 1007 * non-periodic transfer 1008 * @fifo_dwords_avail: Number of DWORDs available in the periodic Tx FIFO 1009 * for periodic transfers or the non-periodic Tx FIFO 1010 * for non-periodic transfers 1011 * 1012 * Return: 1 if a request is queued and more requests may be needed to 1013 * complete the transfer, 0 if no more requests are required for this 1014 * transfer, -1 if there is insufficient space in the Tx FIFO 1015 * 1016 * This function assumes that there is space available in the appropriate 1017 * request queue. For an OUT transfer or SETUP transaction in Slave mode, 1018 * it checks whether space is available in the appropriate Tx FIFO. 1019 * 1020 * Must be called with interrupt disabled and spinlock held 1021 */ 1022 static int dwc2_queue_transaction(struct dwc2_hsotg *hsotg, 1023 struct dwc2_host_chan *chan, 1024 u16 fifo_dwords_avail) 1025 { 1026 int retval = 0; 1027 1028 if (hsotg->core_params->dma_enable > 0) { 1029 if (hsotg->core_params->dma_desc_enable > 0) { 1030 if (!chan->xfer_started || 1031 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 1032 dwc2_hcd_start_xfer_ddma(hsotg, chan->qh); 1033 chan->qh->ping_state = 0; 1034 } 1035 } else if (!chan->xfer_started) { 1036 dwc2_hc_start_transfer(hsotg, chan); 1037 chan->qh->ping_state = 0; 1038 } 1039 } else if (chan->halt_pending) { 1040 /* Don't queue a request if the channel has been halted */ 1041 } else if (chan->halt_on_queue) { 1042 dwc2_hc_halt(hsotg, chan, chan->halt_status); 1043 } else if (chan->do_ping) { 1044 if (!chan->xfer_started) 1045 dwc2_hc_start_transfer(hsotg, chan); 1046 } else if (!chan->ep_is_in || 1047 chan->data_pid_start == DWC2_HC_PID_SETUP) { 1048 if ((fifo_dwords_avail * 4) >= chan->max_packet) { 1049 if (!chan->xfer_started) { 1050 dwc2_hc_start_transfer(hsotg, chan); 1051 retval = 1; 1052 } else { 1053 retval = dwc2_hc_continue_transfer(hsotg, chan); 1054 } 1055 } else { 1056 retval = -1; 1057 } 1058 } else { 1059 if (!chan->xfer_started) { 1060 dwc2_hc_start_transfer(hsotg, chan); 1061 retval = 1; 1062 } else { 1063 retval = dwc2_hc_continue_transfer(hsotg, chan); 1064 } 1065 } 1066 1067 return retval; 1068 } 1069 1070 /* 1071 * Processes periodic channels for the next frame and queues transactions for 1072 * these channels to the DWC_otg controller. After queueing transactions, the 1073 * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions 1074 * to queue as Periodic Tx FIFO or request queue space becomes available. 1075 * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled. 1076 * 1077 * Must be called with interrupt disabled and spinlock held 1078 */ 1079 static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg) 1080 { 1081 struct list_head *qh_ptr; 1082 struct dwc2_qh *qh; 1083 u32 tx_status; 1084 u32 fspcavail; 1085 u32 gintmsk; 1086 int status; 1087 int no_queue_space = 0; 1088 int no_fifo_space = 0; 1089 u32 qspcavail; 1090 1091 if (dbg_perio()) 1092 dev_vdbg(hsotg->dev, "Queue periodic transactions\n"); 1093 1094 tx_status = DWC2_READ_4(hsotg, HPTXSTS); 1095 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1096 TXSTS_QSPCAVAIL_SHIFT; 1097 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1098 TXSTS_FSPCAVAIL_SHIFT; 1099 1100 if (dbg_perio()) { 1101 dev_vdbg(hsotg->dev, " P Tx Req Queue Space Avail (before queue): %d\n", 1102 qspcavail); 1103 dev_vdbg(hsotg->dev, " P Tx FIFO Space Avail (before queue): %d\n", 1104 fspcavail); 1105 } 1106 1107 qh_ptr = hsotg->periodic_sched_assigned.next; 1108 while (qh_ptr != &hsotg->periodic_sched_assigned) { 1109 tx_status = DWC2_READ_4(hsotg, HPTXSTS); 1110 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1111 TXSTS_QSPCAVAIL_SHIFT; 1112 if (qspcavail == 0) { 1113 no_queue_space = 1; 1114 break; 1115 } 1116 1117 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 1118 if (!qh->channel) { 1119 qh_ptr = qh_ptr->next; 1120 continue; 1121 } 1122 1123 /* Make sure EP's TT buffer is clean before queueing qtds */ 1124 if (qh->tt_buffer_dirty) { 1125 qh_ptr = qh_ptr->next; 1126 continue; 1127 } 1128 1129 /* 1130 * Set a flag if we're queuing high-bandwidth in slave mode. 1131 * The flag prevents any halts to get into the request queue in 1132 * the middle of multiple high-bandwidth packets getting queued. 1133 */ 1134 if (hsotg->core_params->dma_enable <= 0 && 1135 qh->channel->multi_count > 1) 1136 hsotg->queuing_high_bandwidth = 1; 1137 1138 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1139 TXSTS_FSPCAVAIL_SHIFT; 1140 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail); 1141 if (status < 0) { 1142 no_fifo_space = 1; 1143 break; 1144 } 1145 1146 /* 1147 * In Slave mode, stay on the current transfer until there is 1148 * nothing more to do or the high-bandwidth request count is 1149 * reached. In DMA mode, only need to queue one request. The 1150 * controller automatically handles multiple packets for 1151 * high-bandwidth transfers. 1152 */ 1153 if (hsotg->core_params->dma_enable > 0 || status == 0 || 1154 qh->channel->requests == qh->channel->multi_count) { 1155 qh_ptr = qh_ptr->next; 1156 /* 1157 * Move the QH from the periodic assigned schedule to 1158 * the periodic queued schedule 1159 */ 1160 list_move(&qh->qh_list_entry, 1161 &hsotg->periodic_sched_queued); 1162 1163 /* done queuing high bandwidth */ 1164 hsotg->queuing_high_bandwidth = 0; 1165 } 1166 } 1167 1168 if (hsotg->core_params->dma_enable <= 0) { 1169 tx_status = DWC2_READ_4(hsotg, HPTXSTS); 1170 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1171 TXSTS_QSPCAVAIL_SHIFT; 1172 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1173 TXSTS_FSPCAVAIL_SHIFT; 1174 if (dbg_perio()) { 1175 dev_vdbg(hsotg->dev, 1176 " P Tx Req Queue Space Avail (after queue): %d\n", 1177 qspcavail); 1178 dev_vdbg(hsotg->dev, 1179 " P Tx FIFO Space Avail (after queue): %d\n", 1180 fspcavail); 1181 } 1182 1183 if (!list_empty(&hsotg->periodic_sched_assigned) || 1184 no_queue_space || no_fifo_space) { 1185 /* 1186 * May need to queue more transactions as the request 1187 * queue or Tx FIFO empties. Enable the periodic Tx 1188 * FIFO empty interrupt. (Always use the half-empty 1189 * level to ensure that new requests are loaded as 1190 * soon as possible.) 1191 */ 1192 gintmsk = DWC2_READ_4(hsotg, GINTMSK); 1193 gintmsk |= GINTSTS_PTXFEMP; 1194 DWC2_WRITE_4(hsotg, GINTMSK, gintmsk); 1195 } else { 1196 /* 1197 * Disable the Tx FIFO empty interrupt since there are 1198 * no more transactions that need to be queued right 1199 * now. This function is called from interrupt 1200 * handlers to queue more transactions as transfer 1201 * states change. 1202 */ 1203 gintmsk = DWC2_READ_4(hsotg, GINTMSK); 1204 gintmsk &= ~GINTSTS_PTXFEMP; 1205 DWC2_WRITE_4(hsotg, GINTMSK, gintmsk); 1206 } 1207 } 1208 } 1209 1210 /* 1211 * Processes active non-periodic channels and queues transactions for these 1212 * channels to the DWC_otg controller. After queueing transactions, the NP Tx 1213 * FIFO Empty interrupt is enabled if there are more transactions to queue as 1214 * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx 1215 * FIFO Empty interrupt is disabled. 1216 * 1217 * Must be called with interrupt disabled and spinlock held 1218 */ 1219 static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg) 1220 { 1221 struct list_head *orig_qh_ptr; 1222 struct dwc2_qh *qh; 1223 u32 tx_status; 1224 u32 qspcavail; 1225 u32 fspcavail; 1226 u32 gintmsk; 1227 int status; 1228 int no_queue_space = 0; 1229 int no_fifo_space = 0; 1230 int more_to_do = 0; 1231 1232 dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n"); 1233 1234 tx_status = DWC2_READ_4(hsotg, GNPTXSTS); 1235 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1236 TXSTS_QSPCAVAIL_SHIFT; 1237 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1238 TXSTS_FSPCAVAIL_SHIFT; 1239 dev_vdbg(hsotg->dev, " NP Tx Req Queue Space Avail (before queue): %d\n", 1240 qspcavail); 1241 dev_vdbg(hsotg->dev, " NP Tx FIFO Space Avail (before queue): %d\n", 1242 fspcavail); 1243 1244 /* 1245 * Keep track of the starting point. Skip over the start-of-list 1246 * entry. 1247 */ 1248 if (hsotg->non_periodic_qh_ptr == &hsotg->non_periodic_sched_active) 1249 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next; 1250 orig_qh_ptr = hsotg->non_periodic_qh_ptr; 1251 1252 /* 1253 * Process once through the active list or until no more space is 1254 * available in the request queue or the Tx FIFO 1255 */ 1256 do { 1257 tx_status = DWC2_READ_4(hsotg, GNPTXSTS); 1258 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1259 TXSTS_QSPCAVAIL_SHIFT; 1260 if (hsotg->core_params->dma_enable <= 0 && qspcavail == 0) { 1261 no_queue_space = 1; 1262 break; 1263 } 1264 1265 qh = list_entry(hsotg->non_periodic_qh_ptr, struct dwc2_qh, 1266 qh_list_entry); 1267 if (!qh->channel) 1268 goto next; 1269 1270 /* Make sure EP's TT buffer is clean before queueing qtds */ 1271 if (qh->tt_buffer_dirty) 1272 goto next; 1273 1274 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1275 TXSTS_FSPCAVAIL_SHIFT; 1276 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail); 1277 1278 if (status > 0) { 1279 more_to_do = 1; 1280 } else if (status < 0) { 1281 no_fifo_space = 1; 1282 break; 1283 } 1284 next: 1285 /* Advance to next QH, skipping start-of-list entry */ 1286 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next; 1287 if (hsotg->non_periodic_qh_ptr == 1288 &hsotg->non_periodic_sched_active) 1289 hsotg->non_periodic_qh_ptr = 1290 hsotg->non_periodic_qh_ptr->next; 1291 } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr); 1292 1293 if (hsotg->core_params->dma_enable <= 0) { 1294 tx_status = DWC2_READ_4(hsotg, GNPTXSTS); 1295 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1296 TXSTS_QSPCAVAIL_SHIFT; 1297 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1298 TXSTS_FSPCAVAIL_SHIFT; 1299 dev_vdbg(hsotg->dev, 1300 " NP Tx Req Queue Space Avail (after queue): %d\n", 1301 qspcavail); 1302 dev_vdbg(hsotg->dev, 1303 " NP Tx FIFO Space Avail (after queue): %d\n", 1304 fspcavail); 1305 1306 if (more_to_do || no_queue_space || no_fifo_space) { 1307 /* 1308 * May need to queue more transactions as the request 1309 * queue or Tx FIFO empties. Enable the non-periodic 1310 * Tx FIFO empty interrupt. (Always use the half-empty 1311 * level to ensure that new requests are loaded as 1312 * soon as possible.) 1313 */ 1314 gintmsk = DWC2_READ_4(hsotg, GINTMSK); 1315 gintmsk |= GINTSTS_NPTXFEMP; 1316 DWC2_WRITE_4(hsotg, GINTMSK, gintmsk); 1317 } else { 1318 /* 1319 * Disable the Tx FIFO empty interrupt since there are 1320 * no more transactions that need to be queued right 1321 * now. This function is called from interrupt 1322 * handlers to queue more transactions as transfer 1323 * states change. 1324 */ 1325 gintmsk = DWC2_READ_4(hsotg, GINTMSK); 1326 gintmsk &= ~GINTSTS_NPTXFEMP; 1327 DWC2_WRITE_4(hsotg, GINTMSK, gintmsk); 1328 } 1329 } 1330 } 1331 1332 /** 1333 * dwc2_hcd_queue_transactions() - Processes the currently active host channels 1334 * and queues transactions for these channels to the DWC_otg controller. Called 1335 * from the HCD interrupt handler functions. 1336 * 1337 * @hsotg: The HCD state structure 1338 * @tr_type: The type(s) of transactions to queue (non-periodic, periodic, 1339 * or both) 1340 * 1341 * Must be called with interrupt disabled and spinlock held 1342 */ 1343 void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg, 1344 enum dwc2_transaction_type tr_type) 1345 { 1346 #ifdef DWC2_DEBUG_SOF 1347 dev_vdbg(hsotg->dev, "Queue Transactions\n"); 1348 #endif 1349 /* Process host channels associated with periodic transfers */ 1350 if ((tr_type == DWC2_TRANSACTION_PERIODIC || 1351 tr_type == DWC2_TRANSACTION_ALL) && 1352 !list_empty(&hsotg->periodic_sched_assigned)) 1353 dwc2_process_periodic_channels(hsotg); 1354 1355 /* Process host channels associated with non-periodic transfers */ 1356 if (tr_type == DWC2_TRANSACTION_NON_PERIODIC || 1357 tr_type == DWC2_TRANSACTION_ALL) { 1358 if (!list_empty(&hsotg->non_periodic_sched_active)) { 1359 dwc2_process_non_periodic_channels(hsotg); 1360 } else { 1361 /* 1362 * Ensure NP Tx FIFO empty interrupt is disabled when 1363 * there are no non-periodic transfers to process 1364 */ 1365 u32 gintmsk = DWC2_READ_4(hsotg, GINTMSK); 1366 1367 gintmsk &= ~GINTSTS_NPTXFEMP; 1368 DWC2_WRITE_4(hsotg, GINTMSK, gintmsk); 1369 } 1370 } 1371 } 1372 1373 static void dwc2_conn_id_status_change(struct work_struct *work) 1374 { 1375 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 1376 wf_otg); 1377 u32 count = 0; 1378 u32 gotgctl; 1379 unsigned long flags; 1380 1381 dev_dbg(hsotg->dev, "%s()\n", __func__); 1382 1383 gotgctl = DWC2_READ_4(hsotg, GOTGCTL); 1384 dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl); 1385 dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n", 1386 !!(gotgctl & GOTGCTL_CONID_B)); 1387 1388 /* B-Device connector (Device Mode) */ 1389 if (gotgctl & GOTGCTL_CONID_B) { 1390 /* Wait for switch to device mode */ 1391 dev_dbg(hsotg->dev, "connId B\n"); 1392 while (!dwc2_is_device_mode(hsotg)) { 1393 dev_info(hsotg->dev, 1394 "Waiting for Peripheral Mode, Mode=%s\n", 1395 dwc2_is_host_mode(hsotg) ? "Host" : 1396 "Peripheral"); 1397 usleep_range(20000, 40000); 1398 if (++count > 250) 1399 break; 1400 } 1401 if (count > 250) 1402 dev_err(hsotg->dev, 1403 "Connection id status change timed out\n"); 1404 hsotg->op_state = OTG_STATE_B_PERIPHERAL; 1405 dwc2_core_init(hsotg, false); 1406 dwc2_enable_global_interrupts(hsotg); 1407 spin_lock_irqsave(&hsotg->lock, flags); 1408 dwc2_hsotg_core_init_disconnected(hsotg, false); 1409 spin_unlock_irqrestore(&hsotg->lock, flags); 1410 dwc2_hsotg_core_connect(hsotg); 1411 } else { 1412 /* A-Device connector (Host Mode) */ 1413 dev_dbg(hsotg->dev, "connId A\n"); 1414 while (!dwc2_is_host_mode(hsotg)) { 1415 dev_info(hsotg->dev, "Waiting for Host Mode, Mode=%s\n", 1416 dwc2_is_host_mode(hsotg) ? 1417 "Host" : "Peripheral"); 1418 usleep_range(20000, 40000); 1419 if (++count > 250) 1420 break; 1421 } 1422 if (count > 250) 1423 dev_err(hsotg->dev, 1424 "Connection id status change timed out\n"); 1425 hsotg->op_state = OTG_STATE_A_HOST; 1426 1427 /* Initialize the Core for Host mode */ 1428 dwc2_core_init(hsotg, false); 1429 dwc2_enable_global_interrupts(hsotg); 1430 dwc2_hcd_start(hsotg); 1431 } 1432 } 1433 1434 void dwc2_wakeup_detected(void *data) 1435 { 1436 struct dwc2_hsotg *hsotg = (struct dwc2_hsotg *)data; 1437 u32 hprt0; 1438 1439 dev_dbg(hsotg->dev, "%s()\n", __func__); 1440 1441 /* 1442 * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms 1443 * so that OPT tests pass with all PHYs.) 1444 */ 1445 hprt0 = dwc2_read_hprt0(hsotg); 1446 dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0); 1447 hprt0 &= ~HPRT0_RES; 1448 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 1449 dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n", 1450 DWC2_READ_4(hsotg, HPRT0)); 1451 1452 dwc2_hcd_rem_wakeup(hsotg); 1453 hsotg->bus_suspended = 0; 1454 1455 /* Change to L0 state */ 1456 hsotg->lx_state = DWC2_L0; 1457 } 1458 1459 /* Must NOT be called with interrupt disabled or spinlock held */ 1460 static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex) 1461 { 1462 unsigned long flags; 1463 u32 hprt0; 1464 u32 pcgctl; 1465 u32 gotgctl; 1466 1467 dev_dbg(hsotg->dev, "%s()\n", __func__); 1468 1469 spin_lock_irqsave(&hsotg->lock, flags); 1470 1471 if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) { 1472 gotgctl = DWC2_READ_4(hsotg, GOTGCTL); 1473 gotgctl |= GOTGCTL_HSTSETHNPEN; 1474 DWC2_WRITE_4(hsotg, GOTGCTL, gotgctl); 1475 hsotg->op_state = OTG_STATE_A_SUSPEND; 1476 } 1477 1478 hprt0 = dwc2_read_hprt0(hsotg); 1479 hprt0 |= HPRT0_SUSP; 1480 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 1481 1482 hsotg->bus_suspended = 1; 1483 1484 /* 1485 * If hibernation is supported, Phy clock will be suspended 1486 * after registers are backuped. 1487 */ 1488 if (!hsotg->core_params->hibernation) { 1489 /* Suspend the Phy Clock */ 1490 pcgctl = DWC2_READ_4(hsotg, PCGCTL); 1491 pcgctl |= PCGCTL_STOPPCLK; 1492 DWC2_WRITE_4(hsotg, PCGCTL, pcgctl); 1493 udelay(10); 1494 } 1495 1496 /* For HNP the bus must be suspended for at least 200ms */ 1497 if (dwc2_host_is_b_hnp_enabled(hsotg)) { 1498 pcgctl = DWC2_READ_4(hsotg, PCGCTL); 1499 pcgctl &= ~PCGCTL_STOPPCLK; 1500 DWC2_WRITE_4(hsotg, PCGCTL, pcgctl); 1501 1502 spin_unlock_irqrestore(&hsotg->lock, flags); 1503 1504 usleep_range(200000, 250000); 1505 } else { 1506 spin_unlock_irqrestore(&hsotg->lock, flags); 1507 } 1508 } 1509 1510 /* Must NOT be called with interrupt disabled or spinlock held */ 1511 static void dwc2_port_resume(struct dwc2_hsotg *hsotg) 1512 { 1513 unsigned long flags; 1514 u32 hprt0; 1515 u32 pcgctl; 1516 1517 spin_lock_irqsave(&hsotg->lock, flags); 1518 1519 /* 1520 * If hibernation is supported, Phy clock is already resumed 1521 * after registers restore. 1522 */ 1523 if (!hsotg->core_params->hibernation) { 1524 pcgctl = DWC2_READ_4(hsotg, PCGCTL); 1525 pcgctl &= ~PCGCTL_STOPPCLK; 1526 DWC2_WRITE_4(hsotg, PCGCTL, pcgctl); 1527 spin_unlock_irqrestore(&hsotg->lock, flags); 1528 usleep_range(20000, 40000); 1529 spin_lock_irqsave(&hsotg->lock, flags); 1530 } 1531 1532 hprt0 = dwc2_read_hprt0(hsotg); 1533 hprt0 |= HPRT0_RES; 1534 hprt0 &= ~HPRT0_SUSP; 1535 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 1536 spin_unlock_irqrestore(&hsotg->lock, flags); 1537 1538 msleep(USB_RESUME_TIMEOUT); 1539 1540 spin_lock_irqsave(&hsotg->lock, flags); 1541 hprt0 = dwc2_read_hprt0(hsotg); 1542 hprt0 &= ~(HPRT0_RES | HPRT0_SUSP); 1543 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 1544 hsotg->bus_suspended = 0; 1545 spin_unlock_irqrestore(&hsotg->lock, flags); 1546 } 1547 1548 /* Handles hub class-specific requests */ 1549 int 1550 dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq, 1551 u16 wvalue, u16 windex, char *buf, u16 wlength) 1552 { 1553 usb_hub_descriptor_t *hub_desc; 1554 usb_port_status_t ps; 1555 int retval = 0; 1556 u32 hprt0; 1557 u32 port_status; 1558 u32 speed; 1559 u32 pcgctl; 1560 1561 switch (typereq) { 1562 case ClearHubFeature: 1563 dev_dbg(hsotg->dev, "ClearHubFeature %1xh\n", wvalue); 1564 1565 switch (wvalue) { 1566 case C_HUB_LOCAL_POWER: 1567 case C_HUB_OVER_CURRENT: 1568 /* Nothing required here */ 1569 break; 1570 1571 default: 1572 retval = -EINVAL; 1573 dev_err(hsotg->dev, 1574 "ClearHubFeature request %1xh unknown\n", 1575 wvalue); 1576 } 1577 break; 1578 1579 case ClearPortFeature: 1580 // if (wvalue != USB_PORT_FEAT_L1) 1581 if (!windex || windex > 1) 1582 goto error; 1583 switch (wvalue) { 1584 case USB_PORT_FEAT_ENABLE: 1585 dev_dbg(hsotg->dev, 1586 "ClearPortFeature USB_PORT_FEAT_ENABLE\n"); 1587 hprt0 = dwc2_read_hprt0(hsotg); 1588 hprt0 |= HPRT0_ENA; 1589 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 1590 break; 1591 1592 case USB_PORT_FEAT_SUSPEND: 1593 dev_dbg(hsotg->dev, 1594 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n"); 1595 if (hsotg->bus_suspended) 1596 dwc2_port_resume(hsotg); 1597 break; 1598 1599 case USB_PORT_FEAT_POWER: 1600 dev_dbg(hsotg->dev, 1601 "ClearPortFeature USB_PORT_FEAT_POWER\n"); 1602 hprt0 = dwc2_read_hprt0(hsotg); 1603 hprt0 &= ~HPRT0_PWR; 1604 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 1605 break; 1606 1607 case USB_PORT_FEAT_INDICATOR: 1608 dev_dbg(hsotg->dev, 1609 "ClearPortFeature USB_PORT_FEAT_INDICATOR\n"); 1610 /* Port indicator not supported */ 1611 break; 1612 1613 case USB_PORT_FEAT_C_CONNECTION: 1614 /* 1615 * Clears driver's internal Connect Status Change flag 1616 */ 1617 dev_dbg(hsotg->dev, 1618 "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n"); 1619 hsotg->flags.b.port_connect_status_change = 0; 1620 break; 1621 1622 case USB_PORT_FEAT_C_RESET: 1623 /* Clears driver's internal Port Reset Change flag */ 1624 dev_dbg(hsotg->dev, 1625 "ClearPortFeature USB_PORT_FEAT_C_RESET\n"); 1626 hsotg->flags.b.port_reset_change = 0; 1627 break; 1628 1629 case USB_PORT_FEAT_C_ENABLE: 1630 /* 1631 * Clears the driver's internal Port Enable/Disable 1632 * Change flag 1633 */ 1634 dev_dbg(hsotg->dev, 1635 "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n"); 1636 hsotg->flags.b.port_enable_change = 0; 1637 break; 1638 1639 case USB_PORT_FEAT_C_SUSPEND: 1640 /* 1641 * Clears the driver's internal Port Suspend Change 1642 * flag, which is set when resume signaling on the host 1643 * port is complete 1644 */ 1645 dev_dbg(hsotg->dev, 1646 "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n"); 1647 hsotg->flags.b.port_suspend_change = 0; 1648 break; 1649 1650 case USB_PORT_FEAT_C_PORT_L1: 1651 dev_dbg(hsotg->dev, 1652 "ClearPortFeature USB_PORT_FEAT_C_PORT_L1\n"); 1653 hsotg->flags.b.port_l1_change = 0; 1654 break; 1655 1656 case USB_PORT_FEAT_C_OVER_CURRENT: 1657 dev_dbg(hsotg->dev, 1658 "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n"); 1659 hsotg->flags.b.port_over_current_change = 0; 1660 break; 1661 1662 default: 1663 retval = -EINVAL; 1664 dev_err(hsotg->dev, 1665 "ClearPortFeature request %1xh unknown or unsupported\n", 1666 wvalue); 1667 } 1668 break; 1669 1670 case GetHubDescriptor: 1671 dev_dbg(hsotg->dev, "GetHubDescriptor\n"); 1672 hub_desc = (usb_hub_descriptor_t *)buf; 1673 hub_desc->bDescLength = 9; 1674 hub_desc->bDescriptorType = USB_DT_HUB; 1675 hub_desc->bNbrPorts = 1; 1676 USETW(hub_desc->wHubCharacteristics, HUB_CHAR_COMMON_LPSM | 1677 HUB_CHAR_INDV_PORT_OCPM); 1678 hub_desc->bPwrOn2PwrGood = 1; 1679 hub_desc->bHubContrCurrent = 0; 1680 hub_desc->DeviceRemovable[0] = 0; 1681 hub_desc->DeviceRemovable[1] = 0xff; 1682 break; 1683 1684 case GetHubStatus: 1685 dev_dbg(hsotg->dev, "GetHubStatus\n"); 1686 memset(buf, 0, 4); 1687 break; 1688 1689 case GetPortStatus: 1690 dev_vdbg(hsotg->dev, 1691 "GetPortStatus wIndex=0x%04x flags=0x%08x\n", windex, 1692 hsotg->flags.d32); 1693 if (!windex || windex > 1) 1694 goto error; 1695 1696 port_status = 0; 1697 if (hsotg->flags.b.port_connect_status_change) 1698 port_status |= USB_PORT_STAT_C_CONNECTION; 1699 if (hsotg->flags.b.port_enable_change) 1700 port_status |= USB_PORT_STAT_C_ENABLE; 1701 if (hsotg->flags.b.port_suspend_change) 1702 port_status |= USB_PORT_STAT_C_SUSPEND; 1703 if (hsotg->flags.b.port_l1_change) 1704 port_status |= USB_PORT_STAT_C_L1; 1705 if (hsotg->flags.b.port_reset_change) 1706 port_status |= USB_PORT_STAT_C_RESET; 1707 if (hsotg->flags.b.port_over_current_change) { 1708 dev_warn(hsotg->dev, "Overcurrent change detected\n"); 1709 port_status |= USB_PORT_STAT_C_OVERCURRENT; 1710 } 1711 USETW(ps.wPortChange, port_status); 1712 1713 dev_vdbg(hsotg->dev, "wPortChange=%04x\n", port_status); 1714 if (!hsotg->flags.b.port_connect_status) { 1715 /* 1716 * The port is disconnected, which means the core is 1717 * either in device mode or it soon will be. Just 1718 * return 0's for the remainder of the port status 1719 * since the port register can't be read if the core 1720 * is in device mode. 1721 */ 1722 USETW(ps.wPortStatus, 0); 1723 memcpy(buf, &ps, sizeof(ps)); 1724 break; 1725 } 1726 1727 port_status = 0; 1728 hprt0 = DWC2_READ_4(hsotg, HPRT0); 1729 dev_vdbg(hsotg->dev, " HPRT0: 0x%08x\n", hprt0); 1730 1731 if (hprt0 & HPRT0_CONNSTS) 1732 port_status |= USB_PORT_STAT_CONNECTION; 1733 if (hprt0 & HPRT0_ENA) 1734 port_status |= USB_PORT_STAT_ENABLE; 1735 if (hprt0 & HPRT0_SUSP) 1736 port_status |= USB_PORT_STAT_SUSPEND; 1737 if (hprt0 & HPRT0_OVRCURRACT) 1738 port_status |= USB_PORT_STAT_OVERCURRENT; 1739 if (hprt0 & HPRT0_RST) 1740 port_status |= USB_PORT_STAT_RESET; 1741 if (hprt0 & HPRT0_PWR) 1742 port_status |= USB_PORT_STAT_POWER; 1743 1744 speed = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; 1745 if (speed == HPRT0_SPD_HIGH_SPEED) 1746 port_status |= USB_PORT_STAT_HIGH_SPEED; 1747 else if (speed == HPRT0_SPD_LOW_SPEED) 1748 port_status |= USB_PORT_STAT_LOW_SPEED; 1749 1750 if (hprt0 & HPRT0_TSTCTL_MASK) 1751 port_status |= USB_PORT_STAT_TEST; 1752 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */ 1753 USETW(ps.wPortStatus, port_status); 1754 1755 if (hsotg->core_params->dma_desc_fs_enable) { 1756 /* 1757 * Enable descriptor DMA only if a full speed 1758 * device is connected. 1759 */ 1760 if (hsotg->new_connection && 1761 ((port_status & 1762 (USB_PORT_STAT_CONNECTION | 1763 USB_PORT_STAT_HIGH_SPEED | 1764 USB_PORT_STAT_LOW_SPEED)) == 1765 USB_PORT_STAT_CONNECTION)) { 1766 u32 hcfg; 1767 1768 dev_info(hsotg->dev, "Enabling descriptor DMA mode\n"); 1769 hsotg->core_params->dma_desc_enable = 1; 1770 hcfg = DWC2_READ_4(hsotg, HCFG); 1771 hcfg |= HCFG_DESCDMA; 1772 DWC2_WRITE_4(hsotg, HCFG, hcfg); 1773 hsotg->new_connection = false; 1774 } 1775 } 1776 dev_vdbg(hsotg->dev, "wPortStatus=%04x\n", port_status); 1777 memcpy(buf, &ps, sizeof(ps)); 1778 break; 1779 1780 case SetHubFeature: 1781 dev_dbg(hsotg->dev, "SetHubFeature\n"); 1782 /* No HUB features supported */ 1783 break; 1784 1785 case SetPortFeature: 1786 dev_dbg(hsotg->dev, "SetPortFeature\n"); 1787 if (wvalue != USB_PORT_FEAT_TEST && (!windex || windex > 1)) 1788 goto error; 1789 1790 if (!hsotg->flags.b.port_connect_status) { 1791 /* 1792 * The port is disconnected, which means the core is 1793 * either in device mode or it soon will be. Just 1794 * return without doing anything since the port 1795 * register can't be written if the core is in device 1796 * mode. 1797 */ 1798 break; 1799 } 1800 1801 switch (wvalue) { 1802 case USB_PORT_FEAT_SUSPEND: 1803 dev_dbg(hsotg->dev, 1804 "SetPortFeature - USB_PORT_FEAT_SUSPEND\n"); 1805 if (windex != hsotg->otg_port) 1806 goto error; 1807 dwc2_port_suspend(hsotg, windex); 1808 break; 1809 1810 case USB_PORT_FEAT_POWER: 1811 dev_dbg(hsotg->dev, 1812 "SetPortFeature - USB_PORT_FEAT_POWER\n"); 1813 hprt0 = dwc2_read_hprt0(hsotg); 1814 hprt0 |= HPRT0_PWR; 1815 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 1816 break; 1817 1818 case USB_PORT_FEAT_RESET: 1819 hprt0 = dwc2_read_hprt0(hsotg); 1820 dev_dbg(hsotg->dev, 1821 "SetPortFeature - USB_PORT_FEAT_RESET\n"); 1822 pcgctl = DWC2_READ_4(hsotg, PCGCTL); 1823 pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK); 1824 DWC2_WRITE_4(hsotg, PCGCTL, pcgctl); 1825 /* ??? Original driver does this */ 1826 DWC2_WRITE_4(hsotg, PCGCTL, 0); 1827 1828 hprt0 = dwc2_read_hprt0(hsotg); 1829 /* Clear suspend bit if resetting from suspend state */ 1830 hprt0 &= ~HPRT0_SUSP; 1831 1832 /* 1833 * When B-Host the Port reset bit is set in the Start 1834 * HCD Callback function, so that the reset is started 1835 * within 1ms of the HNP success interrupt 1836 */ 1837 if (!dwc2_hcd_is_b_host(hsotg)) { 1838 hprt0 |= HPRT0_PWR | HPRT0_RST; 1839 dev_dbg(hsotg->dev, 1840 "In host mode, hprt0=%08x\n", hprt0); 1841 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 1842 } 1843 1844 /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */ 1845 usleep_range(50000, 70000); 1846 hprt0 &= ~HPRT0_RST; 1847 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 1848 hsotg->lx_state = DWC2_L0; /* Now back to On state */ 1849 break; 1850 1851 case USB_PORT_FEAT_INDICATOR: 1852 dev_dbg(hsotg->dev, 1853 "SetPortFeature - USB_PORT_FEAT_INDICATOR\n"); 1854 /* Not supported */ 1855 break; 1856 1857 case USB_PORT_FEAT_TEST: 1858 hprt0 = dwc2_read_hprt0(hsotg); 1859 dev_dbg(hsotg->dev, 1860 "SetPortFeature - USB_PORT_FEAT_TEST\n"); 1861 hprt0 &= ~HPRT0_TSTCTL_MASK; 1862 hprt0 |= (windex >> 8) << HPRT0_TSTCTL_SHIFT; 1863 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 1864 break; 1865 1866 default: 1867 retval = -EINVAL; 1868 dev_err(hsotg->dev, 1869 "SetPortFeature %1xh unknown or unsupported\n", 1870 wvalue); 1871 break; 1872 } 1873 break; 1874 1875 default: 1876 error: 1877 retval = -EINVAL; 1878 dev_dbg(hsotg->dev, 1879 "Unknown hub control request: %1xh wIndex: %1xh wValue: %1xh\n", 1880 typereq, windex, wvalue); 1881 break; 1882 } 1883 1884 return retval; 1885 } 1886 1887 int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg) 1888 { 1889 u32 hfnum = DWC2_READ_4(hsotg, HFNUM); 1890 1891 #ifdef DWC2_DEBUG_SOF 1892 dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n", 1893 (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT); 1894 #endif 1895 return (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT; 1896 } 1897 1898 int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg) 1899 { 1900 return hsotg->op_state == OTG_STATE_B_HOST; 1901 } 1902 1903 struct dwc2_hcd_urb * 1904 dwc2_hcd_urb_alloc(struct dwc2_hsotg *hsotg, int iso_desc_count, 1905 gfp_t mem_flags) 1906 { 1907 struct dwc2_hcd_urb *urb; 1908 u32 size = sizeof(*urb) + iso_desc_count * 1909 sizeof(struct dwc2_hcd_iso_packet_desc); 1910 int kmem_flag; 1911 1912 if ((mem_flags & __GFP_WAIT) == __GFP_WAIT) 1913 kmem_flag = KM_SLEEP; 1914 else 1915 kmem_flag = KM_NOSLEEP; 1916 1917 urb = kmem_zalloc(size, kmem_flag); 1918 if (urb) 1919 urb->packet_count = iso_desc_count; 1920 return urb; 1921 } 1922 1923 void 1924 dwc2_hcd_urb_free(struct dwc2_hsotg *hsotg, struct dwc2_hcd_urb *urb, 1925 int iso_desc_count) 1926 { 1927 1928 u32 size = sizeof(*urb) + iso_desc_count * 1929 sizeof(struct dwc2_hcd_iso_packet_desc); 1930 1931 kmem_free(urb, size); 1932 } 1933 1934 void 1935 dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *hsotg, struct dwc2_hcd_urb *urb, 1936 u8 dev_addr, u8 ep_num, u8 ep_type, u8 ep_dir, 1937 u16 mps) 1938 { 1939 if (dbg_perio() || 1940 ep_type == USB_ENDPOINT_XFER_BULK || 1941 ep_type == USB_ENDPOINT_XFER_CONTROL) 1942 dev_dbg(hsotg->dev, "urb=%p, xfer=%p\n", urb, urb->priv); 1943 urb->pipe_info.dev_addr = dev_addr; 1944 urb->pipe_info.ep_num = ep_num; 1945 urb->pipe_info.pipe_type = ep_type; 1946 urb->pipe_info.pipe_dir = ep_dir; 1947 urb->pipe_info.mps = mps; 1948 } 1949 1950 /* 1951 * NOTE: This function will be removed once the peripheral controller code 1952 * is integrated and the driver is stable 1953 */ 1954 void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg) 1955 { 1956 #ifdef DWC2_DEBUG 1957 struct dwc2_host_chan *chan; 1958 struct dwc2_hcd_urb *urb; 1959 struct dwc2_qtd *qtd; 1960 int num_channels; 1961 u32 np_tx_status; 1962 u32 p_tx_status; 1963 int i; 1964 1965 num_channels = hsotg->core_params->host_channels; 1966 dev_dbg(hsotg->dev, "\n"); 1967 dev_dbg(hsotg->dev, 1968 "************************************************************\n"); 1969 dev_dbg(hsotg->dev, "HCD State:\n"); 1970 dev_dbg(hsotg->dev, " Num channels: %d\n", num_channels); 1971 1972 for (i = 0; i < num_channels; i++) { 1973 chan = hsotg->hc_ptr_array[i]; 1974 dev_dbg(hsotg->dev, " Channel %d:\n", i); 1975 dev_dbg(hsotg->dev, 1976 " dev_addr: %d, ep_num: %d, ep_is_in: %d\n", 1977 chan->dev_addr, chan->ep_num, chan->ep_is_in); 1978 dev_dbg(hsotg->dev, " speed: %d\n", chan->speed); 1979 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type); 1980 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet); 1981 dev_dbg(hsotg->dev, " data_pid_start: %d\n", 1982 chan->data_pid_start); 1983 dev_dbg(hsotg->dev, " multi_count: %d\n", chan->multi_count); 1984 dev_dbg(hsotg->dev, " xfer_started: %d\n", 1985 chan->xfer_started); 1986 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf); 1987 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n", 1988 (unsigned long)chan->xfer_dma); 1989 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len); 1990 dev_dbg(hsotg->dev, " xfer_count: %d\n", chan->xfer_count); 1991 dev_dbg(hsotg->dev, " halt_on_queue: %d\n", 1992 chan->halt_on_queue); 1993 dev_dbg(hsotg->dev, " halt_pending: %d\n", 1994 chan->halt_pending); 1995 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status); 1996 dev_dbg(hsotg->dev, " do_split: %d\n", chan->do_split); 1997 dev_dbg(hsotg->dev, " complete_split: %d\n", 1998 chan->complete_split); 1999 dev_dbg(hsotg->dev, " hub_addr: %d\n", chan->hub_addr); 2000 dev_dbg(hsotg->dev, " hub_port: %d\n", chan->hub_port); 2001 dev_dbg(hsotg->dev, " xact_pos: %d\n", chan->xact_pos); 2002 dev_dbg(hsotg->dev, " requests: %d\n", chan->requests); 2003 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh); 2004 2005 if (chan->xfer_started) { 2006 dev_dbg(hsotg->dev, " hfnum: 0x%08x\n", 2007 DWC2_READ_4(hsotg, HFNUM)); 2008 dev_dbg(hsotg->dev, " hcchar: 0x%08x\n", 2009 DWC2_READ_4(hsotg, HCCHAR(i))); 2010 dev_dbg(hsotg->dev, " hctsiz: 0x%08x\n", 2011 DWC2_READ_4(hsotg, HCTSIZ(i))); 2012 dev_dbg(hsotg->dev, " hcint: 0x%08x\n", 2013 DWC2_READ_4(hsotg, HCINT(i))); 2014 dev_dbg(hsotg->dev, " hcintmsk: 0x%08x\n", 2015 DWC2_READ_4(hsotg, HCINTMSK(i))); 2016 } 2017 2018 if (!(chan->xfer_started && chan->qh)) 2019 continue; 2020 2021 list_for_each_entry(qtd, &chan->qh->qtd_list, qtd_list_entry) { 2022 if (!qtd->in_process) 2023 break; 2024 urb = qtd->urb; 2025 dev_dbg(hsotg->dev, " URB Info:\n"); 2026 dev_dbg(hsotg->dev, " qtd: %p, urb: %p\n", 2027 qtd, urb); 2028 if (urb) { 2029 dev_dbg(hsotg->dev, 2030 " Dev: %d, EP: %d %s\n", 2031 dwc2_hcd_get_dev_addr(&urb->pipe_info), 2032 dwc2_hcd_get_ep_num(&urb->pipe_info), 2033 dwc2_hcd_is_pipe_in(&urb->pipe_info) ? 2034 "IN" : "OUT"); 2035 dev_dbg(hsotg->dev, 2036 " Max packet size: %d\n", 2037 dwc2_hcd_get_mps(&urb->pipe_info)); 2038 dev_dbg(hsotg->dev, 2039 " transfer_buffer: %p\n", 2040 urb->buf); 2041 dev_dbg(hsotg->dev, 2042 " transfer_dma: %08lx\n", 2043 (unsigned long)urb->dma); 2044 dev_dbg(hsotg->dev, 2045 " transfer_buffer_length: %d\n", 2046 urb->length); 2047 dev_dbg(hsotg->dev, " actual_length: %d\n", 2048 urb->actual_length); 2049 } 2050 } 2051 } 2052 2053 dev_dbg(hsotg->dev, " non_periodic_channels: %d\n", 2054 hsotg->non_periodic_channels); 2055 dev_dbg(hsotg->dev, " periodic_channels: %d\n", 2056 hsotg->periodic_channels); 2057 dev_dbg(hsotg->dev, " periodic_usecs: %d\n", hsotg->periodic_usecs); 2058 np_tx_status = DWC2_READ_4(hsotg, GNPTXSTS); 2059 dev_dbg(hsotg->dev, " NP Tx Req Queue Space Avail: %d\n", 2060 (np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT); 2061 dev_dbg(hsotg->dev, " NP Tx FIFO Space Avail: %d\n", 2062 (np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT); 2063 p_tx_status = DWC2_READ_4(hsotg, HPTXSTS); 2064 dev_dbg(hsotg->dev, " P Tx Req Queue Space Avail: %d\n", 2065 (p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT); 2066 dev_dbg(hsotg->dev, " P Tx FIFO Space Avail: %d\n", 2067 (p_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT); 2068 dwc2_hcd_dump_frrem(hsotg); 2069 2070 dwc2_dump_global_registers(hsotg); 2071 dwc2_dump_host_registers(hsotg); 2072 dev_dbg(hsotg->dev, 2073 "************************************************************\n"); 2074 dev_dbg(hsotg->dev, "\n"); 2075 #endif 2076 } 2077 2078 /* 2079 * NOTE: This function will be removed once the peripheral controller code 2080 * is integrated and the driver is stable 2081 */ 2082 void dwc2_hcd_dump_frrem(struct dwc2_hsotg *hsotg) 2083 { 2084 #ifdef DWC2_DUMP_FRREM 2085 dev_dbg(hsotg->dev, "Frame remaining at SOF:\n"); 2086 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2087 hsotg->frrem_samples, hsotg->frrem_accum, 2088 hsotg->frrem_samples > 0 ? 2089 hsotg->frrem_accum / hsotg->frrem_samples : 0); 2090 dev_dbg(hsotg->dev, "\n"); 2091 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 7):\n"); 2092 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2093 hsotg->hfnum_7_samples, 2094 hsotg->hfnum_7_frrem_accum, 2095 hsotg->hfnum_7_samples > 0 ? 2096 hsotg->hfnum_7_frrem_accum / hsotg->hfnum_7_samples : 0); 2097 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 0):\n"); 2098 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2099 hsotg->hfnum_0_samples, 2100 hsotg->hfnum_0_frrem_accum, 2101 hsotg->hfnum_0_samples > 0 ? 2102 hsotg->hfnum_0_frrem_accum / hsotg->hfnum_0_samples : 0); 2103 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 1-6):\n"); 2104 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2105 hsotg->hfnum_other_samples, 2106 hsotg->hfnum_other_frrem_accum, 2107 hsotg->hfnum_other_samples > 0 ? 2108 hsotg->hfnum_other_frrem_accum / hsotg->hfnum_other_samples : 2109 0); 2110 dev_dbg(hsotg->dev, "\n"); 2111 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 7):\n"); 2112 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2113 hsotg->hfnum_7_samples_a, hsotg->hfnum_7_frrem_accum_a, 2114 hsotg->hfnum_7_samples_a > 0 ? 2115 hsotg->hfnum_7_frrem_accum_a / hsotg->hfnum_7_samples_a : 0); 2116 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 0):\n"); 2117 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2118 hsotg->hfnum_0_samples_a, hsotg->hfnum_0_frrem_accum_a, 2119 hsotg->hfnum_0_samples_a > 0 ? 2120 hsotg->hfnum_0_frrem_accum_a / hsotg->hfnum_0_samples_a : 0); 2121 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 1-6):\n"); 2122 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2123 hsotg->hfnum_other_samples_a, hsotg->hfnum_other_frrem_accum_a, 2124 hsotg->hfnum_other_samples_a > 0 ? 2125 hsotg->hfnum_other_frrem_accum_a / hsotg->hfnum_other_samples_a 2126 : 0); 2127 dev_dbg(hsotg->dev, "\n"); 2128 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 7):\n"); 2129 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2130 hsotg->hfnum_7_samples_b, hsotg->hfnum_7_frrem_accum_b, 2131 hsotg->hfnum_7_samples_b > 0 ? 2132 hsotg->hfnum_7_frrem_accum_b / hsotg->hfnum_7_samples_b : 0); 2133 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 0):\n"); 2134 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2135 hsotg->hfnum_0_samples_b, hsotg->hfnum_0_frrem_accum_b, 2136 (hsotg->hfnum_0_samples_b > 0) ? 2137 hsotg->hfnum_0_frrem_accum_b / hsotg->hfnum_0_samples_b : 0); 2138 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 1-6):\n"); 2139 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2140 hsotg->hfnum_other_samples_b, hsotg->hfnum_other_frrem_accum_b, 2141 (hsotg->hfnum_other_samples_b > 0) ? 2142 hsotg->hfnum_other_frrem_accum_b / hsotg->hfnum_other_samples_b 2143 : 0); 2144 #endif 2145 } 2146 2147 struct wrapper_priv_data { 2148 struct dwc2_hsotg *hsotg; 2149 }; 2150 2151 2152 void dwc2_host_start(struct dwc2_hsotg *hsotg) 2153 { 2154 // struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 2155 2156 // hcd->self.is_b_host = dwc2_hcd_is_b_host(hsotg); 2157 _dwc2_hcd_start(hsotg); 2158 } 2159 2160 void dwc2_host_disconnect(struct dwc2_hsotg *hsotg) 2161 { 2162 // struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 2163 2164 // hcd->self.is_b_host = 0; 2165 } 2166 2167 /* 2168 * Work queue function for starting the HCD when A-Cable is connected 2169 */ 2170 static void dwc2_hcd_start_func(struct work_struct *work) 2171 { 2172 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 2173 start_work.work); 2174 2175 dev_dbg(hsotg->dev, "%s() %p\n", __func__, hsotg); 2176 dwc2_host_start(hsotg); 2177 } 2178 2179 /* 2180 * Reset work queue function 2181 */ 2182 static void dwc2_hcd_reset_func(struct work_struct *work) 2183 { 2184 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 2185 reset_work.work); 2186 unsigned long flags; 2187 u32 hprt0; 2188 2189 dev_dbg(hsotg->dev, "USB RESET function called\n"); 2190 2191 spin_lock_irqsave(&hsotg->lock, flags); 2192 2193 hprt0 = dwc2_read_hprt0(hsotg); 2194 hprt0 &= ~HPRT0_RST; 2195 DWC2_WRITE_4(hsotg, HPRT0, hprt0); 2196 hsotg->flags.b.port_reset_change = 1; 2197 2198 dwc2_root_intr(hsotg->hsotg_sc); 2199 2200 spin_unlock_irqrestore(&hsotg->lock, flags); 2201 } 2202 2203 /* 2204 * ========================================================================= 2205 * Linux HC Driver Functions 2206 * ========================================================================= 2207 */ 2208 2209 /* 2210 * Initializes the DWC_otg controller and its root hub and prepares it for host 2211 * mode operation. Activates the root port. Returns 0 on success and a negative 2212 * error code on failure. 2213 */ 2214 2215 /* 2216 * Frees secondary storage associated with the dwc2_hsotg structure contained 2217 * in the struct usb_hcd field 2218 */ 2219 static void dwc2_hcd_free(struct dwc2_hsotg *hsotg) 2220 { 2221 u32 ahbcfg; 2222 u32 dctl; 2223 int i; 2224 2225 dev_dbg(hsotg->dev, "DWC OTG HCD FREE\n"); 2226 2227 /* Free memory for QH/QTD lists */ 2228 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_inactive); 2229 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_waiting); 2230 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_active); 2231 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_inactive); 2232 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_ready); 2233 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_assigned); 2234 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_queued); 2235 2236 /* Free memory for the host channels */ 2237 for (i = 0; i < MAX_EPS_CHANNELS; i++) { 2238 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i]; 2239 2240 if (chan != NULL) { 2241 dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n", 2242 i, chan); 2243 hsotg->hc_ptr_array[i] = NULL; 2244 kmem_free(chan, sizeof(*chan)); 2245 } 2246 } 2247 2248 if (hsotg->core_params->dma_enable > 0) { 2249 if (hsotg->status_buf) { 2250 usb_freemem(&hsotg->status_buf_usbdma); 2251 hsotg->status_buf = NULL; 2252 } 2253 } else { 2254 kmem_free(hsotg->status_buf,DWC2_HCD_STATUS_BUF_SIZE); 2255 hsotg->status_buf = NULL; 2256 } 2257 2258 ahbcfg = DWC2_READ_4(hsotg, GAHBCFG); 2259 2260 /* Disable all interrupts */ 2261 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN; 2262 DWC2_WRITE_4(hsotg, GAHBCFG, ahbcfg); 2263 DWC2_WRITE_4(hsotg, GINTMSK, 0); 2264 2265 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) { 2266 dctl = DWC2_READ_4(hsotg, DCTL); 2267 dctl |= DCTL_SFTDISCON; 2268 DWC2_WRITE_4(hsotg, DCTL, dctl); 2269 } 2270 2271 if (hsotg->wq_otg) { 2272 if (!cancel_work_sync(&hsotg->wf_otg)) 2273 flush_workqueue(hsotg->wq_otg); 2274 destroy_workqueue(hsotg->wq_otg); 2275 } 2276 2277 kmem_free(hsotg->core_params, sizeof(*hsotg->core_params)); 2278 hsotg->core_params = NULL; 2279 callout_destroy(&hsotg->wkp_timer); 2280 } 2281 2282 static void dwc2_hcd_release(struct dwc2_hsotg *hsotg) 2283 { 2284 /* Turn off all host-specific interrupts */ 2285 dwc2_disable_host_interrupts(hsotg); 2286 2287 dwc2_hcd_free(hsotg); 2288 } 2289 2290 /* 2291 * Initializes the HCD. This function allocates memory for and initializes the 2292 * static parts of the usb_hcd and dwc2_hsotg structures. It also registers the 2293 * USB bus with the core and calls the hc_driver->start() function. It returns 2294 * a negative error on failure. 2295 */ 2296 int dwc2_hcd_init(struct dwc2_hsotg *hsotg) 2297 { 2298 struct dwc2_host_chan *channel; 2299 int i, num_channels; 2300 int retval; 2301 2302 if (usb_disabled()) 2303 return -ENODEV; 2304 2305 dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n"); 2306 2307 retval = -ENOMEM; 2308 2309 dev_dbg(hsotg->dev, "hcfg=%08x\n", DWC2_READ_4(hsotg, HCFG)); 2310 2311 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 2312 hsotg->frame_num_array = kmem_zalloc(sizeof(*hsotg->frame_num_array) * 2313 FRAME_NUM_ARRAY_SIZE, KM_SLEEP); 2314 if (!hsotg->frame_num_array) 2315 goto error1; 2316 hsotg->last_frame_num_array = kmem_zalloc( 2317 sizeof(*hsotg->last_frame_num_array) * 2318 FRAME_NUM_ARRAY_SIZE, KM_SLEEP); 2319 if (!hsotg->last_frame_num_array) 2320 goto error1; 2321 hsotg->last_frame_num = HFNUM_MAX_FRNUM; 2322 #endif 2323 2324 spin_lock_init(&hsotg->lock); 2325 2326 /* 2327 * Disable the global interrupt until all the interrupt handlers are 2328 * installed 2329 */ 2330 dwc2_disable_global_interrupts(hsotg); 2331 2332 /* Initialize the DWC_otg core, and select the Phy type */ 2333 retval = dwc2_core_init(hsotg, true); 2334 if (retval) 2335 goto error2; 2336 2337 /* Create new workqueue and init work */ 2338 retval = -ENOMEM; 2339 hsotg->wq_otg = create_singlethread_workqueue("dwc2"); 2340 if (!hsotg->wq_otg) { 2341 dev_err(hsotg->dev, "Failed to create workqueue\n"); 2342 goto error2; 2343 } 2344 INIT_WORK(&hsotg->wf_otg, dwc2_conn_id_status_change); 2345 2346 callout_init(&hsotg->wkp_timer, CALLOUT_MPSAFE); 2347 callout_setfunc(&hsotg->wkp_timer, dwc2_wakeup_detected, hsotg); 2348 2349 /* Initialize the non-periodic schedule */ 2350 INIT_LIST_HEAD(&hsotg->non_periodic_sched_inactive); 2351 INIT_LIST_HEAD(&hsotg->non_periodic_sched_waiting); 2352 INIT_LIST_HEAD(&hsotg->non_periodic_sched_active); 2353 2354 /* Initialize the periodic schedule */ 2355 INIT_LIST_HEAD(&hsotg->periodic_sched_inactive); 2356 INIT_LIST_HEAD(&hsotg->periodic_sched_ready); 2357 INIT_LIST_HEAD(&hsotg->periodic_sched_assigned); 2358 INIT_LIST_HEAD(&hsotg->periodic_sched_queued); 2359 2360 /* 2361 * Create a host channel descriptor for each host channel implemented 2362 * in the controller. Initialize the channel descriptor array. 2363 */ 2364 INIT_LIST_HEAD(&hsotg->free_hc_list); 2365 num_channels = hsotg->core_params->host_channels; 2366 memset(&hsotg->hc_ptr_array[0], 0, sizeof(hsotg->hc_ptr_array)); 2367 2368 for (i = 0; i < num_channels; i++) { 2369 channel = kmem_zalloc(sizeof(*channel), KM_SLEEP); 2370 if (channel == NULL) 2371 goto error3; 2372 channel->hc_num = i; 2373 hsotg->hc_ptr_array[i] = channel; 2374 } 2375 2376 if (hsotg->core_params->uframe_sched > 0) 2377 dwc2_hcd_init_usecs(hsotg); 2378 2379 /* Initialize hsotg start work */ 2380 INIT_DELAYED_WORK(&hsotg->start_work, dwc2_hcd_start_func); 2381 2382 /* Initialize port reset work */ 2383 INIT_DELAYED_WORK(&hsotg->reset_work, dwc2_hcd_reset_func); 2384 2385 /* 2386 * Allocate space for storing data on status transactions. Normally no 2387 * data is sent, but this space acts as a bit bucket. This must be 2388 * done after usb_add_hcd since that function allocates the DMA buffer 2389 * pool. 2390 */ 2391 hsotg->status_buf = NULL; 2392 if (hsotg->core_params->dma_enable > 0) { 2393 int error = usb_allocmem(hsotg->hsotg_sc->sc_bus.ub_dmatag, 2394 DWC2_HCD_STATUS_BUF_SIZE, 0, USBMALLOC_COHERENT, 2395 &hsotg->status_buf_usbdma); 2396 if (!error) { 2397 hsotg->status_buf = KERNADDR(&hsotg->status_buf_usbdma, 0); 2398 hsotg->status_buf_dma = DMAADDR(&hsotg->status_buf_usbdma, 0); 2399 } 2400 } else 2401 hsotg->status_buf = kmem_zalloc(DWC2_HCD_STATUS_BUF_SIZE, 2402 KM_SLEEP); 2403 2404 /* retval is already -ENOMEM */ 2405 if (!hsotg->status_buf) 2406 goto error3; 2407 2408 hsotg->otg_port = 1; 2409 hsotg->frame_list = NULL; 2410 hsotg->frame_list_dma = 0; 2411 hsotg->periodic_qh_count = 0; 2412 2413 /* Initiate lx_state to L3 disconnected state */ 2414 hsotg->lx_state = DWC2_L3; 2415 2416 _dwc2_hcd_start(hsotg); 2417 2418 dwc2_hcd_dump_state(hsotg); 2419 2420 dwc2_enable_global_interrupts(hsotg); 2421 2422 return 0; 2423 2424 error3: 2425 dwc2_hcd_release(hsotg); 2426 error2: 2427 if (hsotg->core_params != NULL) 2428 kmem_free(hsotg->core_params, sizeof(*hsotg->core_params)); 2429 2430 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 2431 if (hsotg->last_frame_num_array != NULL) 2432 kmem_free(hsotg->last_frame_num_array, 2433 sizeof(*hsotg->last_frame_num_array) * FRAME_NUM_ARRAY_SIZE); 2434 if (hsotg->frame_num_array != NULL) 2435 kmem_free(hsotg->frame_num_array, 2436 sizeof(*hsotg->frame_num_array) * FRAME_NUM_ARRAY_SIZE); 2437 #endif 2438 2439 dev_err(hsotg->dev, "%s() FAILED, returning %d\n", __func__, retval); 2440 return retval; 2441 } 2442 2443 /* 2444 * Removes the HCD. 2445 * Frees memory and resources associated with the HCD and deregisters the bus. 2446 */ 2447 void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) 2448 { 2449 struct usb_hcd *hcd; 2450 2451 dev_dbg(hsotg->dev, "DWC OTG HCD REMOVE\n"); 2452 2453 hcd = dwc2_hsotg_to_hcd(hsotg); 2454 dev_dbg(hsotg->dev, "hsotg->hcd = %p\n", hcd); 2455 2456 if (!hcd) { 2457 dev_dbg(hsotg->dev, "%s: dwc2_hsotg_to_hcd(hsotg) NULL!\n", 2458 __func__); 2459 return; 2460 } 2461 hsotg->priv = NULL; 2462 2463 dwc2_hcd_release(hsotg); 2464 2465 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 2466 kmem_free(hsotg->last_frame_num_array, sizeof(*hsotg->last_frame_num_array) * FRAME_NUM_ARRAY_SIZE); 2467 kmem_free(hsotg->frame_num_array, sizeof(*hsotg->frame_num_array) * FRAME_NUM_ARRAY_SIZE); 2468 #endif 2469 } 2470
Indexes created Sun Sep 21 15:09:59 GMT 2025