1 /* $NetBSD: dwc_gmac_reg.h,v 1.24 2024/10/19 05:09:03 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2013, 2014 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas of 3am Software Foundry and Martin Husemann. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #define AWIN_GMAC_MAC_CONF 0x0000 33 #define AWIN_GMAC_MAC_FFILT 0x0004 34 #define AWIN_GMAC_MAC_HTHIGH 0x0008 35 #define AWIN_GMAC_MAC_HTLOW 0x000c 36 #define AWIN_GMAC_MAC_MIIADDR 0x0010 37 #define AWIN_GMAC_MAC_MIIDATA 0x0014 38 #define AWIN_GMAC_MAC_FLOWCTRL 0x0018 39 #define AWIN_GMAC_MAC_VLANTAG 0x001c 40 #define AWIN_GMAC_MAC_VERSION 0x0020 /* not always implemented? */ 41 #define AWIN_GMAC_MAC_VERSION_USERVER_MASK __BITS(15, 8) 42 #define AWIN_GMAC_MAC_VERSION_SNPSVER_MASK __BITS( 7, 0) 43 #define AWIN_GMAC_MAC_INTR 0x0038 44 #define AWIN_GMAC_MAC_INTMASK 0x003c 45 #define AWIN_GMAC_MAC_ADDR0HI 0x0040 46 #define AWIN_GMAC_MAC_ADDR0LO 0x0044 47 #define AWIN_GMAC_MII_STATUS 0x00D8 48 49 #define AWIN_GMAC_MAC_CONF_DISABLEJABBER __BIT(22) /* jabber disable */ 50 #define AWIN_GMAC_MAC_CONF_FRAMEBURST __BIT(21) /* allow TX frameburst when 51 in half duplex mode */ 52 #define AWIN_GMAC_MAC_CONF_MIISEL __BIT(15) /* select MII phy */ 53 #define AWIN_GMAC_MAC_CONF_FES100 __BIT(14) /* 100 mbit mode */ 54 #define AWIN_GMAC_MAC_CONF_DISABLERXOWN __BIT(13) /* do not receive our own 55 TX frames in half duplex 56 mode */ 57 #define AWIN_GMAC_MAC_CONF_FULLDPLX __BIT(11) /* select full duplex */ 58 #define AWIN_GMAC_MAC_CONF_ACS __BIT(7) /* auto pad/CRC stripping */ 59 #define AWIN_GMAC_MAC_CONF_TXENABLE __BIT(3) /* enable TX dma engine */ 60 #define AWIN_GMAC_MAC_CONF_RXENABLE __BIT(2) /* enable RX dma engine */ 61 62 #define AWIN_GMAC_MAC_FFILT_RA __BIT(31) /* receive all mode */ 63 #define AWIN_GMAC_MAC_FFILT_HPF __BIT(10) /* hash or perfect filter */ 64 #define AWIN_GMAC_MAC_FFILT_SAF __BIT(9) /* source address filter */ 65 #define AWIN_GMAC_MAC_FFILT_SAIF __BIT(8) /* inverse filtering */ 66 #define AWIN_GMAC_MAC_FFILT_DBF __BIT(5) /* disable broadcast frames */ 67 #define AWIN_GMAC_MAC_FFILT_PM __BIT(4) /* promiscuous multicast */ 68 #define AWIN_GMAC_MAC_FFILT_DAIF __BIT(3) /* DA inverse filtering */ 69 #define AWIN_GMAC_MAC_FFILT_HMC __BIT(2) /* multicast hash compare */ 70 #define AWIN_GMAC_MAC_FFILT_HUC __BIT(1) /* unicast hash compare */ 71 #define AWIN_GMAC_MAC_FFILT_PR __BIT(0) /* promiscuous mode */ 72 73 #define AWIN_GMAC_MAC_INT_LPI __BIT(10) 74 #define AWIN_GMAC_MAC_INT_TSI __BIT(9) 75 #define AWIN_GMAC_MAC_INT_ANEG __BIT(2) 76 #define AWIN_GMAC_MAC_INT_LINKCHG __BIT(1) 77 #define AWIN_GMAC_MAC_INT_RGSMII __BIT(0) 78 79 #define AWIN_GMAC_MAC_FLOWCTRL_PAUSE __BITS(31,16) 80 #define AWIN_GMAC_MAC_FLOWCTRL_RFE __BIT(2) 81 #define AWIN_GMAC_MAC_FLOWCTRL_TFE __BIT(1) 82 #define AWIN_GMAC_MAC_FLOWCTRL_BUSY __BIT(0) 83 84 #define GMAC_MMC_CTRL 0x0100 /* MMC control */ 85 #define GMAC_MMC_RX_INTR 0x0104 /* MMC RX interrupt */ 86 #define GMAC_MMC_TX_INTR 0x0108 /* MMC TX interrupt */ 87 #define GMAC_MMC_RX_INT_MSK 0x010c /* MMC RX interrupt mask */ 88 #define GMAC_MMC_TX_INT_MSK 0x0110 /* MMC TX interrupt mask */ 89 #define GMAC_MMC_TXOCTETCNT_GB 0x0114 /* TX octet good+bad */ 90 #define GMAC_MMC_TXFRMCNT_GB 0x0118 /* TX frame good+bad */ 91 #define GMAC_MMC_TXUNDFLWERR 0x0148 /* TX underflow */ 92 #define GMAC_MMC_TXCARERR 0x0160 /* TX carrier error */ 93 #define GMAC_MMC_TXOCTETCNT_G 0x0164 /* TX octet good */ 94 #define GMAC_MMC_TXFRMCNT_G 0x0168 /* TX frame good */ 95 #define GMAC_MMC_RXFRMCNT_GB 0x0180 /* RX frame good+bad */ 96 #define GMAC_MMC_RXOCTETCNT_GB 0x0184 /* RX octet good+bad */ 97 #define GMAC_MMC_RXOCTETCNT_G 0x0188 /* RX octet good */ 98 #define GMAC_MMC_RXMCFRMCNT_G 0x0190 /* RX mcast frame good */ 99 #define GMAC_MMC_RXCRCERR 0x0194 /* RX CRC error */ 100 #define GMAC_MMC_RXLENERR 0x01c8 /* RX length error */ 101 #define GMAC_MMC_RXFIFOOVRFLW 0x01d4 /* RX FIFO overflow */ 102 #define GMAC_MMC_IPC_INT_MSK 0x0200 /* RX csum offload intr mask */ 103 #define GMAC_MMC_IPC_INTR 0x0208 /* RX csum offload interrupt */ 104 #define GMAC_MMC_RXIPV4GFRM 0x0210 /* RX IPv4 good frame */ 105 #define GMAC_MMC_RXIPV4HDERRFRM 0x0214 /* RX IPv4 header error */ 106 #define GMAC_MMC_RXIPV6GFRM 0x0224 /* RX IPv6 good frame */ 107 #define GMAC_MMC_RXIPV6HDERRFRM 0x0228 /* RX IPv6 header error */ 108 #define GMAC_MMC_RXUDPERRFRM 0x0234 /* RX UDP csum error frame */ 109 #define GMAC_MMC_RXTCPERRFRM 0x023c /* RX TCP csum error frame */ 110 #define GMAC_MMC_RXICMPERRFRM 0x0244 /* RX ICMP csum error frame */ 111 #define GMAC_MMC_RXIPV4HDERROCT 0x0254 /* RX IPv4 header error octets */ 112 #define GMAC_MMC_RXIPV6HDERROCT 0x0268 /* RX IPv6 header error octets */ 113 #define GMAC_MMC_RXUDPERROCT 0x0274 /* RX UDP error octets */ 114 #define GMAC_MMC_RXTCPERROCT 0x027c /* RX TCP error octets */ 115 #define GMAC_MMC_RXICMPERROCT 0x0280 /* RX ICMP error octets */ 116 117 #define GMAC_MMC_CTRL_FHP __BIT(5) /* Full-Half preset */ 118 #define GMAC_MMC_CTRL_CP __BIT(4) /* Counters preset */ 119 #define GMAC_MMC_CTRL_MCF __BIT(3) /* MMC counter freeze */ 120 #define GMAC_MMC_CTRL_ROR __BIT(2) /* reset on read */ 121 #define GMAC_MMC_CTRL_CSR __BIT(1) /* Counter stop rollover */ 122 #define GMAC_MMC_CTRL_CR __BIT(0) /* Counters reset */ 123 124 #define AWIN_GMAC_DMA_BUSMODE 0x1000 125 #define AWIN_GMAC_DMA_TXPOLL 0x1004 126 #define AWIN_GMAC_DMA_RXPOLL 0x1008 127 #define AWIN_GMAC_DMA_RX_ADDR 0x100c 128 #define AWIN_GMAC_DMA_TX_ADDR 0x1010 129 #define AWIN_GMAC_DMA_STATUS 0x1014 130 #define AWIN_GMAC_DMA_OPMODE 0x1018 131 #define AWIN_GMAC_DMA_INTENABLE 0x101c 132 #define AWIN_GMAC_DMA_CUR_TX_DESC 0x1048 133 #define AWIN_GMAC_DMA_CUR_RX_DESC 0x104c 134 #define AWIN_GMAC_DMA_CUR_TX_BUFADDR 0x1050 135 #define AWIN_GMAC_DMA_CUR_RX_BUFADDR 0x1054 136 #define AWIN_GMAC_DMA_HWFEATURES 0x1058 /* not always implemented? */ 137 138 #define GMAC_MII_PHY_MASK __BITS(15,11) 139 #define GMAC_MII_REG_MASK __BITS(10,6) 140 141 #define GMAC_MII_BUSY __BIT(0) 142 #define GMAC_MII_WRITE __BIT(1) 143 #define GMAC_MII_CLK_60_100M_DIV42 0x0 144 #define GMAC_MII_CLK_100_150M_DIV62 0x1 145 #define GMAC_MII_CLK_25_35M_DIV16 0x2 146 #define GMAC_MII_CLK_35_60M_DIV26 0x3 147 #define GMAC_MII_CLK_150_250M_DIV102 0x4 148 #define GMAC_MII_CLK_250_300M_DIV124 0x5 149 #define GMAC_MII_CLK_DIV4 0x8 150 #define GMAC_MII_CLK_DIV6 0x9 151 #define GMAC_MII_CLK_DIV8 0xa 152 #define GMAC_MII_CLK_DIV10 0xb 153 #define GMAC_MII_CLK_DIV12 0xc 154 #define GMAC_MII_CLK_DIV14 0xd 155 #define GMAC_MII_CLK_DIV16 0xe 156 #define GMAC_MII_CLK_DIV18 0xf 157 #define GMAC_MII_CLKMASK __BITS(5,2) 158 159 #define GMAC_BUSMODE_4PBL __BIT(24) 160 #define GMAC_BUSMODE_RPBL __BITS(22,17) 161 #define GMAC_BUSMODE_FIXEDBURST __BIT(16) 162 #define GMAC_BUSMODE_PRIORXTX __BITS(15,14) 163 #define GMAC_BUSMODE_PRIORXTX_41 3 164 #define GMAC_BUSMODE_PRIORXTX_31 2 165 #define GMAC_BUSMODE_PRIORXTX_21 1 166 #define GMAC_BUSMODE_PRIORXTX_11 0 167 #define GMAC_BUSMODE_PBL __BITS(13,8) /* possible DMA 168 burst len */ 169 #define GMAC_BUSMODE_RESET __BIT(0) 170 171 #define AWIN_GMAC_MRCOIS __BIT(7) /* MMC RX csum offload intr */ 172 #define AWIN_GMAC_MTIS __BIT(6) /* MMC TX interrupt */ 173 #define AWIN_GMAC_MRIS __BIT(3) /* MMC RX interrupt */ 174 #define AWIN_GMAC_MIS __BIT(4) /* MMC interrupt */ 175 #define AWIN_GMAC_PIS __BIT(3) /* PMT interrupt */ 176 #define AWIN_GMAC_MII_IRQ __BIT(0) /* RGMII interrupt */ 177 178 179 #define GMAC_DMA_OP_DISABLECSDROP __BIT(26) /* disable dropping of 180 frames with TCP/IP 181 checksum errors */ 182 #define GMAC_DMA_OP_RXSTOREFORWARD __BIT(25) /* start RX when a 183 full frame is available */ 184 #define GMAC_DMA_OP_DISABLERXFLUSH __BIT(24) /* Do not drop frames 185 when out of RX descr. */ 186 #define GMAC_DMA_OP_TXSTOREFORWARD __BIT(21) /* start TX when a 187 full frame is available */ 188 #define GMAC_DMA_OP_FLUSHTX __BIT(20) /* flush TX fifo */ 189 #define GMAC_DMA_OP_TTC __BITS(16,14) /* TX thresh control */ 190 #define GMAC_DMA_OP_TXSTART __BIT(13) /* start TX DMA engine */ 191 #define GMAC_DMA_OP_RTC __BITS(4,3) /* RX thres control */ 192 #define GMAC_DMA_OP_RXSTART __BIT(1) /* start RX DMA engine */ 193 194 #define GMAC_DMA_INT_MMC __BIT(27) /* MMC interrupt */ 195 #define GMAC_DMA_INT_NIE __BIT(16) /* Normal/Summary */ 196 #define GMAC_DMA_INT_AIE __BIT(15) /* Abnormal/Summary */ 197 #define GMAC_DMA_INT_ERE __BIT(14) /* Early receive */ 198 #define GMAC_DMA_INT_FBE __BIT(13) /* Fatal bus error */ 199 #define GMAC_DMA_INT_ETE __BIT(10) /* Early transmit */ 200 #define GMAC_DMA_INT_RWE __BIT(9) /* Receive watchdog */ 201 #define GMAC_DMA_INT_RSE __BIT(8) /* Receive stopped */ 202 #define GMAC_DMA_INT_RUE __BIT(7) /* Receive buffer unavail. */ 203 #define GMAC_DMA_INT_RIE __BIT(6) /* Receive interrupt */ 204 #define GMAC_DMA_INT_UNE __BIT(5) /* Tx underflow */ 205 #define GMAC_DMA_INT_OVE __BIT(4) /* Receive overflow */ 206 #define GMAC_DMA_INT_TJE __BIT(3) /* Transmit jabber */ 207 #define GMAC_DMA_INT_TUE __BIT(2) /* Transmit buffer unavail. */ 208 #define GMAC_DMA_INT_TSE __BIT(1) /* Transmit stopped */ 209 #define GMAC_DMA_INT_TIE __BIT(0) /* Transmit interrupt */ 210 211 #define GMAC_DMA_INT_MASK __BITS(0,16) /* all possible intr bits */ 212 213 #define GMAC_DMA_FEAT_ENHANCED_DESC __BIT(24) 214 #define GMAC_DMA_FEAT_RMON __BIT(11) /* MMC */ 215 216 struct dwc_gmac_dev_dmadesc { 217 uint32_t ddesc_status0; /* Status / TDES0 */ 218 /* both: */ 219 #define DDESC_STATUS_OWNEDBYDEV __BIT(31) 220 221 /* for RX descriptors */ 222 #define DDESC_STATUS_DAFILTERFAIL __BIT(30) 223 #define DDESC_STATUS_FRMLENMSK __BITS(29,16) 224 #define DDESC_STATUS_RXERROR __BIT(15) 225 #define DDESC_STATUS_RXTRUNCATED __BIT(14) 226 #define DDESC_STATUS_SAFILTERFAIL __BIT(13) 227 #define DDESC_STATUS_RXIPC_GIANTFRAME __BIT(12) 228 #define DDESC_STATUS_RXDAMAGED __BIT(11) 229 #define DDESC_STATUS_RXVLANTAG __BIT(10) 230 #define DDESC_STATUS_RXFIRST __BIT(9) 231 #define DDESC_STATUS_RXLAST __BIT(8) 232 #define DDESC_STATUS_RXIPC_GIANT __BIT(7) 233 #define DDESC_STATUS_RXCOLLISION __BIT(6) 234 #define DDESC_STATUS_RXFRAMEETHER __BIT(5) 235 #define DDESC_STATUS_RXWATCHDOG __BIT(4) 236 #define DDESC_STATUS_RXMIIERROR __BIT(3) 237 #define DDESC_STATUS_RXDRIBBLING __BIT(2) 238 #define DDESC_STATUS_RXCRC __BIT(1) 239 240 uint32_t ddesc_cntl1; /* Control / TDES1 */ 241 242 /* for TX descriptors */ 243 #define DDESC_CNTL_TXINT __BIT(31) 244 #define DDESC_CNTL_TXLAST __BIT(30) 245 #define DDESC_CNTL_TXFIRST __BIT(29) 246 #define DDESC_CNTL_TXCHECKINSCTRL __BITS(27,28) 247 248 #define DDESC_TXCHECK_DISABLED 0 249 #define DDESC_TXCHECK_IP 1 250 #define DDESC_TXCHECK_IP_NO_PSE 2 251 #define DDESC_TXCHECK_FULL 3 252 253 #define DDESC_CNTL_TXCRCDIS __BIT(26) 254 #define DDESC_CNTL_TXRINGEND __BIT(25) 255 #define DDESC_CNTL_TXCHAIN __BIT(24) 256 #define DDESC_CNTL_TXDISPAD __BIT(23) 257 258 /* for RX descriptors */ 259 #define DDESC_CNTL_RXINTDIS __BIT(31) 260 #define DDESC_CNTL_RXRINGEND __BIT(25) 261 #define DDESC_CNTL_RXCHAIN __BIT(24) 262 263 /* both */ 264 #define DDESC_CNTL_SIZE1MASK __BITS(10,0) 265 #define DDESC_CNTL_SIZE1SHIFT 0 266 #define DDESC_CNTL_SIZE2MASK __BITS(21,11) 267 #define DDESC_CNTL_SIZE2SHIFT 11 268 269 uint32_t ddesc_data; /* pointer to buffer data */ 270 uint32_t ddesc_next; /* link to next descriptor */ 271 }; 272 273 /* Common to enhanced descriptors */ 274 275 #define DDESC_DES0_OWN __BIT(31) 276 277 #define DDESC_DES1_SIZE2MASK __BITS(28,16) 278 #define DDESC_DES1_SIZE1MASK __BITS(12,0) 279 280 /* For enhanced TX descriptors */ 281 282 #define DDESC_TDES0_IC __BIT(30) 283 #define DDESC_TDES0_LS __BIT(29) 284 #define DDESC_TDES0_FS __BIT(28) 285 #define DDESC_TDES0_TCH __BIT(20) 286 287 /* For enhanced RX descriptors */ 288 289 #define DDESC_RDES0_FL __BITS(29,16) 290 #define DDESC_RDES0_ES __BIT(15) 291 #define DDESC_RDES0_LE __BIT(12) 292 293 #define DDESC_RDES1_RCH __BIT(14) 294
Indexes created Sun Sep 21 20:09:37 GMT 2025