1 /* $NetBSD: dwlpx.c,v 1.43 2021/08/07 16:18:41 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1997 by Matthew Jacob 5 * NASA AMES Research Center. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice immediately at the beginning of the file, without modification, 13 * this list of conditions, and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 24 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 34 35 __KERNEL_RCSID(0, "$NetBSD: dwlpx.c,v 1.43 2021/08/07 16:18:41 thorpej Exp $"); 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 #include <sys/device.h> 41 #include <sys/cpu.h> 42 43 #include <machine/autoconf.h> 44 45 #include <dev/pci/pcireg.h> 46 #include <dev/pci/pcivar.h> 47 48 #include <alpha/tlsb/tlsbreg.h> 49 #include <alpha/tlsb/kftxxvar.h> 50 #include <alpha/tlsb/kftxxreg.h> 51 #include <alpha/pci/dwlpxreg.h> 52 #include <alpha/pci/dwlpxvar.h> 53 54 #define KV(_addr) ((void *)ALPHA_PHYS_TO_K0SEG((_addr))) 55 #define DWLPX_SYSBASE(sc) \ 56 ((((unsigned long)((sc)->dwlpx_node - 4)) << 36) | \ 57 (((unsigned long) (sc)->dwlpx_hosenum) << 34) | \ 58 (1LL << 39)) 59 #define DWLPX_SYSBASE1(node, hosenum) \ 60 ((((unsigned long)(node - 4)) << 36) | \ 61 (((unsigned long) hosenum) << 34) | \ 62 (1LL << 39)) 63 64 65 static int dwlpxmatch(device_t, cfdata_t, void *); 66 static void dwlpxattach(device_t, device_t, void *); 67 68 CFATTACH_DECL_NEW(dwlpx, sizeof(struct dwlpx_softc), 69 dwlpxmatch, dwlpxattach, NULL, NULL); 70 71 extern struct cfdriver dwlpx_cd; 72 73 void dwlpx_errintr(void *, u_long vec); 74 75 static int 76 dwlpxmatch(device_t parent, cfdata_t cf, void *aux) 77 { 78 struct kft_dev_attach_args *ka = aux; 79 unsigned long ls; 80 uint32_t ctl; 81 82 if (strcmp(ka->ka_name, dwlpx_cd.cd_name) != 0) 83 return (0); 84 85 ls = DWLPX_SYSBASE1(ka->ka_node, ka->ka_hosenum); 86 87 /* 88 * Probe the first HPC to make sure this really is a dwlpx and 89 * nothing else. 90 */ 91 if (badaddr(KV(PCIA_CTL(1) + ls), sizeof (ctl)) != 0) { 92 /* 93 * If we are here something went wrong. One reason 94 * could be that this is a dwlma and not a dwlpx. 95 * 96 * We can not clear potential illegal CSR errors here 97 * since it is unknown hardware. 98 */ 99 return (0); 100 } 101 102 return (1); 103 } 104 105 static void 106 dwlpxattach(device_t parent, device_t self, void *aux) 107 { 108 struct dwlpx_softc *sc = device_private(self); 109 struct dwlpx_config *ccp = &sc->dwlpx_cc; 110 struct kft_dev_attach_args *ka = aux; 111 struct pcibus_attach_args pba; 112 uint32_t pcia_present; 113 114 sc->dwlpx_dev = self; 115 sc->dwlpx_node = ka->ka_node; 116 sc->dwlpx_dtype = ka->ka_dtype; 117 sc->dwlpx_hosenum = ka->ka_hosenum; 118 119 dwlpx_init(sc); 120 dwlpx_dma_init(ccp); 121 122 pcia_present = REGVAL(PCIA_PRESENT + ccp->cc_sysbase); 123 aprint_normal(": PCIA rev. %d, STD I/O %spresent, %dK S/G entries\n", 124 (pcia_present >> PCIA_PRESENT_REVSHIFT) & PCIA_PRESENT_REVMASK, 125 (pcia_present & PCIA_PRESENT_STDIO) == 0 ? "not " : "", 126 sc->dwlpx_sgmapsz == DWLPX_SG128K ? 128 : 32); 127 128 #if 0 129 { 130 int hpc, slot, slotval; 131 const char *str; 132 for (hpc = 0; hpc < sc->dwlpx_nhpc; hpc++) { 133 for (slot = 0; slot < 4; slot++) { 134 slotval = (pcia_present >> 135 PCIA_PRESENT_SLOTSHIFT(hpc, slot)) & 136 PCIA_PRESENT_SLOT_MASK; 137 if (slotval == PCIA_PRESENT_SLOT_NONE) 138 continue; 139 switch (slotval) { 140 case PCIA_PRESENT_SLOT_25W: 141 str = "25"; 142 break; 143 case PCIA_PRESENT_SLOT_15W: 144 str = "15"; 145 break; 146 case PCIA_PRESENT_SLOW_7W: 147 default: /* XXX gcc */ 148 str = "7.5"; 149 break; 150 } 151 aprint_normal_dev(sc->dwlpx_dev, 152 "hpc %d slot %d: %s watt module\n", 153 hpc, slot, str); 154 } 155 } 156 } 157 #endif 158 159 /* 160 * Set up interrupts 161 */ 162 alpha_pci_intr_init(&sc->dwlpx_cc, &sc->dwlpx_cc.cc_iot, 163 &sc->dwlpx_cc.cc_memt, &sc->dwlpx_cc.cc_pc); 164 165 /* 166 * Attach PCI bus 167 */ 168 pba.pba_iot = &sc->dwlpx_cc.cc_iot; 169 pba.pba_memt = &sc->dwlpx_cc.cc_memt; 170 pba.pba_dmat = /* start with direct, may change... */ 171 alphabus_dma_get_tag(&sc->dwlpx_cc.cc_dmat_direct, ALPHA_BUS_PCI); 172 pba.pba_dmat64 = NULL; 173 pba.pba_pc = &sc->dwlpx_cc.cc_pc; 174 pba.pba_bus = 0; 175 pba.pba_bridgetag = NULL; 176 pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY | 177 PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY; 178 config_found(self, &pba, pcibusprint, CFARGS_NONE); 179 } 180 181 void 182 dwlpx_init(struct dwlpx_softc *sc) 183 { 184 uint32_t ctl; 185 struct dwlpx_config *ccp = &sc->dwlpx_cc; 186 unsigned long vec, ls = DWLPX_SYSBASE(sc); 187 int i; 188 189 if (ccp->cc_initted == 0) { 190 /* 191 * On reads, you get a fault if you read a nonexisted HPC. 192 * We know the internal KFTIA hose (hose 0) has only 2 HPCs, 193 * but we can also actually probe for HPCs. 194 * Assume at least one. 195 */ 196 for (sc->dwlpx_nhpc = 1; sc->dwlpx_nhpc < NHPC; 197 sc->dwlpx_nhpc++) { 198 if (badaddr(KV(PCIA_CTL(sc->dwlpx_nhpc) + ls), 199 sizeof (ctl)) != 0) { 200 break; 201 } 202 } 203 if (sc->dwlpx_nhpc != NHPC) { 204 /* clear (potential) Illegal CSR Address Error */ 205 REGVAL(PCIA_ERR(0) + DWLPX_SYSBASE(sc)) = 206 PCIA_ERR_ALLERR; 207 } 208 209 dwlpx_bus_io_init(&ccp->cc_iot, ccp); 210 dwlpx_bus_mem_init(&ccp->cc_memt, ccp); 211 } 212 dwlpx_pci_init(&ccp->cc_pc, ccp); 213 ccp->cc_sc = sc; 214 215 /* 216 * Establish a precalculated base for convenience's sake. 217 */ 218 ccp->cc_sysbase = ls; 219 220 /* 221 * If there are only 2 HPCs, then the 'present' register is not 222 * implemented, so there will only ever be 32K SG entries. Otherwise 223 * any revision greater than zero will have 128K entries. 224 */ 225 ctl = REGVAL(PCIA_PRESENT + ccp->cc_sysbase); 226 if (sc->dwlpx_nhpc == 2) { 227 sc->dwlpx_sgmapsz = DWLPX_SG32K; 228 #if 0 229 /* 230 * As of 2/25/98- When I enable SG128K, and then have to flip 231 * TBIT below, I get bad SGRAM errors. We'll fix this later 232 * if this gets important. 233 */ 234 } else if ((ctl >> PCIA_PRESENT_REVSHIFT) & PCIA_PRESENT_REVMASK) { 235 sc->dwlpx_sgmapsz = DWLPX_SG128K; 236 #endif 237 } else { 238 sc->dwlpx_sgmapsz = DWLPX_SG32K; 239 } 240 241 /* 242 * Set up interrupt stuff for this DWLPX. 243 * 244 * Note that all PCI interrupt pins are disabled at this time. 245 * 246 * Do this even for all HPCs- even for the nonexistent 247 * one on hose zero of a KFTIA. 248 */ 249 mutex_enter(&cpu_lock); 250 vec = scb_alloc(dwlpx_errintr, sc); 251 mutex_exit(&cpu_lock); 252 if (vec == SCB_ALLOC_FAILED) 253 panic("%s: unable to allocate error vector", 254 device_xname(sc->dwlpx_dev)); 255 aprint_normal_dev(sc->dwlpx_dev, "error interrupt at vector 0x%lx\n", 256 vec); 257 for (i = 0; i < NHPC; i++) { 258 REGVAL(PCIA_IMASK(i) + ccp->cc_sysbase) = DWLPX_IMASK_DFLT; 259 REGVAL(PCIA_ERRVEC(i) + ccp->cc_sysbase) = vec; 260 } 261 262 /* 263 * Establish HAE values, as well as make sure of sanity elsewhere. 264 */ 265 for (i = 0; i < sc->dwlpx_nhpc; i++) { 266 ctl = REGVAL(PCIA_CTL(i) + ccp->cc_sysbase); 267 ctl &= 0x0fffffff; 268 ctl &= ~(PCIA_CTL_MHAE(0x1f) | PCIA_CTL_IHAE(0x1f)); 269 /* 270 * I originally also had it or'ing in 3, which makes no sense. 271 */ 272 273 ctl |= PCIA_CTL_RMMENA | PCIA_CTL_RMMARB; 274 275 /* 276 * Only valid if we're attached to a KFTIA or a KTHA. 277 */ 278 ctl |= PCIA_CTL_3UP; 279 280 ctl |= PCIA_CTL_CUTENA; 281 282 /* 283 * Fit in appropriate S/G Map Ram size. 284 */ 285 if (sc->dwlpx_sgmapsz == DWLPX_SG32K) 286 ctl |= PCIA_CTL_SG32K; 287 else if (sc->dwlpx_sgmapsz == DWLPX_SG128K) 288 ctl |= PCIA_CTL_SG128K; 289 else 290 ctl |= PCIA_CTL_SG32K; 291 292 REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) = ctl; 293 } 294 /* 295 * Enable TBIT if required 296 */ 297 if (sc->dwlpx_sgmapsz == DWLPX_SG128K) 298 REGVAL(PCIA_TBIT + ccp->cc_sysbase) = 1; 299 alpha_mb(); 300 ccp->cc_initted = 1; 301 } 302 303 void 304 dwlpx_errintr(void *arg, unsigned long vec) 305 { 306 struct dwlpx_softc *sc = arg; 307 struct dwlpx_config *ccp = &sc->dwlpx_cc; 308 int i; 309 struct { 310 uint32_t err; 311 uint32_t addr; 312 } hpcs[NHPC]; 313 314 for (i = 0; i < sc->dwlpx_nhpc; i++) { 315 hpcs[i].err = REGVAL(PCIA_ERR(i) + ccp->cc_sysbase); 316 hpcs[i].addr = REGVAL(PCIA_FADR(i) + ccp->cc_sysbase); 317 } 318 aprint_error_dev(sc->dwlpx_dev, "node %d hose %d error interrupt\n", 319 sc->dwlpx_node, sc->dwlpx_hosenum); 320 321 for (i = 0; i < sc->dwlpx_nhpc; i++) { 322 if ((hpcs[i].err & PCIA_ERR_ERROR) == 0) 323 continue; 324 aprint_error("\tHPC %d: ERR=0x%08x; DMA %s Memory, " 325 "Failing Address 0x%x\n", 326 i, hpcs[i].err, hpcs[i].addr & 0x1? "write to" : 327 "read from", hpcs[i].addr & ~3); 328 if (hpcs[i].err & PCIA_ERR_SERR_L) 329 aprint_error("\t PCI device asserted SERR_L\n"); 330 if (hpcs[i].err & PCIA_ERR_ILAT) 331 aprint_error("\t Incremental Latency Exceeded\n"); 332 if (hpcs[i].err & PCIA_ERR_SGPRTY) 333 aprint_error("\t CPU access of SG RAM Parity Error\n"); 334 if (hpcs[i].err & PCIA_ERR_ILLCSR) 335 aprint_error("\t Illegal CSR Address Error\n"); 336 if (hpcs[i].err & PCIA_ERR_PCINXM) 337 aprint_error("\t Nonexistent PCI Address Error\n"); 338 if (hpcs[i].err & PCIA_ERR_DSCERR) 339 aprint_error("\t PCI Target Disconnect Error\n"); 340 if (hpcs[i].err & PCIA_ERR_ABRT) 341 aprint_error("\t PCI Target Abort Error\n"); 342 if (hpcs[i].err & PCIA_ERR_WPRTY) 343 aprint_error("\t PCI Write Parity Error\n"); 344 if (hpcs[i].err & PCIA_ERR_DPERR) 345 aprint_error("\t PCI Data Parity Error\n"); 346 if (hpcs[i].err & PCIA_ERR_APERR) 347 aprint_error("\t PCI Address Parity Error\n"); 348 if (hpcs[i].err & PCIA_ERR_DFLT) 349 aprint_error("\t SG Map RAM Invalid Entry Error\n"); 350 if (hpcs[i].err & PCIA_ERR_DPRTY) 351 aprint_error("\t DMA access of SG RAM Parity Error\n"); 352 if (hpcs[i].err & PCIA_ERR_DRPERR) 353 aprint_error("\t DMA Read Return Parity Error\n"); 354 if (hpcs[i].err & PCIA_ERR_MABRT) 355 aprint_error("\t PCI Master Abort Error\n"); 356 if (hpcs[i].err & PCIA_ERR_CPRTY) 357 aprint_error("\t CSR Parity Error\n"); 358 if (hpcs[i].err & PCIA_ERR_COVR) 359 aprint_error("\t CSR Overrun Error\n"); 360 if (hpcs[i].err & PCIA_ERR_MBPERR) 361 aprint_error("\t Mailbox Parity Error\n"); 362 if (hpcs[i].err & PCIA_ERR_MBILI) 363 aprint_error("\t Mailbox Illegal Length Error\n"); 364 REGVAL(PCIA_ERR(i) + ccp->cc_sysbase) = hpcs[i].err; 365 } 366 } 367
Indexes created Thu Sep 25 06:09:39 GMT 2025