1 /* $NetBSD: e500_timer.c,v 1.8 2023/08/10 20:02:56 andvar Exp $ */ 2 /*- 3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 8 * Agency and which was developed by Matt Thomas of 3am Software Foundry. 9 * 10 * This material is based upon work supported by the Defense Advanced Research 11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 12 * Contract No. N66001-09-C-2073. 13 * Approved for Public Release, Distribution Unlimited 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: e500_timer.c,v 1.8 2023/08/10 20:02:56 andvar Exp $"); 39 40 #include <sys/param.h> 41 #include <sys/kernel.h> 42 #include <sys/systm.h> 43 #include <sys/timetc.h> 44 #include <sys/intr.h> 45 #include <sys/cpu.h> 46 47 #include <uvm/uvm_extern.h> 48 49 #include <powerpc/spr.h> 50 #include <powerpc/booke/spr.h> 51 #include <powerpc/booke/cpuvar.h> 52 #include <powerpc/booke/e500reg.h> 53 #include <powerpc/booke/e500var.h> 54 #include <powerpc/booke/openpicreg.h> 55 56 uint32_t ticks_per_sec; 57 static u_long ns_per_tick; 58 59 static void init_ppcbooke_tc(void); 60 static u_int get_ppcbooke_timecount(struct timecounter *); 61 62 static struct timecounter ppcbooke_timecounter = { 63 .tc_get_timecount = get_ppcbooke_timecount, 64 .tc_counter_mask = ~0u, 65 .tc_name = "ppc_timebase", 66 .tc_quality = 100, 67 }; 68 69 static inline void 70 openpic_write(struct cpu_softc *cpu, bus_size_t offset, uint32_t val) 71 { 72 73 return bus_space_write_4(cpu->cpu_bst, cpu->cpu_bsh, 74 OPENPIC_BASE + offset, val); 75 } 76 77 int 78 e500_clock_intr(void *v) 79 { 80 struct trapframe * const tf = v; 81 struct cpu_info * const ci = curcpu(); 82 struct cpu_softc * const cpu = ci->ci_softc; 83 u_int nticks; 84 85 /* 86 * Check whether we are initialized. 87 */ 88 if (!cpu->cpu_ticks_per_clock_intr) 89 return 0; 90 91 /* 92 * Now let's how delayed the clock interrupt was. Obviously it must 93 * at least one clock tick since the clock interrupt. But it might 94 * be more if interrupts were blocked for a long time. We keep 95 * subtracting an interrupts We should be 96 * [well] within a single tick. 97 * We add back one tick (which should put us back above 0). If we 98 * are still below 0, keep adding ticks until we are above 0. 99 */ 100 const uint64_t now = mftb(); 101 uint64_t latency = now - (ci->ci_lastintr + cpu->cpu_ticks_per_clock_intr); 102 #if 0 103 uint64_t orig_latency = latency; 104 #endif 105 if (now < ci->ci_lastintr + cpu->cpu_ticks_per_clock_intr) 106 latency = 0; 107 108 nticks = 1 + latency / cpu->cpu_ticks_per_clock_intr; 109 latency %= cpu->cpu_ticks_per_clock_intr; 110 #if 0 111 for (nticks = 1; latency >= cpu->cpu_ticks_per_clock_intr; nticks++) { 112 latency -= cpu->cpu_ticks_per_clock_intr; 113 } 114 #endif 115 116 ci->ci_ev_clock.ev_count++; 117 cpu->cpu_ev_late_clock.ev_count += nticks - 1; 118 119 /* 120 * lasttb is used during microtime. Set it to the virtual 121 * start of this tick interval. 122 */ 123 #if 0 124 if (nticks > 10 || now - ci->ci_lastintr < 7 * cpu->cpu_ticks_per_clock_intr / 8) 125 printf("%s: nticks=%u lastintr=%#"PRIx64"(%#"PRIx64") now=%#"PRIx64" latency=%#"PRIx64" orig=%#"PRIx64"\n", __func__, 126 nticks, ci->ci_lastintr, now - latency, now, latency, orig_latency); 127 #endif 128 ci->ci_lastintr = now - latency; 129 ci->ci_lasttb = now; 130 131 wrtee(PSL_EE); /* Reenable interrupts */ 132 133 /* 134 * Do standard timer interrupt stuff. 135 */ 136 while (nticks-- > 0) { 137 hardclock(&tf->tf_cf); 138 } 139 140 wrtee(0); /* turn off interrupts */ 141 142 tf->tf_srr1 &= ~PSL_POW; /* make cpu_idle exit */ 143 144 return 1; 145 } 146 147 void 148 cpu_initclocks(void) 149 { 150 struct cpu_info * const ci = curcpu(); 151 struct cpu_softc * const cpu = ci->ci_softc; 152 153 cpu->cpu_ticks_per_clock_intr = (ci->ci_data.cpu_cc_freq + hz/2 - 1) / hz; 154 155 /* interrupt established in e500_intr_cpu_init */ 156 157 ci->ci_lastintr = ci->ci_lasttb = mftb(); 158 openpic_write(cpu, cpu->cpu_clock_gtbcr, 159 GTBCR_CI | cpu->cpu_ticks_per_clock_intr); 160 openpic_write(cpu, cpu->cpu_clock_gtbcr, 161 cpu->cpu_ticks_per_clock_intr); 162 163 if (CPU_IS_PRIMARY(ci)) 164 init_ppcbooke_tc(); 165 } 166 167 void 168 calc_delayconst(void) 169 { 170 struct cpu_info * const ci = curcpu(); 171 172 ci->ci_data.cpu_cc_freq = board_info_get_number("timebase-frequency"); 173 ticks_per_sec = (uint32_t)ci->ci_data.cpu_cc_freq; 174 ns_per_tick = 1000000000 / (u_int)ci->ci_data.cpu_cc_freq; 175 } 176 177 static u_int 178 get_ppcbooke_timecount(struct timecounter *tc) 179 { 180 return mftbl(); 181 } 182 183 /* 184 * Wait for about n microseconds (at least!). 185 */ 186 void 187 delay(unsigned int n) 188 { 189 uint64_t tb; 190 u_long tbh, tbl, scratch; 191 192 tb = mftb(); 193 /* use 1000ULL to force 64 bit math to avoid 32 bit overflows */ 194 tb += (n * 1000ULL + ns_per_tick - 1) / ns_per_tick; 195 tbh = tb >> 32; 196 tbl = tb; 197 __asm volatile ( 198 "1: mfspr %0,%4" "\n" 199 " cmplw %0,%1" "\n" 200 " blt 1b" "\n" 201 " bgt 2f" "\n" 202 " mfspr %0,%3" "\n" 203 " cmplw %0,%2" "\n" 204 " blt 1b" "\n" 205 "2:" "\n" 206 : "=&r"(scratch) 207 : "r"(tbh), "r"(tbl), "n"(SPR_TBL), "n"(SPR_TBU) 208 : "cr0"); 209 } 210 211 /* 212 * Nothing to do. 213 */ 214 void 215 setstatclockrate(int arg) 216 { 217 218 /* Do nothing */ 219 } 220 221 static void 222 init_ppcbooke_tc(void) 223 { 224 /* from machdep initialization */ 225 ppcbooke_timecounter.tc_frequency = curcpu()->ci_data.cpu_cc_freq; 226 tc_init(&ppcbooke_timecounter); 227 } 228
Indexes created Sat Sep 20 22:09:52 GMT 2025