1 /* $NetBSD: ebusreg.h,v 1.10 2022/07/21 14:41:59 andvar Exp $ */ 2 3 /* 4 * Copyright (c) 1999 Matthew R. Green 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef _DEV_EBUS_EBUSREG_H_ 30 #define _DEV_EBUS_EBUSREG_H_ 31 32 /* 33 * SPARC `ebus' 34 * 35 * The `ebus' bus is designed to plug traditional PC-ISA devices into 36 * an SPARC system with as few costs as possible, without sacrificing 37 * to performance. Typically, it is implemented in the PCIO IC from 38 * SME, which also implements a `hme-compatible' PCI network device 39 * (`network'). The ebus has 4 DMA channels, similar to the DMA seen 40 * in the ESP SCSI DMA. 41 * 42 * Typical UltraSPARC systems have a NatSemi SuperIO IC to provide 43 * serial ports for the keyboard and mouse (`se'), floppy disk 44 * controller (`fdthree'), parallel port controller (`bpp') connected 45 * to the ebus, and a PCI-IDE controller (connected directly to the 46 * PCI bus, of course), as well as a Siemens Nixdorf SAB82532 dual 47 * channel serial controller (`su' providing ttya and ttyb), an MK48T59 48 * EEPROM/clock controller (also where the idprom, including the 49 * ethernet address, is located), the audio system (`SUNW,CS4231', same 50 * as other UltraSPARC and some SPARC systems), and other various 51 * internal devices found on traditional SPARC systems such as the 52 * `power', `flashprom', etc., devices. Other machines with this 53 * device include microSPARC-IIep based systems, e.g. JavaStation10. 54 * 55 * The ebus uses an interrupt mapping scheme similar to PCI, though 56 * the actual structures are different. 57 */ 58 59 /* 60 * EBus PROM structures. There's no official OFW binding for EBus, 61 * so ms-IIep PROMs deviate from de-facto standard used on Ultra's. 62 * 63 * EBus address is represented in PROM by 2 cells: bar and offset. 64 * "bar" specifies the EBus BAR register used to translate the 65 * "offset" into PCI address space. 66 * 67 * On Ultra the bar is the _offset_ of the BAR in PCI config space but 68 * in (some?) ms-IIep systems (e.g. Krups) it's the _number_ of the 69 * BAR - e.g. BAR1 is represented by 1 in Krups PROM, while on Ultra 70 * it's 0x14. 71 */ 72 73 struct ebus_regs { 74 uint32_t hi; /* high bits of physaddr */ 75 uint32_t lo; 76 uint32_t size; 77 }; 78 79 #define EBUS_ADDR_FROM_REG(reg) BUS_ADDR((reg)->hi, (reg)->lo) 80 81 82 struct ebus_ranges { 83 uint32_t child_hi; /* child high phys addr */ 84 uint32_t child_lo; /* child low phys addr */ 85 uint32_t phys_hi; /* parent high phys addr */ 86 uint32_t phys_mid; /* parent mid phys addr */ 87 uint32_t phys_lo; /* parent low phys addr */ 88 uint32_t size; 89 }; 90 91 struct ebus_mainbus_ranges { 92 u_int32_t child_hi; 93 u_int32_t child_lo; 94 u_int32_t phys_hi; 95 u_int32_t phys_lo; 96 u_int32_t size; 97 }; 98 99 100 /* NB: ms-IIep PROMs lack these interrupt-related properties */ 101 struct ebus_interrupt_map { 102 uint32_t hi; /* high phys addr mask */ 103 uint32_t lo; /* low phys addr mask */ 104 uint32_t intr; /* interrupt mask */ 105 int32_t cnode; /* child node */ 106 uint32_t cintr; /* child interrupt */ 107 }; 108 109 struct ebus_interrupt_map_mask { 110 uint32_t hi; /* high phys addr */ 111 uint32_t lo; /* low phys addr */ 112 uint32_t intr; /* interrupt */ 113 }; 114 115 116 /* 117 * DMA controller registers. 118 * 119 * The "next" registers are at the same locations. 120 * Which one you write to depends on EN_NEXT bit in the DCSR. 121 */ 122 #define EBUS_DMAC_DCSR 0 /* control/status register */ 123 #define EBUS_DMAC_DACR 4 /* address count register */ 124 #define EBUS_DMAC_DNAR 4 /* next address register */ 125 #define EBUS_DMAC_DBCR 8 /* byte count register */ 126 #define EBUS_DMAC_DNBR 8 /* next byte register */ 127 128 #define EBUS_DMAC_SIZE 12 129 130 131 /* 132 * DCSR bits (PCIO manual, Table 7-23, pp 134-135) 133 * 134 * On Reset all the register bits except ID will be 0 and CYC_PENDING 135 * will reflect the status of any pending requests. 136 */ 137 #define EBDMA_INT_PEND 0x00000001 /* interrupt pending */ 138 #define EBDMA_ERR_PEND 0x00000002 /* error pending */ 139 #define EBDMA_DRAIN 0x00000004 /* fifo's being drained to memory */ 140 #define EBDMA_INT_EN 0x00000010 /* enable interrupts */ 141 #define EBDMA_RESET 0x00000080 /* reset - write 0 to clear */ 142 #define EBDMA_WRITE 0x00000100 /* 0: mem->dev, 1: dev->mem */ 143 #define EBDMA_EN_DMA 0x00000200 /* enable DMA */ 144 #define EBDMA_CYC_PEND 0x00000400 /* DMA cycle pending 145 - not safe to clear reset */ 146 #define EBDMA_DIAG_RD_DONE 0x00000800 /* DIAG mode: DMA read completed */ 147 #define EBDMA_DIAG_WR_DONE 0x00001000 /* DIAG mode: DMA write completed */ 148 #define EBDMA_EN_CNT 0x00002000 /* enable byte counter */ 149 #define EBDMA_TC 0x00004000 /* terminal count 150 - write 1 to clear */ 151 #define EBDMA_DIS_CSR_DRN 0x00010000 /* disable fifo draining 152 on slave writes to CSR */ 153 #define EBDMA_BURST_SIZE_MASK 0x000c0000 /* burst sizes: */ 154 #define EBDMA_BURST_SIZE_4 0x00000000 /* 00 - 4 words */ 155 #define EBDMA_BURST_SIZE_8 0x00040000 /* 01 - 8 words */ 156 #define EBDMA_BURST_SIZE_1 0x00080000 /* 10 - 1 word */ 157 #define EBDMA_BURST_SIZE_16 0x000c0000 /* 11 - 16 words */ 158 #define EBDMA_DIAG_EN 0x00100000 /* enable diag mode */ 159 #define EBDMA_DIS_ERR_PEND 0x00400000 /* disable stop/interrupt 160 on error pending */ 161 #define EBDMA_TCI_DIS 0x00800000 /* disable interrupt on TC */ 162 #define EBDMA_EN_NEXT 0x01000000 /* enable next address autoload 163 (must set EN_CNT too) */ 164 #define EBDMA_DMA_ON 0x02000000 /* DMA is able to respond */ 165 #define EBDMA_A_LOADED 0x04000000 /* DACR loaded 166 (directly or from DNAR) */ 167 #define EBDMA_NA_LOADED 0x08000000 /* DNAR loaded */ 168 #define EBDMA_ID_MASK 0xf0000000 /* Device ID = 0xC */ 169 170 #define EBUS_DCSR_BITS \ 171 "\20\34NA_LOADED\33A_LOADED\32DMA_ON\31EN_NEXT\30TCI_DIS\27DIS_ERR_PEND" \ 172 "\25DIAG_EN\21DIS_CSR_DRN\17TC\16EN_CNT\15DIAG_WR_DONE\14DIAG_RD_DONE" \ 173 "\13CYC_PEND\12EN_DMA\11WRITE\10RESET\6INT_EN\3DRAIN\2ERR_PEND\1INT_PEND" 174 175 #endif /* _DEV_EBUS_EBUSREG_H_ */ 176
Indexes created Sun Sep 21 18:09:52 GMT 2025