1 /* $NetBSD: sumo_dpm.h,v 1.3 2021/12/18 23:45:43 riastradh Exp $ */ 2 3 /* 4 * Copyright 2012 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 #ifndef __SUMO_DPM_H__ 26 #define __SUMO_DPM_H__ 27 28 #include "atom.h" 29 #include "radeon.h" 30 31 #define SUMO_MAX_HARDWARE_POWERLEVELS 5 32 #define SUMO_PM_NUMBER_OF_TC 15 33 34 struct sumo_pl { 35 u32 sclk; 36 u32 vddc_index; 37 u32 ds_divider_index; 38 u32 ss_divider_index; 39 u32 allow_gnb_slow; 40 u32 sclk_dpm_tdp_limit; 41 }; 42 43 /* used for the flags field */ 44 #define SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE (1 << 0) 45 #define SUMO_POWERSTATE_FLAGS_BOOST_STATE (1 << 1) 46 47 struct sumo_ps { 48 struct sumo_pl levels[SUMO_MAX_HARDWARE_POWERLEVELS]; 49 u32 num_levels; 50 /* flags */ 51 u32 flags; 52 }; 53 54 #define NUMBER_OF_M3ARB_PARAM_SETS 10 55 #define SUMO_MAX_NUMBER_VOLTAGES 4 56 57 struct sumo_disp_clock_voltage_mapping_table { 58 u32 num_max_voltage_levels; 59 u32 display_clock_frequency[SUMO_MAX_NUMBER_VOLTAGES]; 60 }; 61 62 struct sumo_vid_mapping_entry { 63 u16 vid_2bit; 64 u16 vid_7bit; 65 }; 66 67 struct sumo_vid_mapping_table { 68 u32 num_entries; 69 struct sumo_vid_mapping_entry entries[SUMO_MAX_NUMBER_VOLTAGES]; 70 }; 71 72 struct sumo_sclk_voltage_mapping_entry { 73 u32 sclk_frequency; 74 u16 vid_2bit; 75 u16 rsv; 76 }; 77 78 struct sumo_sclk_voltage_mapping_table { 79 u32 num_max_dpm_entries; 80 struct sumo_sclk_voltage_mapping_entry entries[SUMO_MAX_HARDWARE_POWERLEVELS]; 81 }; 82 83 struct sumo_sys_info { 84 u32 bootup_sclk; 85 u32 min_sclk; 86 u32 bootup_uma_clk; 87 u16 bootup_nb_voltage_index; 88 u8 htc_tmp_lmt; 89 u8 htc_hyst_lmt; 90 struct sumo_sclk_voltage_mapping_table sclk_voltage_mapping_table; 91 struct sumo_disp_clock_voltage_mapping_table disp_clk_voltage_mapping_table; 92 struct sumo_vid_mapping_table vid_mapping_table; 93 u32 csr_m3_arb_cntl_default[NUMBER_OF_M3ARB_PARAM_SETS]; 94 u32 csr_m3_arb_cntl_uvd[NUMBER_OF_M3ARB_PARAM_SETS]; 95 u32 csr_m3_arb_cntl_fs3d[NUMBER_OF_M3ARB_PARAM_SETS]; 96 u32 sclk_dpm_boost_margin; 97 u32 sclk_dpm_throttle_margin; 98 u32 sclk_dpm_tdp_limit_pg; 99 u32 gnb_tdp_limit; 100 u32 sclk_dpm_tdp_limit_boost; 101 u32 boost_sclk; 102 u32 boost_vid_2bit; 103 bool enable_boost; 104 }; 105 106 struct sumo_power_info { 107 u32 asi; 108 u32 pasi; 109 u32 bsp; 110 u32 bsu; 111 u32 pbsp; 112 u32 pbsu; 113 u32 dsp; 114 u32 psp; 115 u32 thermal_auto_throttling; 116 u32 uvd_m3_arbiter; 117 u32 fw_version; 118 struct sumo_sys_info sys_info; 119 struct sumo_pl acpi_pl; 120 struct sumo_pl boot_pl; 121 struct sumo_pl boost_pl; 122 bool disable_gfx_power_gating_in_uvd; 123 bool driver_nbps_policy_disable; 124 bool enable_alt_vddnb; 125 bool enable_dynamic_m3_arbiter; 126 bool enable_gfx_clock_gating; 127 bool enable_gfx_power_gating; 128 bool enable_mg_clock_gating; 129 bool enable_sclk_ds; 130 bool enable_auto_thermal_throttling; 131 bool enable_dynamic_patch_ps; 132 bool enable_dpm; 133 bool enable_boost; 134 struct radeon_ps current_rps; 135 struct sumo_ps current_ps; 136 struct radeon_ps requested_rps; 137 struct sumo_ps requested_ps; 138 }; 139 140 #define SUMO_UTC_DFLT_00 0x48 141 #define SUMO_UTC_DFLT_01 0x44 142 #define SUMO_UTC_DFLT_02 0x44 143 #define SUMO_UTC_DFLT_03 0x44 144 #define SUMO_UTC_DFLT_04 0x44 145 #define SUMO_UTC_DFLT_05 0x44 146 #define SUMO_UTC_DFLT_06 0x44 147 #define SUMO_UTC_DFLT_07 0x44 148 #define SUMO_UTC_DFLT_08 0x44 149 #define SUMO_UTC_DFLT_09 0x44 150 #define SUMO_UTC_DFLT_10 0x44 151 #define SUMO_UTC_DFLT_11 0x44 152 #define SUMO_UTC_DFLT_12 0x44 153 #define SUMO_UTC_DFLT_13 0x44 154 #define SUMO_UTC_DFLT_14 0x44 155 156 #define SUMO_DTC_DFLT_00 0x48 157 #define SUMO_DTC_DFLT_01 0x44 158 #define SUMO_DTC_DFLT_02 0x44 159 #define SUMO_DTC_DFLT_03 0x44 160 #define SUMO_DTC_DFLT_04 0x44 161 #define SUMO_DTC_DFLT_05 0x44 162 #define SUMO_DTC_DFLT_06 0x44 163 #define SUMO_DTC_DFLT_07 0x44 164 #define SUMO_DTC_DFLT_08 0x44 165 #define SUMO_DTC_DFLT_09 0x44 166 #define SUMO_DTC_DFLT_10 0x44 167 #define SUMO_DTC_DFLT_11 0x44 168 #define SUMO_DTC_DFLT_12 0x44 169 #define SUMO_DTC_DFLT_13 0x44 170 #define SUMO_DTC_DFLT_14 0x44 171 172 #define SUMO_AH_DFLT 5 173 174 #define SUMO_R_DFLT0 70 175 #define SUMO_R_DFLT1 70 176 #define SUMO_R_DFLT2 70 177 #define SUMO_R_DFLT3 70 178 #define SUMO_R_DFLT4 100 179 180 #define SUMO_L_DFLT0 0 181 #define SUMO_L_DFLT1 20 182 #define SUMO_L_DFLT2 20 183 #define SUMO_L_DFLT3 20 184 #define SUMO_L_DFLT4 20 185 #define SUMO_VRC_DFLT 0x30033 186 #define SUMO_MGCGTTLOCAL0_DFLT 0 187 #define SUMO_MGCGTTLOCAL1_DFLT 0 188 #define SUMO_GICST_DFLT 19 189 #define SUMO_SST_DFLT 8 190 #define SUMO_VOLTAGEDROPT_DFLT 1 191 #define SUMO_GFXPOWERGATINGT_DFLT 100 192 193 /* sumo_dpm.c */ 194 void sumo_gfx_clockgating_initialize(struct radeon_device *rdev); 195 void sumo_program_vc(struct radeon_device *rdev, u32 vrc); 196 void sumo_clear_vc(struct radeon_device *rdev); 197 void sumo_program_sstp(struct radeon_device *rdev); 198 void sumo_take_smu_control(struct radeon_device *rdev, bool enable); 199 void sumo_construct_sclk_voltage_mapping_table(struct radeon_device *rdev, 200 struct sumo_sclk_voltage_mapping_table *sclk_voltage_mapping_table, 201 ATOM_AVAILABLE_SCLK_LIST *table); 202 void sumo_construct_vid_mapping_table(struct radeon_device *rdev, 203 struct sumo_vid_mapping_table *vid_mapping_table, 204 ATOM_AVAILABLE_SCLK_LIST *table); 205 u32 sumo_convert_vid2_to_vid7(struct radeon_device *rdev, 206 struct sumo_vid_mapping_table *vid_mapping_table, 207 u32 vid_2bit); 208 u32 sumo_get_sleep_divider_from_id(u32 id); 209 u32 sumo_get_sleep_divider_id_from_clock(struct radeon_device *rdev, 210 u32 sclk, 211 u32 min_sclk_in_sr); 212 213 /* sumo_smc.c */ 214 void sumo_initialize_m3_arb(struct radeon_device *rdev); 215 void sumo_smu_pg_init(struct radeon_device *rdev); 216 void sumo_set_tdp_limit(struct radeon_device *rdev, u32 index, u32 tdp_limit); 217 void sumo_smu_notify_alt_vddnb_change(struct radeon_device *rdev, 218 bool powersaving, bool force_nbps1); 219 void sumo_boost_state_enable(struct radeon_device *rdev, bool enable); 220 void sumo_enable_boost_timer(struct radeon_device *rdev); 221 u32 sumo_get_running_fw_version(struct radeon_device *rdev); 222 223 #endif 224
Indexes created Sun Sep 21 16:09:51 GMT 2025