1 /* $NetBSD: amdgpu_dcn10_stream_encoder.c,v 1.3 2021/12/19 11:25:01 riastradh Exp $ */ 2 3 /* 4 * Copyright 2012-15 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: AMD 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: amdgpu_dcn10_stream_encoder.c,v 1.3 2021/12/19 11:25:01 riastradh Exp $"); 30 31 #include <linux/delay.h> 32 33 #include "dc_bios_types.h" 34 #include "dcn10_stream_encoder.h" 35 #include "reg_helper.h" 36 #include "hw_shared.h" 37 38 #define DC_LOGGER \ 39 enc1->base.ctx->logger 40 41 42 #define REG(reg)\ 43 (enc1->regs->reg) 44 45 #undef FN 46 #define FN(reg_name, field_name) \ 47 enc1->se_shift->field_name, enc1->se_mask->field_name 48 49 #define VBI_LINE_0 0 50 #define DP_BLANK_MAX_RETRY 20 51 #define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000 52 53 54 enum { 55 DP_MST_UPDATE_MAX_RETRY = 50 56 }; 57 58 #define CTX \ 59 enc1->base.ctx 60 61 void enc1_update_generic_info_packet( 62 struct dcn10_stream_encoder *enc1, 63 uint32_t packet_index, 64 const struct dc_info_packet *info_packet) 65 { 66 uint32_t regval __unused; 67 /* TODOFPGA Figure out a proper number for max_retries polling for lock 68 * use 50 for now. 69 */ 70 uint32_t max_retries = 50; 71 72 /*we need turn on clock before programming AFMT block*/ 73 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1); 74 75 if (packet_index >= 8) 76 ASSERT(0); 77 78 /* poll dig_update_lock is not locked -> asic internal signal 79 * assume otg master lock will unlock it 80 */ 81 /* REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS, 82 0, 10, max_retries);*/ 83 84 /* check if HW reading GSP memory */ 85 REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT, 86 0, 10, max_retries); 87 88 /* HW does is not reading GSP memory not reading too long -> 89 * something wrong. clear GPS memory access and notify? 90 * hw SW is writing to GSP memory 91 */ 92 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1); 93 94 /* choose which generic packet to use */ 95 regval = REG_READ(AFMT_VBI_PACKET_CONTROL); 96 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, 97 AFMT_GENERIC_INDEX, packet_index); 98 99 /* write generic packet header 100 * (4th byte is for GENERIC0 only) 101 */ 102 REG_SET_4(AFMT_GENERIC_HDR, 0, 103 AFMT_GENERIC_HB0, info_packet->hb0, 104 AFMT_GENERIC_HB1, info_packet->hb1, 105 AFMT_GENERIC_HB2, info_packet->hb2, 106 AFMT_GENERIC_HB3, info_packet->hb3); 107 108 /* write generic packet contents 109 * (we never use last 4 bytes) 110 * there are 8 (0-7) mmDIG0_AFMT_GENERIC0_x registers 111 */ 112 { 113 const uint32_t *content = 114 (const uint32_t *) &info_packet->sb[0]; 115 116 REG_WRITE(AFMT_GENERIC_0, *content++); 117 REG_WRITE(AFMT_GENERIC_1, *content++); 118 REG_WRITE(AFMT_GENERIC_2, *content++); 119 REG_WRITE(AFMT_GENERIC_3, *content++); 120 REG_WRITE(AFMT_GENERIC_4, *content++); 121 REG_WRITE(AFMT_GENERIC_5, *content++); 122 REG_WRITE(AFMT_GENERIC_6, *content++); 123 REG_WRITE(AFMT_GENERIC_7, *content); 124 } 125 126 switch (packet_index) { 127 case 0: 128 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 129 AFMT_GENERIC0_FRAME_UPDATE, 1); 130 break; 131 case 1: 132 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 133 AFMT_GENERIC1_FRAME_UPDATE, 1); 134 break; 135 case 2: 136 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 137 AFMT_GENERIC2_FRAME_UPDATE, 1); 138 break; 139 case 3: 140 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 141 AFMT_GENERIC3_FRAME_UPDATE, 1); 142 break; 143 case 4: 144 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 145 AFMT_GENERIC4_FRAME_UPDATE, 1); 146 break; 147 case 5: 148 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 149 AFMT_GENERIC5_FRAME_UPDATE, 1); 150 break; 151 case 6: 152 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 153 AFMT_GENERIC6_FRAME_UPDATE, 1); 154 break; 155 case 7: 156 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 157 AFMT_GENERIC7_FRAME_UPDATE, 1); 158 break; 159 default: 160 break; 161 } 162 } 163 164 static void enc1_update_hdmi_info_packet( 165 struct dcn10_stream_encoder *enc1, 166 uint32_t packet_index, 167 const struct dc_info_packet *info_packet) 168 { 169 uint32_t cont, send, line; 170 171 if (info_packet->valid) { 172 enc1_update_generic_info_packet( 173 enc1, 174 packet_index, 175 info_packet); 176 177 /* enable transmission of packet(s) - 178 * packet transmission begins on the next frame 179 */ 180 cont = 1; 181 /* send packet(s) every frame */ 182 send = 1; 183 /* select line number to send packets on */ 184 line = 2; 185 } else { 186 cont = 0; 187 send = 0; 188 line = 0; 189 } 190 191 /* choose which generic packet control to use */ 192 switch (packet_index) { 193 case 0: 194 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0, 195 HDMI_GENERIC0_CONT, cont, 196 HDMI_GENERIC0_SEND, send, 197 HDMI_GENERIC0_LINE, line); 198 break; 199 case 1: 200 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0, 201 HDMI_GENERIC1_CONT, cont, 202 HDMI_GENERIC1_SEND, send, 203 HDMI_GENERIC1_LINE, line); 204 break; 205 case 2: 206 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1, 207 HDMI_GENERIC0_CONT, cont, 208 HDMI_GENERIC0_SEND, send, 209 HDMI_GENERIC0_LINE, line); 210 break; 211 case 3: 212 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1, 213 HDMI_GENERIC1_CONT, cont, 214 HDMI_GENERIC1_SEND, send, 215 HDMI_GENERIC1_LINE, line); 216 break; 217 case 4: 218 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2, 219 HDMI_GENERIC0_CONT, cont, 220 HDMI_GENERIC0_SEND, send, 221 HDMI_GENERIC0_LINE, line); 222 break; 223 case 5: 224 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2, 225 HDMI_GENERIC1_CONT, cont, 226 HDMI_GENERIC1_SEND, send, 227 HDMI_GENERIC1_LINE, line); 228 break; 229 case 6: 230 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3, 231 HDMI_GENERIC0_CONT, cont, 232 HDMI_GENERIC0_SEND, send, 233 HDMI_GENERIC0_LINE, line); 234 break; 235 case 7: 236 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3, 237 HDMI_GENERIC1_CONT, cont, 238 HDMI_GENERIC1_SEND, send, 239 HDMI_GENERIC1_LINE, line); 240 break; 241 default: 242 /* invalid HW packet index */ 243 DC_LOG_WARNING( 244 "Invalid HW packet index: %s()\n", 245 __func__); 246 return; 247 } 248 } 249 250 /* setup stream encoder in dp mode */ 251 void enc1_stream_encoder_dp_set_stream_attribute( 252 struct stream_encoder *enc, 253 struct dc_crtc_timing *crtc_timing, 254 enum dc_color_space output_color_space, 255 bool use_vsc_sdp_for_colorimetry, 256 uint32_t enable_sdp_splitting) 257 { 258 uint32_t h_active_start; 259 uint32_t v_active_start; 260 uint32_t misc0 = 0; 261 uint32_t misc1 = 0; 262 uint32_t h_blank; 263 uint32_t h_back_porch; 264 uint8_t synchronous_clock = 0; /* asynchronous mode */ 265 uint8_t colorimetry_bpc; 266 uint8_t dynamic_range_rgb __unused = 0; /*full range*/ 267 uint8_t dynamic_range_ycbcr __unused = 1; /*bt709*/ 268 uint8_t dp_pixel_encoding = 0; 269 uint8_t dp_component_depth = 0; 270 271 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 272 struct dc_crtc_timing hw_crtc_timing = *crtc_timing; 273 274 if (hw_crtc_timing.flags.INTERLACE) { 275 /*the input timing is in VESA spec format with Interlace flag =1*/ 276 hw_crtc_timing.v_total /= 2; 277 hw_crtc_timing.v_border_top /= 2; 278 hw_crtc_timing.v_addressable /= 2; 279 hw_crtc_timing.v_border_bottom /= 2; 280 hw_crtc_timing.v_front_porch /= 2; 281 hw_crtc_timing.v_sync_width /= 2; 282 } 283 284 285 /* set pixel encoding */ 286 switch (hw_crtc_timing.pixel_encoding) { 287 case PIXEL_ENCODING_YCBCR422: 288 dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR422; 289 break; 290 case PIXEL_ENCODING_YCBCR444: 291 dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR444; 292 293 if (hw_crtc_timing.flags.Y_ONLY) 294 if (hw_crtc_timing.display_color_depth != COLOR_DEPTH_666) 295 /* HW testing only, no use case yet. 296 * Color depth of Y-only could be 297 * 8, 10, 12, 16 bits 298 */ 299 dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_Y_ONLY; 300 301 /* Note: DP_MSA_MISC1 bit 7 is the indicator 302 * of Y-only mode. 303 * This bit is set in HW if register 304 * DP_PIXEL_ENCODING is programmed to 0x4 305 */ 306 break; 307 case PIXEL_ENCODING_YCBCR420: 308 dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR420; 309 break; 310 default: 311 dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_RGB444; 312 break; 313 } 314 315 misc1 = REG_READ(DP_MSA_MISC); 316 /* For YCbCr420 and BT2020 Colorimetry Formats, VSC SDP shall be used. 317 * When MISC1, bit 6, is Set to 1, a Source device uses a VSC SDP to indicate the 318 * Pixel Encoding/Colorimetry Format and that a Sink device shall ignore MISC1, bit 7, 319 * and MISC0, bits 7:1 (MISC1, bit 7, and MISC0, bits 7:1, become "don't care"). 320 */ 321 if (use_vsc_sdp_for_colorimetry) 322 misc1 = misc1 | 0x40; 323 else 324 misc1 = misc1 & ~0x40; 325 326 /* set color depth */ 327 switch (hw_crtc_timing.display_color_depth) { 328 case COLOR_DEPTH_666: 329 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_6BPC; 330 break; 331 case COLOR_DEPTH_888: 332 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_8BPC; 333 break; 334 case COLOR_DEPTH_101010: 335 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_10BPC; 336 break; 337 case COLOR_DEPTH_121212: 338 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_12BPC; 339 break; 340 case COLOR_DEPTH_161616: 341 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_16BPC; 342 break; 343 default: 344 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_6BPC; 345 break; 346 } 347 348 /* Set DP pixel encoding and component depth */ 349 REG_UPDATE_2(DP_PIXEL_FORMAT, 350 DP_PIXEL_ENCODING, dp_pixel_encoding, 351 DP_COMPONENT_DEPTH, dp_component_depth); 352 353 /* set dynamic range and YCbCr range */ 354 355 switch (hw_crtc_timing.display_color_depth) { 356 case COLOR_DEPTH_666: 357 colorimetry_bpc = 0; 358 break; 359 case COLOR_DEPTH_888: 360 colorimetry_bpc = 1; 361 break; 362 case COLOR_DEPTH_101010: 363 colorimetry_bpc = 2; 364 break; 365 case COLOR_DEPTH_121212: 366 colorimetry_bpc = 3; 367 break; 368 default: 369 colorimetry_bpc = 0; 370 break; 371 } 372 373 misc0 = misc0 | synchronous_clock; 374 misc0 = colorimetry_bpc << 5; 375 376 switch (output_color_space) { 377 case COLOR_SPACE_SRGB: 378 misc1 = misc1 & ~0x80; /* bit7 = 0*/ 379 dynamic_range_rgb = 0; /*full range*/ 380 break; 381 case COLOR_SPACE_SRGB_LIMITED: 382 misc0 = misc0 | 0x8; /* bit3=1 */ 383 misc1 = misc1 & ~0x80; /* bit7 = 0*/ 384 dynamic_range_rgb = 1; /*limited range*/ 385 break; 386 case COLOR_SPACE_YCBCR601: 387 case COLOR_SPACE_YCBCR601_LIMITED: 388 misc0 = misc0 | 0x8; /* bit3=1, bit4=0 */ 389 misc1 = misc1 & ~0x80; /* bit7 = 0*/ 390 dynamic_range_ycbcr = 0; /*bt601*/ 391 if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 392 misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */ 393 else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444) 394 misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */ 395 break; 396 case COLOR_SPACE_YCBCR709: 397 case COLOR_SPACE_YCBCR709_LIMITED: 398 misc0 = misc0 | 0x18; /* bit3=1, bit4=1 */ 399 misc1 = misc1 & ~0x80; /* bit7 = 0*/ 400 dynamic_range_ycbcr = 1; /*bt709*/ 401 if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 402 misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */ 403 else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444) 404 misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */ 405 break; 406 case COLOR_SPACE_2020_RGB_LIMITEDRANGE: 407 dynamic_range_rgb = 1; /*limited range*/ 408 break; 409 case COLOR_SPACE_2020_RGB_FULLRANGE: 410 case COLOR_SPACE_2020_YCBCR: 411 case COLOR_SPACE_XR_RGB: 412 case COLOR_SPACE_MSREF_SCRGB: 413 case COLOR_SPACE_ADOBERGB: 414 case COLOR_SPACE_DCIP3: 415 case COLOR_SPACE_XV_YCC_709: 416 case COLOR_SPACE_XV_YCC_601: 417 case COLOR_SPACE_DISPLAYNATIVE: 418 case COLOR_SPACE_DOLBYVISION: 419 case COLOR_SPACE_APPCTRL: 420 case COLOR_SPACE_CUSTOMPOINTS: 421 case COLOR_SPACE_UNKNOWN: 422 case COLOR_SPACE_YCBCR709_BLACK: 423 /* do nothing */ 424 break; 425 } 426 427 REG_SET(DP_MSA_COLORIMETRY, 0, DP_MSA_MISC0, misc0); 428 REG_WRITE(DP_MSA_MISC, misc1); /* MSA_MISC1 */ 429 430 /* dcn new register 431 * dc_crtc_timing is vesa dmt struct. data from edid 432 */ 433 REG_SET_2(DP_MSA_TIMING_PARAM1, 0, 434 DP_MSA_HTOTAL, hw_crtc_timing.h_total, 435 DP_MSA_VTOTAL, hw_crtc_timing.v_total); 436 437 /* calculate from vesa timing parameters 438 * h_active_start related to leading edge of sync 439 */ 440 441 h_blank = hw_crtc_timing.h_total - hw_crtc_timing.h_border_left - 442 hw_crtc_timing.h_addressable - hw_crtc_timing.h_border_right; 443 444 h_back_porch = h_blank - hw_crtc_timing.h_front_porch - 445 hw_crtc_timing.h_sync_width; 446 447 /* start at beginning of left border */ 448 h_active_start = hw_crtc_timing.h_sync_width + h_back_porch; 449 450 451 v_active_start = hw_crtc_timing.v_total - hw_crtc_timing.v_border_top - 452 hw_crtc_timing.v_addressable - hw_crtc_timing.v_border_bottom - 453 hw_crtc_timing.v_front_porch; 454 455 456 /* start at beginning of left border */ 457 REG_SET_2(DP_MSA_TIMING_PARAM2, 0, 458 DP_MSA_HSTART, h_active_start, 459 DP_MSA_VSTART, v_active_start); 460 461 REG_SET_4(DP_MSA_TIMING_PARAM3, 0, 462 DP_MSA_HSYNCWIDTH, 463 hw_crtc_timing.h_sync_width, 464 DP_MSA_HSYNCPOLARITY, 465 !hw_crtc_timing.flags.HSYNC_POSITIVE_POLARITY, 466 DP_MSA_VSYNCWIDTH, 467 hw_crtc_timing.v_sync_width, 468 DP_MSA_VSYNCPOLARITY, 469 !hw_crtc_timing.flags.VSYNC_POSITIVE_POLARITY); 470 471 /* HWDITH include border or overscan */ 472 REG_SET_2(DP_MSA_TIMING_PARAM4, 0, 473 DP_MSA_HWIDTH, hw_crtc_timing.h_border_left + 474 hw_crtc_timing.h_addressable + hw_crtc_timing.h_border_right, 475 DP_MSA_VHEIGHT, hw_crtc_timing.v_border_top + 476 hw_crtc_timing.v_addressable + hw_crtc_timing.v_border_bottom); 477 } 478 479 void enc1_stream_encoder_set_stream_attribute_helper( 480 struct dcn10_stream_encoder *enc1, 481 struct dc_crtc_timing *crtc_timing) 482 { 483 switch (crtc_timing->pixel_encoding) { 484 case PIXEL_ENCODING_YCBCR422: 485 REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 1); 486 break; 487 default: 488 REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 0); 489 break; 490 } 491 REG_UPDATE(DIG_FE_CNTL, TMDS_COLOR_FORMAT, 0); 492 } 493 494 /* setup stream encoder in hdmi mode */ 495 void enc1_stream_encoder_hdmi_set_stream_attribute( 496 struct stream_encoder *enc, 497 struct dc_crtc_timing *crtc_timing, 498 int actual_pix_clk_khz, 499 bool enable_audio) 500 { 501 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 502 struct bp_encoder_control cntl = {0}; 503 504 cntl.action = ENCODER_CONTROL_SETUP; 505 cntl.engine_id = enc1->base.id; 506 cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A; 507 cntl.enable_dp_audio = enable_audio; 508 cntl.pixel_clock = actual_pix_clk_khz; 509 cntl.lanes_number = LANE_COUNT_FOUR; 510 511 if (enc1->base.bp->funcs->encoder_control( 512 enc1->base.bp, &cntl) != BP_RESULT_OK) 513 return; 514 515 enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing); 516 517 /* setup HDMI engine */ 518 REG_UPDATE_6(HDMI_CONTROL, 519 HDMI_PACKET_GEN_VERSION, 1, 520 HDMI_KEEPOUT_MODE, 1, 521 HDMI_DEEP_COLOR_ENABLE, 0, 522 HDMI_DATA_SCRAMBLE_EN, 0, 523 HDMI_NO_EXTRA_NULL_PACKET_FILLED, 1, 524 HDMI_CLOCK_CHANNEL_RATE, 0); 525 526 527 switch (crtc_timing->display_color_depth) { 528 case COLOR_DEPTH_888: 529 REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0); 530 break; 531 case COLOR_DEPTH_101010: 532 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) { 533 REG_UPDATE_2(HDMI_CONTROL, 534 HDMI_DEEP_COLOR_DEPTH, 1, 535 HDMI_DEEP_COLOR_ENABLE, 0); 536 } else { 537 REG_UPDATE_2(HDMI_CONTROL, 538 HDMI_DEEP_COLOR_DEPTH, 1, 539 HDMI_DEEP_COLOR_ENABLE, 1); 540 } 541 break; 542 case COLOR_DEPTH_121212: 543 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) { 544 REG_UPDATE_2(HDMI_CONTROL, 545 HDMI_DEEP_COLOR_DEPTH, 2, 546 HDMI_DEEP_COLOR_ENABLE, 0); 547 } else { 548 REG_UPDATE_2(HDMI_CONTROL, 549 HDMI_DEEP_COLOR_DEPTH, 2, 550 HDMI_DEEP_COLOR_ENABLE, 1); 551 } 552 break; 553 case COLOR_DEPTH_161616: 554 REG_UPDATE_2(HDMI_CONTROL, 555 HDMI_DEEP_COLOR_DEPTH, 3, 556 HDMI_DEEP_COLOR_ENABLE, 1); 557 break; 558 default: 559 break; 560 } 561 562 if (actual_pix_clk_khz >= HDMI_CLOCK_CHANNEL_RATE_MORE_340M) { 563 /* enable HDMI data scrambler 564 * HDMI_CLOCK_CHANNEL_RATE_MORE_340M 565 * Clock channel frequency is 1/4 of character rate. 566 */ 567 REG_UPDATE_2(HDMI_CONTROL, 568 HDMI_DATA_SCRAMBLE_EN, 1, 569 HDMI_CLOCK_CHANNEL_RATE, 1); 570 } else if (crtc_timing->flags.LTE_340MCSC_SCRAMBLE) { 571 572 /* TODO: New feature for DCE11, still need to implement */ 573 574 /* enable HDMI data scrambler 575 * HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE 576 * Clock channel frequency is the same 577 * as character rate 578 */ 579 REG_UPDATE_2(HDMI_CONTROL, 580 HDMI_DATA_SCRAMBLE_EN, 1, 581 HDMI_CLOCK_CHANNEL_RATE, 0); 582 } 583 584 585 REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL, 586 HDMI_GC_CONT, 1, 587 HDMI_GC_SEND, 1, 588 HDMI_NULL_SEND, 1); 589 590 /* following belongs to audio */ 591 REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); 592 593 REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); 594 595 REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 596 VBI_LINE_0 + 2); 597 598 REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0); 599 } 600 601 /* setup stream encoder in dvi mode */ 602 void enc1_stream_encoder_dvi_set_stream_attribute( 603 struct stream_encoder *enc, 604 struct dc_crtc_timing *crtc_timing, 605 bool is_dual_link) 606 { 607 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 608 struct bp_encoder_control cntl = {0}; 609 610 cntl.action = ENCODER_CONTROL_SETUP; 611 cntl.engine_id = enc1->base.id; 612 cntl.signal = is_dual_link ? 613 SIGNAL_TYPE_DVI_DUAL_LINK : SIGNAL_TYPE_DVI_SINGLE_LINK; 614 cntl.enable_dp_audio = false; 615 cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10; 616 cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR; 617 618 if (enc1->base.bp->funcs->encoder_control( 619 enc1->base.bp, &cntl) != BP_RESULT_OK) 620 return; 621 622 ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB); 623 ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888); 624 enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing); 625 } 626 627 void enc1_stream_encoder_set_mst_bandwidth( 628 struct stream_encoder *enc, 629 struct fixed31_32 avg_time_slots_per_mtp) 630 { 631 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 632 uint32_t x = dc_fixpt_floor( 633 avg_time_slots_per_mtp); 634 uint32_t y = dc_fixpt_ceil( 635 dc_fixpt_shl( 636 dc_fixpt_sub_int( 637 avg_time_slots_per_mtp, 638 x), 639 26)); 640 641 REG_SET_2(DP_MSE_RATE_CNTL, 0, 642 DP_MSE_RATE_X, x, 643 DP_MSE_RATE_Y, y); 644 645 /* wait for update to be completed on the link */ 646 /* i.e. DP_MSE_RATE_UPDATE_PENDING field (read only) */ 647 /* is reset to 0 (not pending) */ 648 REG_WAIT(DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING, 649 0, 650 10, DP_MST_UPDATE_MAX_RETRY); 651 } 652 653 static void enc1_stream_encoder_update_hdmi_info_packets( 654 struct stream_encoder *enc, 655 const struct encoder_info_frame *info_frame) 656 { 657 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 658 659 /* for bring up, disable dp double TODO */ 660 REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1); 661 662 enc1_update_hdmi_info_packet(enc1, 0, &info_frame->avi); 663 enc1_update_hdmi_info_packet(enc1, 1, &info_frame->vendor); 664 enc1_update_hdmi_info_packet(enc1, 2, &info_frame->gamut); 665 enc1_update_hdmi_info_packet(enc1, 3, &info_frame->spd); 666 enc1_update_hdmi_info_packet(enc1, 4, &info_frame->hdrsmd); 667 } 668 669 static void enc1_stream_encoder_stop_hdmi_info_packets( 670 struct stream_encoder *enc) 671 { 672 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 673 674 /* stop generic packets 0 & 1 on HDMI */ 675 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL0, 0, 676 HDMI_GENERIC1_CONT, 0, 677 HDMI_GENERIC1_LINE, 0, 678 HDMI_GENERIC1_SEND, 0, 679 HDMI_GENERIC0_CONT, 0, 680 HDMI_GENERIC0_LINE, 0, 681 HDMI_GENERIC0_SEND, 0); 682 683 /* stop generic packets 2 & 3 on HDMI */ 684 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL1, 0, 685 HDMI_GENERIC0_CONT, 0, 686 HDMI_GENERIC0_LINE, 0, 687 HDMI_GENERIC0_SEND, 0, 688 HDMI_GENERIC1_CONT, 0, 689 HDMI_GENERIC1_LINE, 0, 690 HDMI_GENERIC1_SEND, 0); 691 692 /* stop generic packets 2 & 3 on HDMI */ 693 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL2, 0, 694 HDMI_GENERIC0_CONT, 0, 695 HDMI_GENERIC0_LINE, 0, 696 HDMI_GENERIC0_SEND, 0, 697 HDMI_GENERIC1_CONT, 0, 698 HDMI_GENERIC1_LINE, 0, 699 HDMI_GENERIC1_SEND, 0); 700 701 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL3, 0, 702 HDMI_GENERIC0_CONT, 0, 703 HDMI_GENERIC0_LINE, 0, 704 HDMI_GENERIC0_SEND, 0, 705 HDMI_GENERIC1_CONT, 0, 706 HDMI_GENERIC1_LINE, 0, 707 HDMI_GENERIC1_SEND, 0); 708 } 709 710 void enc1_stream_encoder_update_dp_info_packets( 711 struct stream_encoder *enc, 712 const struct encoder_info_frame *info_frame) 713 { 714 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 715 uint32_t value = 0; 716 717 if (info_frame->vsc.valid) 718 enc1_update_generic_info_packet( 719 enc1, 720 0, /* packetIndex */ 721 &info_frame->vsc); 722 723 if (info_frame->spd.valid) 724 enc1_update_generic_info_packet( 725 enc1, 726 2, /* packetIndex */ 727 &info_frame->spd); 728 729 if (info_frame->hdrsmd.valid) 730 enc1_update_generic_info_packet( 731 enc1, 732 3, /* packetIndex */ 733 &info_frame->hdrsmd); 734 735 /* packetIndex 4 is used for send immediate sdp message, and please 736 * use other packetIndex (such as 5,6) for other info packet 737 */ 738 739 /* enable/disable transmission of packet(s). 740 * If enabled, packet transmission begins on the next frame 741 */ 742 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid); 743 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid); 744 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid); 745 746 747 /* This bit is the master enable bit. 748 * When enabling secondary stream engine, 749 * this master bit must also be set. 750 * This register shared with audio info frame. 751 * Therefore we need to enable master bit 752 * if at least on of the fields is not 0 753 */ 754 value = REG_READ(DP_SEC_CNTL); 755 if (value) 756 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 757 } 758 759 void enc1_stream_encoder_send_immediate_sdp_message( 760 struct stream_encoder *enc, 761 const uint8_t *custom_sdp_message, 762 unsigned int sdp_message_size) 763 { 764 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 765 uint32_t value = 0; 766 767 /* TODOFPGA Figure out a proper number for max_retries polling for lock 768 * use 50 for now. 769 */ 770 uint32_t max_retries = 50; 771 772 /* check if GSP4 is transmitted */ 773 REG_WAIT(DP_SEC_CNTL2, DP_SEC_GSP4_SEND_PENDING, 774 0, 10, max_retries); 775 776 /* disable GSP4 transmitting */ 777 REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP4_SEND, 0); 778 779 /* transmit GSP4 at the earliest time in a frame */ 780 REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP4_SEND_ANY_LINE, 1); 781 782 /*we need turn on clock before programming AFMT block*/ 783 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1); 784 785 /* check if HW reading GSP memory */ 786 REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT, 787 0, 10, max_retries); 788 789 /* HW does is not reading GSP memory not reading too long -> 790 * something wrong. clear GPS memory access and notify? 791 * hw SW is writing to GSP memory 792 */ 793 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1); 794 795 /* use generic packet 4 for immediate sdp message */ 796 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, 797 AFMT_GENERIC_INDEX, 4); 798 799 /* write generic packet header 800 * (4th byte is for GENERIC0 only) 801 */ 802 REG_SET_4(AFMT_GENERIC_HDR, 0, 803 AFMT_GENERIC_HB0, custom_sdp_message[0], 804 AFMT_GENERIC_HB1, custom_sdp_message[1], 805 AFMT_GENERIC_HB2, custom_sdp_message[2], 806 AFMT_GENERIC_HB3, custom_sdp_message[3]); 807 808 /* write generic packet contents 809 * (we never use last 4 bytes) 810 * there are 8 (0-7) mmDIG0_AFMT_GENERIC0_x registers 811 */ 812 { 813 const uint32_t *content = 814 (const uint32_t *) &custom_sdp_message[4]; 815 816 REG_WRITE(AFMT_GENERIC_0, *content++); 817 REG_WRITE(AFMT_GENERIC_1, *content++); 818 REG_WRITE(AFMT_GENERIC_2, *content++); 819 REG_WRITE(AFMT_GENERIC_3, *content++); 820 REG_WRITE(AFMT_GENERIC_4, *content++); 821 REG_WRITE(AFMT_GENERIC_5, *content++); 822 REG_WRITE(AFMT_GENERIC_6, *content++); 823 REG_WRITE(AFMT_GENERIC_7, *content); 824 } 825 826 /* check whether GENERIC4 registers double buffer update in immediate mode 827 * is pending 828 */ 829 REG_WAIT(AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING, 830 0, 10, max_retries); 831 832 /* atomically update double-buffered GENERIC4 registers in immediate mode 833 * (update immediately) 834 */ 835 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 836 AFMT_GENERIC4_IMMEDIATE_UPDATE, 1); 837 838 /* enable GSP4 transmitting */ 839 REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP4_SEND, 1); 840 841 /* This bit is the master enable bit. 842 * When enabling secondary stream engine, 843 * this master bit must also be set. 844 * This register shared with audio info frame. 845 * Therefore we need to enable master bit 846 * if at least on of the fields is not 0 847 */ 848 value = REG_READ(DP_SEC_CNTL); 849 if (value) 850 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 851 } 852 853 void enc1_stream_encoder_stop_dp_info_packets( 854 struct stream_encoder *enc) 855 { 856 /* stop generic packets on DP */ 857 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 858 uint32_t value = 0; 859 860 REG_SET_10(DP_SEC_CNTL, 0, 861 DP_SEC_GSP0_ENABLE, 0, 862 DP_SEC_GSP1_ENABLE, 0, 863 DP_SEC_GSP2_ENABLE, 0, 864 DP_SEC_GSP3_ENABLE, 0, 865 DP_SEC_GSP4_ENABLE, 0, 866 DP_SEC_GSP5_ENABLE, 0, 867 DP_SEC_GSP6_ENABLE, 0, 868 DP_SEC_GSP7_ENABLE, 0, 869 DP_SEC_MPG_ENABLE, 0, 870 DP_SEC_STREAM_ENABLE, 0); 871 872 /* this register shared with audio info frame. 873 * therefore we need to keep master enabled 874 * if at least one of the fields is not 0 */ 875 value = REG_READ(DP_SEC_CNTL); 876 if (value) 877 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 878 879 } 880 881 void enc1_stream_encoder_dp_blank( 882 struct stream_encoder *enc) 883 { 884 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 885 uint32_t reg1 = 0; 886 uint32_t max_retries = DP_BLANK_MAX_RETRY * 10; 887 888 /* Note: For CZ, we are changing driver default to disable 889 * stream deferred to next VBLANK. If results are positive, we 890 * will make the same change to all DCE versions. There are a 891 * handful of panels that cannot handle disable stream at 892 * HBLANK and will result in a white line flash across the 893 * screen on stream disable. 894 */ 895 REG_GET(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, ®1); 896 if ((reg1 & 0x1) == 0) 897 /*stream not enabled*/ 898 return; 899 /* Specify the video stream disable point 900 * (2 = start of the next vertical blank) 901 */ 902 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2); 903 /* Larger delay to wait until VBLANK - use max retry of 904 * 10us*5000=50ms. This covers 41.7ms of minimum 24 Hz mode + 905 * a little more because we may not trust delay accuracy. 906 */ 907 max_retries = DP_BLANK_MAX_RETRY * 250; 908 909 /* disable DP stream */ 910 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0); 911 912 /* the encoder stops sending the video stream 913 * at the start of the vertical blanking. 914 * Poll for DP_VID_STREAM_STATUS == 0 915 */ 916 917 REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, 918 0, 919 10, max_retries); 920 921 /* Tell the DP encoder to ignore timing from CRTC, must be done after 922 * the polling. If we set DP_STEER_FIFO_RESET before DP stream blank is 923 * complete, stream status will be stuck in video stream enabled state, 924 * i.e. DP_VID_STREAM_STATUS stuck at 1. 925 */ 926 927 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, true); 928 } 929 930 /* output video stream to link encoder */ 931 void enc1_stream_encoder_dp_unblank( 932 struct stream_encoder *enc, 933 const struct encoder_unblank_param *param) 934 { 935 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 936 937 if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) { 938 uint32_t n_vid = 0x8000; 939 uint32_t m_vid; 940 uint32_t n_multiply = 0; 941 uint64_t m_vid_l = n_vid; 942 943 /* YCbCr 4:2:0 : Computed VID_M will be 2X the input rate */ 944 if (param->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) { 945 /*this param->pixel_clk_khz is half of 444 rate for 420 already*/ 946 n_multiply = 1; 947 } 948 /* M / N = Fstream / Flink 949 * m_vid / n_vid = pixel rate / link rate 950 */ 951 952 m_vid_l *= param->timing.pix_clk_100hz / 10; 953 m_vid_l = div_u64(m_vid_l, 954 param->link_settings.link_rate 955 * LINK_RATE_REF_FREQ_IN_KHZ); 956 957 m_vid = (uint32_t) m_vid_l; 958 959 /* enable auto measurement */ 960 961 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0); 962 963 /* auto measurement need 1 full 0x8000 symbol cycle to kick in, 964 * therefore program initial value for Mvid and Nvid 965 */ 966 967 REG_UPDATE(DP_VID_N, DP_VID_N, n_vid); 968 969 REG_UPDATE(DP_VID_M, DP_VID_M, m_vid); 970 971 REG_UPDATE_2(DP_VID_TIMING, 972 DP_VID_M_N_GEN_EN, 1, 973 DP_VID_N_MUL, n_multiply); 974 } 975 976 /* set DIG_START to 0x1 to resync FIFO */ 977 978 REG_UPDATE(DIG_FE_CNTL, DIG_START, 1); 979 980 /* switch DP encoder to CRTC data */ 981 982 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0); 983 984 /* wait 100us for DIG/DP logic to prime 985 * (i.e. a few video lines) 986 */ 987 udelay(100); 988 989 /* the hardware would start sending video at the start of the next DP 990 * frame (i.e. rising edge of the vblank). 991 * NOTE: We used to program DP_VID_STREAM_DIS_DEFER = 2 here, but this 992 * register has no effect on enable transition! HW always guarantees 993 * VID_STREAM enable at start of next frame, and this is not 994 * programmable 995 */ 996 997 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true); 998 } 999 1000 void enc1_stream_encoder_set_avmute( 1001 struct stream_encoder *enc, 1002 bool enable) 1003 { 1004 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 1005 unsigned int value = enable ? 1 : 0; 1006 1007 REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, value); 1008 } 1009 1010 void enc1_reset_hdmi_stream_attribute( 1011 struct stream_encoder *enc) 1012 { 1013 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 1014 1015 REG_UPDATE_5(HDMI_CONTROL, 1016 HDMI_PACKET_GEN_VERSION, 1, 1017 HDMI_KEEPOUT_MODE, 1, 1018 HDMI_DEEP_COLOR_ENABLE, 0, 1019 HDMI_DATA_SCRAMBLE_EN, 0, 1020 HDMI_CLOCK_CHANNEL_RATE, 0); 1021 } 1022 1023 1024 #define DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT 0x8000 1025 #define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC 1 1026 1027 #include "include/audio_types.h" 1028 1029 /** 1030 * speakersToChannels 1031 * 1032 * @brief 1033 * translate speakers to channels 1034 * 1035 * FL - Front Left 1036 * FR - Front Right 1037 * RL - Rear Left 1038 * RR - Rear Right 1039 * RC - Rear Center 1040 * FC - Front Center 1041 * FLC - Front Left Center 1042 * FRC - Front Right Center 1043 * RLC - Rear Left Center 1044 * RRC - Rear Right Center 1045 * LFE - Low Freq Effect 1046 * 1047 * FC 1048 * FLC FRC 1049 * FL FR 1050 * 1051 * LFE 1052 * () 1053 * 1054 * 1055 * RL RR 1056 * RLC RRC 1057 * RC 1058 * 1059 * ch 8 7 6 5 4 3 2 1 1060 * 0b00000011 - - - - - - FR FL 1061 * 0b00000111 - - - - - LFE FR FL 1062 * 0b00001011 - - - - FC - FR FL 1063 * 0b00001111 - - - - FC LFE FR FL 1064 * 0b00010011 - - - RC - - FR FL 1065 * 0b00010111 - - - RC - LFE FR FL 1066 * 0b00011011 - - - RC FC - FR FL 1067 * 0b00011111 - - - RC FC LFE FR FL 1068 * 0b00110011 - - RR RL - - FR FL 1069 * 0b00110111 - - RR RL - LFE FR FL 1070 * 0b00111011 - - RR RL FC - FR FL 1071 * 0b00111111 - - RR RL FC LFE FR FL 1072 * 0b01110011 - RC RR RL - - FR FL 1073 * 0b01110111 - RC RR RL - LFE FR FL 1074 * 0b01111011 - RC RR RL FC - FR FL 1075 * 0b01111111 - RC RR RL FC LFE FR FL 1076 * 0b11110011 RRC RLC RR RL - - FR FL 1077 * 0b11110111 RRC RLC RR RL - LFE FR FL 1078 * 0b11111011 RRC RLC RR RL FC - FR FL 1079 * 0b11111111 RRC RLC RR RL FC LFE FR FL 1080 * 0b11000011 FRC FLC - - - - FR FL 1081 * 0b11000111 FRC FLC - - - LFE FR FL 1082 * 0b11001011 FRC FLC - - FC - FR FL 1083 * 0b11001111 FRC FLC - - FC LFE FR FL 1084 * 0b11010011 FRC FLC - RC - - FR FL 1085 * 0b11010111 FRC FLC - RC - LFE FR FL 1086 * 0b11011011 FRC FLC - RC FC - FR FL 1087 * 0b11011111 FRC FLC - RC FC LFE FR FL 1088 * 0b11110011 FRC FLC RR RL - - FR FL 1089 * 0b11110111 FRC FLC RR RL - LFE FR FL 1090 * 0b11111011 FRC FLC RR RL FC - FR FL 1091 * 0b11111111 FRC FLC RR RL FC LFE FR FL 1092 * 1093 * @param 1094 * speakers - speaker information as it comes from CEA audio block 1095 */ 1096 /* translate speakers to channels */ 1097 1098 union audio_cea_channels { 1099 uint8_t all; 1100 struct audio_cea_channels_bits { 1101 uint32_t FL:1; 1102 uint32_t FR:1; 1103 uint32_t LFE:1; 1104 uint32_t FC:1; 1105 uint32_t RL_RC:1; 1106 uint32_t RR:1; 1107 uint32_t RC_RLC_FLC:1; 1108 uint32_t RRC_FRC:1; 1109 } channels; 1110 }; 1111 1112 /* 25.2MHz/1.001*/ 1113 /* 25.2MHz/1.001*/ 1114 /* 25.2MHz*/ 1115 /* 27MHz */ 1116 /* 27MHz*1.001*/ 1117 /* 27MHz*1.001*/ 1118 /* 54MHz*/ 1119 /* 54MHz*1.001*/ 1120 /* 74.25MHz/1.001*/ 1121 /* 74.25MHz*/ 1122 /* 148.5MHz/1.001*/ 1123 /* 148.5MHz*/ 1124 1125 static const struct audio_clock_info audio_clock_info_table[16] = { 1126 {2517, 4576, 28125, 7007, 31250, 6864, 28125}, 1127 {2518, 4576, 28125, 7007, 31250, 6864, 28125}, 1128 {2520, 4096, 25200, 6272, 28000, 6144, 25200}, 1129 {2700, 4096, 27000, 6272, 30000, 6144, 27000}, 1130 {2702, 4096, 27027, 6272, 30030, 6144, 27027}, 1131 {2703, 4096, 27027, 6272, 30030, 6144, 27027}, 1132 {5400, 4096, 54000, 6272, 60000, 6144, 54000}, 1133 {5405, 4096, 54054, 6272, 60060, 6144, 54054}, 1134 {7417, 11648, 210937, 17836, 234375, 11648, 140625}, 1135 {7425, 4096, 74250, 6272, 82500, 6144, 74250}, 1136 {14835, 11648, 421875, 8918, 234375, 5824, 140625}, 1137 {14850, 4096, 148500, 6272, 165000, 6144, 148500}, 1138 {29670, 5824, 421875, 4459, 234375, 5824, 281250}, 1139 {29700, 3072, 222750, 4704, 247500, 5120, 247500}, 1140 {59340, 5824, 843750, 8918, 937500, 5824, 562500}, 1141 {59400, 3072, 445500, 9408, 990000, 6144, 594000} 1142 }; 1143 1144 static const struct audio_clock_info audio_clock_info_table_36bpc[14] = { 1145 {2517, 9152, 84375, 7007, 48875, 9152, 56250}, 1146 {2518, 9152, 84375, 7007, 48875, 9152, 56250}, 1147 {2520, 4096, 37800, 6272, 42000, 6144, 37800}, 1148 {2700, 4096, 40500, 6272, 45000, 6144, 40500}, 1149 {2702, 8192, 81081, 6272, 45045, 8192, 54054}, 1150 {2703, 8192, 81081, 6272, 45045, 8192, 54054}, 1151 {5400, 4096, 81000, 6272, 90000, 6144, 81000}, 1152 {5405, 4096, 81081, 6272, 90090, 6144, 81081}, 1153 {7417, 11648, 316406, 17836, 351562, 11648, 210937}, 1154 {7425, 4096, 111375, 6272, 123750, 6144, 111375}, 1155 {14835, 11648, 632812, 17836, 703125, 11648, 421875}, 1156 {14850, 4096, 222750, 6272, 247500, 6144, 222750}, 1157 {29670, 5824, 632812, 8918, 703125, 5824, 421875}, 1158 {29700, 4096, 445500, 4704, 371250, 5120, 371250} 1159 }; 1160 1161 static const struct audio_clock_info audio_clock_info_table_48bpc[14] = { 1162 {2517, 4576, 56250, 7007, 62500, 6864, 56250}, 1163 {2518, 4576, 56250, 7007, 62500, 6864, 56250}, 1164 {2520, 4096, 50400, 6272, 56000, 6144, 50400}, 1165 {2700, 4096, 54000, 6272, 60000, 6144, 54000}, 1166 {2702, 4096, 54054, 6267, 60060, 8192, 54054}, 1167 {2703, 4096, 54054, 6272, 60060, 8192, 54054}, 1168 {5400, 4096, 108000, 6272, 120000, 6144, 108000}, 1169 {5405, 4096, 108108, 6272, 120120, 6144, 108108}, 1170 {7417, 11648, 421875, 17836, 468750, 11648, 281250}, 1171 {7425, 4096, 148500, 6272, 165000, 6144, 148500}, 1172 {14835, 11648, 843750, 8918, 468750, 11648, 281250}, 1173 {14850, 4096, 297000, 6272, 330000, 6144, 297000}, 1174 {29670, 5824, 843750, 4459, 468750, 5824, 562500}, 1175 {29700, 3072, 445500, 4704, 495000, 5120, 495000} 1176 1177 1178 }; 1179 1180 static union audio_cea_channels speakers_to_channels( 1181 struct audio_speaker_flags speaker_flags) 1182 { 1183 union audio_cea_channels cea_channels = {0}; 1184 1185 /* these are one to one */ 1186 cea_channels.channels.FL = speaker_flags.FL_FR; 1187 cea_channels.channels.FR = speaker_flags.FL_FR; 1188 cea_channels.channels.LFE = speaker_flags.LFE; 1189 cea_channels.channels.FC = speaker_flags.FC; 1190 1191 /* if Rear Left and Right exist move RC speaker to channel 7 1192 * otherwise to channel 5 1193 */ 1194 if (speaker_flags.RL_RR) { 1195 cea_channels.channels.RL_RC = speaker_flags.RL_RR; 1196 cea_channels.channels.RR = speaker_flags.RL_RR; 1197 cea_channels.channels.RC_RLC_FLC = speaker_flags.RC; 1198 } else { 1199 cea_channels.channels.RL_RC = speaker_flags.RC; 1200 } 1201 1202 /* FRONT Left Right Center and REAR Left Right Center are exclusive */ 1203 if (speaker_flags.FLC_FRC) { 1204 cea_channels.channels.RC_RLC_FLC = speaker_flags.FLC_FRC; 1205 cea_channels.channels.RRC_FRC = speaker_flags.FLC_FRC; 1206 } else { 1207 cea_channels.channels.RC_RLC_FLC = speaker_flags.RLC_RRC; 1208 cea_channels.channels.RRC_FRC = speaker_flags.RLC_RRC; 1209 } 1210 1211 return cea_channels; 1212 } 1213 1214 void get_audio_clock_info( 1215 enum dc_color_depth color_depth, 1216 uint32_t crtc_pixel_clock_100Hz, 1217 uint32_t actual_pixel_clock_100Hz, 1218 struct audio_clock_info *audio_clock_info) 1219 { 1220 const struct audio_clock_info *clock_info; 1221 uint32_t index; 1222 uint32_t crtc_pixel_clock_in_10khz = crtc_pixel_clock_100Hz / 100; 1223 uint32_t audio_array_size; 1224 1225 switch (color_depth) { 1226 case COLOR_DEPTH_161616: 1227 clock_info = audio_clock_info_table_48bpc; 1228 audio_array_size = ARRAY_SIZE( 1229 audio_clock_info_table_48bpc); 1230 break; 1231 case COLOR_DEPTH_121212: 1232 clock_info = audio_clock_info_table_36bpc; 1233 audio_array_size = ARRAY_SIZE( 1234 audio_clock_info_table_36bpc); 1235 break; 1236 default: 1237 clock_info = audio_clock_info_table; 1238 audio_array_size = ARRAY_SIZE( 1239 audio_clock_info_table); 1240 break; 1241 } 1242 1243 if (clock_info != NULL) { 1244 /* search for exact pixel clock in table */ 1245 for (index = 0; index < audio_array_size; index++) { 1246 if (clock_info[index].pixel_clock_in_10khz > 1247 crtc_pixel_clock_in_10khz) 1248 break; /* not match */ 1249 else if (clock_info[index].pixel_clock_in_10khz == 1250 crtc_pixel_clock_in_10khz) { 1251 /* match found */ 1252 *audio_clock_info = clock_info[index]; 1253 return; 1254 } 1255 } 1256 } 1257 1258 /* not found */ 1259 if (actual_pixel_clock_100Hz == 0) 1260 actual_pixel_clock_100Hz = crtc_pixel_clock_100Hz; 1261 1262 /* See HDMI spec the table entry under 1263 * pixel clock of "Other". */ 1264 audio_clock_info->pixel_clock_in_10khz = 1265 actual_pixel_clock_100Hz / 100; 1266 audio_clock_info->cts_32khz = actual_pixel_clock_100Hz / 10; 1267 audio_clock_info->cts_44khz = actual_pixel_clock_100Hz / 10; 1268 audio_clock_info->cts_48khz = actual_pixel_clock_100Hz / 10; 1269 1270 audio_clock_info->n_32khz = 4096; 1271 audio_clock_info->n_44khz = 6272; 1272 audio_clock_info->n_48khz = 6144; 1273 } 1274 1275 static void enc1_se_audio_setup( 1276 struct stream_encoder *enc, 1277 unsigned int az_inst, 1278 struct audio_info *audio_info) 1279 { 1280 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 1281 1282 uint32_t speakers __unused = 0; 1283 uint32_t channels = 0; 1284 1285 ASSERT(audio_info); 1286 if (audio_info == NULL) 1287 /* This should not happen.it does so we don't get BSOD*/ 1288 return; 1289 1290 speakers = audio_info->flags.info.ALLSPEAKERS; 1291 channels = speakers_to_channels(audio_info->flags.speaker_flags).all; 1292 1293 /* setup the audio stream source select (audio -> dig mapping) */ 1294 REG_SET(AFMT_AUDIO_SRC_CONTROL, 0, AFMT_AUDIO_SRC_SELECT, az_inst); 1295 1296 /* Channel allocation */ 1297 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, channels); 1298 } 1299 1300 static void enc1_se_setup_hdmi_audio( 1301 struct stream_encoder *enc, 1302 const struct audio_crtc_info *crtc_info) 1303 { 1304 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 1305 1306 struct audio_clock_info audio_clock_info = {0}; 1307 1308 /* HDMI_AUDIO_PACKET_CONTROL */ 1309 REG_UPDATE(HDMI_AUDIO_PACKET_CONTROL, 1310 HDMI_AUDIO_DELAY_EN, 1); 1311 1312 /* AFMT_AUDIO_PACKET_CONTROL */ 1313 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); 1314 1315 /* AFMT_AUDIO_PACKET_CONTROL2 */ 1316 REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2, 1317 AFMT_AUDIO_LAYOUT_OVRD, 0, 1318 AFMT_60958_OSF_OVRD, 0); 1319 1320 /* HDMI_ACR_PACKET_CONTROL */ 1321 REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL, 1322 HDMI_ACR_AUTO_SEND, 1, 1323 HDMI_ACR_SOURCE, 0, 1324 HDMI_ACR_AUDIO_PRIORITY, 0); 1325 1326 /* Program audio clock sample/regeneration parameters */ 1327 get_audio_clock_info(crtc_info->color_depth, 1328 crtc_info->requested_pixel_clock_100Hz, 1329 crtc_info->calculated_pixel_clock_100Hz, 1330 &audio_clock_info); 1331 DC_LOG_HW_AUDIO( 1332 "\n%s:Input::requested_pixel_clock_100Hz = %d" \ 1333 "calculated_pixel_clock_100Hz = %d \n", __func__, \ 1334 crtc_info->requested_pixel_clock_100Hz, \ 1335 crtc_info->calculated_pixel_clock_100Hz); 1336 1337 /* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */ 1338 REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz); 1339 1340 /* HDMI_ACR_32_1__HDMI_ACR_N_32_MASK */ 1341 REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz); 1342 1343 /* HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK */ 1344 REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz); 1345 1346 /* HDMI_ACR_44_1__HDMI_ACR_N_44_MASK */ 1347 REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz); 1348 1349 /* HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK */ 1350 REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz); 1351 1352 /* HDMI_ACR_48_1__HDMI_ACR_N_48_MASK */ 1353 REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz); 1354 1355 /* Video driver cannot know in advance which sample rate will 1356 * be used by HD Audio driver 1357 * HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE field is 1358 * programmed below in interruppt callback 1359 */ 1360 1361 /* AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK & 1362 * AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 1363 */ 1364 REG_UPDATE_2(AFMT_60958_0, 1365 AFMT_60958_CS_CHANNEL_NUMBER_L, 1, 1366 AFMT_60958_CS_CLOCK_ACCURACY, 0); 1367 1368 /* AFMT_60958_1 AFMT_60958_CS_CHALNNEL_NUMBER_R */ 1369 REG_UPDATE(AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2); 1370 1371 /* AFMT_60958_2 now keep this settings until 1372 * Programming guide comes out 1373 */ 1374 REG_UPDATE_6(AFMT_60958_2, 1375 AFMT_60958_CS_CHANNEL_NUMBER_2, 3, 1376 AFMT_60958_CS_CHANNEL_NUMBER_3, 4, 1377 AFMT_60958_CS_CHANNEL_NUMBER_4, 5, 1378 AFMT_60958_CS_CHANNEL_NUMBER_5, 6, 1379 AFMT_60958_CS_CHANNEL_NUMBER_6, 7, 1380 AFMT_60958_CS_CHANNEL_NUMBER_7, 8); 1381 } 1382 1383 static void enc1_se_setup_dp_audio( 1384 struct stream_encoder *enc) 1385 { 1386 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 1387 1388 /* --- DP Audio packet configurations --- */ 1389 1390 /* ATP Configuration */ 1391 REG_SET(DP_SEC_AUD_N, 0, 1392 DP_SEC_AUD_N, DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT); 1393 1394 /* Async/auto-calc timestamp mode */ 1395 REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE, 1396 DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC); 1397 1398 /* --- The following are the registers 1399 * copied from the SetupHDMI --- 1400 */ 1401 1402 /* AFMT_AUDIO_PACKET_CONTROL */ 1403 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); 1404 1405 /* AFMT_AUDIO_PACKET_CONTROL2 */ 1406 /* Program the ATP and AIP next */ 1407 REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2, 1408 AFMT_AUDIO_LAYOUT_OVRD, 0, 1409 AFMT_60958_OSF_OVRD, 0); 1410 1411 /* AFMT_INFOFRAME_CONTROL0 */ 1412 REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); 1413 1414 /* AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */ 1415 REG_UPDATE(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, 0); 1416 } 1417 1418 void enc1_se_enable_audio_clock( 1419 struct stream_encoder *enc, 1420 bool enable) 1421 { 1422 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 1423 1424 if (REG(AFMT_CNTL) == 0) 1425 return; /* DCE8/10 does not have this register */ 1426 1427 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, !!enable); 1428 1429 /* wait for AFMT clock to turn on, 1430 * expectation: this should complete in 1-2 reads 1431 * 1432 * REG_WAIT(AFMT_CNTL, AFMT_AUDIO_CLOCK_ON, !!enable, 1, 10); 1433 * 1434 * TODO: wait for clock_on does not work well. May need HW 1435 * program sequence. But audio seems work normally even without wait 1436 * for clock_on status change 1437 */ 1438 } 1439 1440 void enc1_se_enable_dp_audio( 1441 struct stream_encoder *enc) 1442 { 1443 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 1444 1445 /* Enable Audio packets */ 1446 REG_UPDATE(DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1); 1447 1448 /* Program the ATP and AIP next */ 1449 REG_UPDATE_2(DP_SEC_CNTL, 1450 DP_SEC_ATP_ENABLE, 1, 1451 DP_SEC_AIP_ENABLE, 1); 1452 1453 /* Program STREAM_ENABLE after all the other enables. */ 1454 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 1455 } 1456 1457 static void enc1_se_disable_dp_audio( 1458 struct stream_encoder *enc) 1459 { 1460 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 1461 uint32_t value = 0; 1462 1463 /* Disable Audio packets */ 1464 REG_UPDATE_5(DP_SEC_CNTL, 1465 DP_SEC_ASP_ENABLE, 0, 1466 DP_SEC_ATP_ENABLE, 0, 1467 DP_SEC_AIP_ENABLE, 0, 1468 DP_SEC_ACM_ENABLE, 0, 1469 DP_SEC_STREAM_ENABLE, 0); 1470 1471 /* This register shared with encoder info frame. Therefore we need to 1472 * keep master enabled if at least on of the fields is not 0 1473 */ 1474 value = REG_READ(DP_SEC_CNTL); 1475 if (value != 0) 1476 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 1477 1478 } 1479 1480 void enc1_se_audio_mute_control( 1481 struct stream_encoder *enc, 1482 bool mute) 1483 { 1484 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 1485 1486 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, !mute); 1487 } 1488 1489 void enc1_se_dp_audio_setup( 1490 struct stream_encoder *enc, 1491 unsigned int az_inst, 1492 struct audio_info *info) 1493 { 1494 enc1_se_audio_setup(enc, az_inst, info); 1495 } 1496 1497 void enc1_se_dp_audio_enable( 1498 struct stream_encoder *enc) 1499 { 1500 enc1_se_enable_audio_clock(enc, true); 1501 enc1_se_setup_dp_audio(enc); 1502 enc1_se_enable_dp_audio(enc); 1503 } 1504 1505 void enc1_se_dp_audio_disable( 1506 struct stream_encoder *enc) 1507 { 1508 enc1_se_disable_dp_audio(enc); 1509 enc1_se_enable_audio_clock(enc, false); 1510 } 1511 1512 void enc1_se_hdmi_audio_setup( 1513 struct stream_encoder *enc, 1514 unsigned int az_inst, 1515 struct audio_info *info, 1516 struct audio_crtc_info *audio_crtc_info) 1517 { 1518 enc1_se_enable_audio_clock(enc, true); 1519 enc1_se_setup_hdmi_audio(enc, audio_crtc_info); 1520 enc1_se_audio_setup(enc, az_inst, info); 1521 } 1522 1523 void enc1_se_hdmi_audio_disable( 1524 struct stream_encoder *enc) 1525 { 1526 enc1_se_enable_audio_clock(enc, false); 1527 } 1528 1529 1530 void enc1_setup_stereo_sync( 1531 struct stream_encoder *enc, 1532 int tg_inst, bool enable) 1533 { 1534 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 1535 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst); 1536 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, !enable); 1537 } 1538 1539 void enc1_dig_connect_to_otg( 1540 struct stream_encoder *enc, 1541 int tg_inst) 1542 { 1543 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 1544 1545 REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst); 1546 } 1547 1548 unsigned int enc1_dig_source_otg( 1549 struct stream_encoder *enc) 1550 { 1551 uint32_t tg_inst = 0; 1552 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 1553 1554 REG_GET(DIG_FE_CNTL, DIG_SOURCE_SELECT, &tg_inst); 1555 1556 return tg_inst; 1557 } 1558 1559 bool enc1_stream_encoder_dp_get_pixel_format( 1560 struct stream_encoder *enc, 1561 enum dc_pixel_encoding *encoding, 1562 enum dc_color_depth *depth) 1563 { 1564 uint32_t hw_encoding = 0; 1565 uint32_t hw_depth = 0; 1566 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 1567 1568 if (enc == NULL || 1569 encoding == NULL || 1570 depth == NULL) 1571 return false; 1572 1573 REG_GET_2(DP_PIXEL_FORMAT, 1574 DP_PIXEL_ENCODING, &hw_encoding, 1575 DP_COMPONENT_DEPTH, &hw_depth); 1576 1577 switch (hw_depth) { 1578 case DP_COMPONENT_PIXEL_DEPTH_6BPC: 1579 *depth = COLOR_DEPTH_666; 1580 break; 1581 case DP_COMPONENT_PIXEL_DEPTH_8BPC: 1582 *depth = COLOR_DEPTH_888; 1583 break; 1584 case DP_COMPONENT_PIXEL_DEPTH_10BPC: 1585 *depth = COLOR_DEPTH_101010; 1586 break; 1587 case DP_COMPONENT_PIXEL_DEPTH_12BPC: 1588 *depth = COLOR_DEPTH_121212; 1589 break; 1590 case DP_COMPONENT_PIXEL_DEPTH_16BPC: 1591 *depth = COLOR_DEPTH_161616; 1592 break; 1593 default: 1594 *depth = COLOR_DEPTH_UNDEFINED; 1595 break; 1596 } 1597 1598 switch (hw_encoding) { 1599 case DP_PIXEL_ENCODING_TYPE_RGB444: 1600 *encoding = PIXEL_ENCODING_RGB; 1601 break; 1602 case DP_PIXEL_ENCODING_TYPE_YCBCR422: 1603 *encoding = PIXEL_ENCODING_YCBCR422; 1604 break; 1605 case DP_PIXEL_ENCODING_TYPE_YCBCR444: 1606 case DP_PIXEL_ENCODING_TYPE_Y_ONLY: 1607 *encoding = PIXEL_ENCODING_YCBCR444; 1608 break; 1609 case DP_PIXEL_ENCODING_TYPE_YCBCR420: 1610 *encoding = PIXEL_ENCODING_YCBCR420; 1611 break; 1612 default: 1613 *encoding = PIXEL_ENCODING_UNDEFINED; 1614 break; 1615 } 1616 return true; 1617 } 1618 1619 static const struct stream_encoder_funcs dcn10_str_enc_funcs = { 1620 .dp_set_stream_attribute = 1621 enc1_stream_encoder_dp_set_stream_attribute, 1622 .hdmi_set_stream_attribute = 1623 enc1_stream_encoder_hdmi_set_stream_attribute, 1624 .dvi_set_stream_attribute = 1625 enc1_stream_encoder_dvi_set_stream_attribute, 1626 .set_mst_bandwidth = 1627 enc1_stream_encoder_set_mst_bandwidth, 1628 .update_hdmi_info_packets = 1629 enc1_stream_encoder_update_hdmi_info_packets, 1630 .stop_hdmi_info_packets = 1631 enc1_stream_encoder_stop_hdmi_info_packets, 1632 .update_dp_info_packets = 1633 enc1_stream_encoder_update_dp_info_packets, 1634 .send_immediate_sdp_message = 1635 enc1_stream_encoder_send_immediate_sdp_message, 1636 .stop_dp_info_packets = 1637 enc1_stream_encoder_stop_dp_info_packets, 1638 .dp_blank = 1639 enc1_stream_encoder_dp_blank, 1640 .dp_unblank = 1641 enc1_stream_encoder_dp_unblank, 1642 .audio_mute_control = enc1_se_audio_mute_control, 1643 1644 .dp_audio_setup = enc1_se_dp_audio_setup, 1645 .dp_audio_enable = enc1_se_dp_audio_enable, 1646 .dp_audio_disable = enc1_se_dp_audio_disable, 1647 1648 .hdmi_audio_setup = enc1_se_hdmi_audio_setup, 1649 .hdmi_audio_disable = enc1_se_hdmi_audio_disable, 1650 .setup_stereo_sync = enc1_setup_stereo_sync, 1651 .set_avmute = enc1_stream_encoder_set_avmute, 1652 .dig_connect_to_otg = enc1_dig_connect_to_otg, 1653 .hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute, 1654 .dig_source_otg = enc1_dig_source_otg, 1655 1656 .dp_get_pixel_format = enc1_stream_encoder_dp_get_pixel_format, 1657 }; 1658 1659 void dcn10_stream_encoder_construct( 1660 struct dcn10_stream_encoder *enc1, 1661 struct dc_context *ctx, 1662 struct dc_bios *bp, 1663 enum engine_id eng_id, 1664 const struct dcn10_stream_enc_registers *regs, 1665 const struct dcn10_stream_encoder_shift *se_shift, 1666 const struct dcn10_stream_encoder_mask *se_mask) 1667 { 1668 enc1->base.funcs = &dcn10_str_enc_funcs; 1669 enc1->base.ctx = ctx; 1670 enc1->base.id = eng_id; 1671 enc1->base.bp = bp; 1672 enc1->regs = regs; 1673 enc1->se_shift = se_shift; 1674 enc1->se_mask = se_mask; 1675 } 1676 1677
Indexes created Sun Sep 21 18:09:52 GMT 2025