1 /* $NetBSD: if_enet_imx.c,v 1.7 2022/12/27 18:55:06 mrg Exp $ */ 2 3 /*- 4 * Copyright (c) 2019 Genetec Corporation. All rights reserved. 5 * Written by Hashimoto Kenichi for Genetec Corporation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: if_enet_imx.c,v 1.7 2022/12/27 18:55:06 mrg Exp $"); 31 32 #include "opt_fdt.h" 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 38 #include <arm/imx/if_enetreg.h> 39 #include <arm/imx/if_enetvar.h> 40 41 #include <dev/fdt/fdtvar.h> 42 43 struct enet_fdt_softc { 44 struct enet_softc sc_enet; 45 46 struct fdtbus_gpio_pin *sc_pin_reset; 47 }; 48 49 CFATTACH_DECL_NEW(enet_fdt, sizeof(struct enet_fdt_softc), 50 enet_match, enet_attach, NULL, NULL); 51 52 static const struct device_compatible_entry compat_data[] = { 53 /* compatible imxtype */ 54 { .compat = "fsl,imx6q-fec", .value = 6 }, 55 { .compat = "fsl,imx6sx-fec", .value = 7 }, 56 DEVICE_COMPAT_EOL 57 }; 58 59 static int enet_init_clocks(struct enet_softc *); 60 static void enet_phy_reset(struct enet_fdt_softc *, const int); 61 static int enet_phy_id(struct enet_softc *, const int); 62 static void *enet_intr_establish(struct enet_softc *, int, u_int); 63 64 int 65 enet_match(device_t parent, cfdata_t cf, void *aux) 66 { 67 struct fdt_attach_args * const faa = aux; 68 69 return of_compatible_match(faa->faa_phandle, compat_data); 70 } 71 72 void 73 enet_attach(device_t parent, device_t self, void *aux) 74 { 75 struct enet_fdt_softc * const efsc = device_private(self); 76 struct enet_softc *sc = &efsc->sc_enet; 77 struct fdt_attach_args * const faa = aux; 78 prop_dictionary_t prop = device_properties(self); 79 const int phandle = faa->faa_phandle; 80 bus_space_tag_t bst = faa->faa_bst; 81 bus_space_handle_t bsh; 82 bus_addr_t addr; 83 bus_size_t size; 84 int error; 85 86 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 87 aprint_error(": couldn't get enet registers\n"); 88 return; 89 } 90 91 error = bus_space_map(bst, addr, size, 0, &bsh); 92 if (error) { 93 aprint_error(": couldn't map enet registers: %d\n", error); 94 return; 95 } 96 97 sc->sc_clk_ipg = fdtbus_clock_get(phandle, "ipg"); 98 if (sc->sc_clk_ipg == NULL) { 99 aprint_error(": couldn't get clock ipg\n"); 100 goto failure; 101 } 102 sc->sc_clk_enet = fdtbus_clock_get(phandle, "ahb"); 103 if (sc->sc_clk_enet == NULL) { 104 aprint_error(": couldn't get clock ahb\n"); 105 goto failure; 106 } 107 sc->sc_clk_enet_ref = fdtbus_clock_get(phandle, "ptp"); 108 if (sc->sc_clk_enet_ref == NULL) { 109 aprint_error(": couldn't get clock ptp\n"); 110 goto failure; 111 } 112 113 if (fdtbus_clock_enable(phandle, "enet_clk_ref", false) != 0) { 114 aprint_error(": couldn't enable clock enet_clk_ref\n"); 115 goto failure; 116 } 117 if (fdtbus_clock_enable(phandle, "enet_out", false) != 0) { 118 aprint_error(": couldn't enable clock enet_out\n"); 119 goto failure; 120 } 121 122 aprint_naive("\n"); 123 aprint_normal(": Gigabit Ethernet Controller\n"); 124 125 sc->sc_dev = self; 126 sc->sc_iot = bst; 127 sc->sc_ioh = bsh; 128 sc->sc_dmat = faa->faa_dmat; 129 130 sc->sc_imxtype = of_compatible_lookup(phandle, compat_data)->value; 131 sc->sc_unit = 0; 132 sc->sc_phyid = enet_phy_id(sc, phandle); 133 134 const char *phy_mode = fdtbus_get_string(phandle, "phy-mode"); 135 if (phy_mode == NULL) { 136 aprint_error(": missing 'phy-mode' property\n"); 137 goto failure; 138 } 139 140 if (strcmp(phy_mode, "rgmii-txid") == 0) { 141 prop_dictionary_set_bool(prop, "tx_internal_delay", true); 142 sc->sc_rgmii = 1; 143 } else if (strcmp(phy_mode, "rgmii-rxid") == 0) { 144 prop_dictionary_set_bool(prop, "rx_internal_delay", true); 145 sc->sc_rgmii = 1; 146 } else if (strcmp(phy_mode, "rgmii-id") == 0) { 147 prop_dictionary_set_bool(prop, "tx_internal_delay", true); 148 prop_dictionary_set_bool(prop, "rx_internal_delay", true); 149 sc->sc_rgmii = 1; 150 } else if (strcmp(phy_mode, "rgmii") == 0) { 151 sc->sc_rgmii = 1; 152 } else { 153 sc->sc_rgmii = 0; 154 } 155 156 sc->sc_ih = enet_intr_establish(sc, phandle, 0); 157 if (sc->sc_ih == NULL) 158 goto failure; 159 160 if (sc->sc_imxtype == 7) { 161 sc->sc_ih2 = enet_intr_establish(sc, phandle, 1); 162 sc->sc_ih3 = enet_intr_establish(sc, phandle, 2); 163 if (sc->sc_ih2 == NULL || sc->sc_ih3 == NULL) 164 goto failure; 165 } 166 167 enet_init_clocks(sc); 168 sc->sc_clock = clk_get_rate(sc->sc_clk_ipg); 169 170 enet_phy_reset(efsc, phandle); 171 172 if (enet_attach_common(self) != 0) 173 goto failure; 174 175 return; 176 177 failure: 178 bus_space_unmap(bst, bsh, size); 179 return; 180 } 181 182 static void * 183 enet_intr_establish(struct enet_softc *sc, int phandle, u_int index) 184 { 185 char intrstr[128]; 186 char xname[16]; 187 void *ih; 188 189 if (!fdtbus_intr_str(phandle, index, intrstr, sizeof(intrstr))) { 190 aprint_error_dev(sc->sc_dev, "failed to decode interrupt %d\n", 191 index); 192 return NULL; 193 } 194 195 snprintf(xname, sizeof(xname), "%s #%u", device_xname(sc->sc_dev), 196 index); 197 ih = fdtbus_intr_establish_xname(phandle, index, IPL_NET, 0, 198 enet_intr, sc, xname); 199 if (ih == NULL) { 200 aprint_error_dev(sc->sc_dev, "failed to establish interrupt on %s\n", 201 intrstr); 202 return NULL; 203 } 204 aprint_normal_dev(sc->sc_dev, "interrupting on %s\n", intrstr); 205 206 return ih; 207 } 208 209 static int 210 enet_init_clocks(struct enet_softc *sc) 211 { 212 int error; 213 214 error = clk_enable(sc->sc_clk_ipg); 215 if (error) { 216 aprint_error_dev(sc->sc_dev, "couldn't enable ipg: %d\n", error); 217 return error; 218 } 219 error = clk_enable(sc->sc_clk_enet); 220 if (error) { 221 aprint_error_dev(sc->sc_dev, "couldn't enable enet: %d\n", error); 222 return error; 223 } 224 error = clk_enable(sc->sc_clk_enet_ref); 225 if (error) { 226 aprint_error_dev(sc->sc_dev, "couldn't enable enet_ref: %d\n", error); 227 return error; 228 } 229 230 return 0; 231 } 232 233 static void 234 enet_phy_reset(struct enet_fdt_softc *sc, const int phandle) 235 { 236 u_int msec; 237 238 sc->sc_pin_reset = fdtbus_gpio_acquire(phandle, "phy-reset-gpios", GPIO_PIN_OUTPUT); 239 if (sc->sc_pin_reset == NULL) { 240 aprint_error_dev(sc->sc_enet.sc_dev, "couldn't find phy reset gpios\n"); 241 return; 242 } 243 244 if (of_getprop_uint32(phandle, "phy-reset-duration", &msec)) 245 msec = 1; 246 247 /* Reset */ 248 fdtbus_gpio_write(sc->sc_pin_reset, 1); 249 delay(msec * 1000); 250 fdtbus_gpio_write(sc->sc_pin_reset, 0); 251 252 /* Post delay */ 253 if (of_getprop_uint32(phandle, "phy-reset-post-delay", &msec)) 254 msec = 0; 255 256 delay(msec * 1000); 257 } 258 259 static int 260 enet_phy_id(struct enet_softc *sc, const int phandle) 261 { 262 int phy_phandle; 263 bus_addr_t addr; 264 265 phy_phandle = fdtbus_get_phandle(phandle, "phy-handle"); 266 if (phy_phandle == -1) 267 return MII_PHY_ANY; 268 269 if (fdtbus_get_reg(phy_phandle, 0, &addr, NULL) != 0) 270 return MII_PHY_ANY; 271 272 return (int)addr; 273 } 274
Indexes created Sun Sep 21 20:09:37 GMT 2025