| /src/sys/external/bsd/drm2/dist/drm/i915/gt/ |
| selftest_rc6.c | 116 struct intel_engine_cs *engine, **engines; local in function:randomised_engines
126 engines = kmalloc_array(n, sizeof(*engines), GFP_KERNEL);
127 if (!engines)
132 engines[n++] = engine;
134 i915_prandom_shuffle(engines, sizeof(*engines), n, prng);
137 return engines;
143 struct intel_engine_cs **engines; local in function:live_rc6_ctx_wa
152 engines = randomised_engines(gt, &prng, &count)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/nouveau/include/nvif/ |
| device.h | 16 u64 engines; member in struct:nvif_device::nvif_fifo_runlist
|
| /src/sys/external/bsd/drm2/dist/drm/i915/gem/ |
| i915_gem_context_types.h | 37 struct intel_context *engines[]; member in struct:i915_gem_engines
42 const struct i915_gem_engines *engines; member in struct:i915_gem_engines_iter
59 * @engines: User defined engines for this context
66 * engines.
79 struct i915_gem_engines __rcu *engines; member in struct:i915_gem_context
80 struct mutex engines_mutex; /* guards writes to engines */
|
| i915_gem_context.c | 254 if (!e->engines[count])
257 RCU_INIT_POINTER(e->engines[count]->gem_context, NULL);
258 intel_context_put(e->engines[count]);
280 e = kzalloc(struct_size(e, engines, I915_NUM_ENGINES), GFP_KERNEL);
292 GEM_BUG_ON(e->engines[engine->legacy_idx]);
302 e->engines[engine->legacy_idx] = ce;
318 free_engines(rcu_access_pointer(ctx->engines));
366 return rcu_dereference_protected(ctx->engines, true);
472 * Map the user's engine back to the actual engines; one virtual
473 * engine will be mapped to multiple engines, and using ctx->engine[
1482 struct i915_gem_engines *engines; member in struct:set_engines
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/nouveau/include/nvkm/engine/ |
| fifo.h | 22 u64 engines; member in struct:nvkm_fifo_chan
|
| /src/sys/external/bsd/drm2/dist/drm/i915/selftests/ |
| intel_memory_region.c | 309 struct i915_gem_engines *engines; local in function:igt_gpu_write
352 engines = i915_gem_context_lock_engines(ctx);
357 ce = engines->engines[order[i] % engines->num_engines];
|
| /src/sys/external/bsd/drm2/dist/drm/i915/gem/selftests/ |
| huge_pages.c | 1118 struct i915_gem_engines *engines; local in function:igt_write_huge
1154 * To keep things interesting when alternating between engines in our
1171 engines = i915_gem_context_lock_engines(ctx);
1178 ce = engines->engines[order[i] % engines->num_engines];
|
| i915_gem_context.c | 286 struct i915_gem_engines *engines; local in function:live_parallel_switch
296 * Check we can process switches on all engines simultaneously.
312 engines = i915_gem_context_lock_engines(ctx);
313 count = engines->num_engines;
322 m = 0; /* Use the first context as our template for the engines */
323 for_each_gem_engine(ce, engines, it) {
333 /* Clone the same set of engines into the other contexts */
1441 pr_info("Submitted %lu dwords (across %lu engines)\n",
1583 const u32 RCS_GPR0 = 0x2600; /* not all engines have their own GPR! */
1783 pr_info("Checked %lu scratch offsets across %lu engines\n"
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/i915/ |
| i915_gpu_error.c | 1693 intel_engine_mask_t engines; local in function:error_msg
1696 engines = 0;
1704 engines |= cs->engine->mask;
1709 INTEL_GEN(error->i915), engines,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/ |
| core_types.h | 172 struct dce_aux *engines[MAX_PIPES]; member in struct:resource_pool
|
| /src/sys/external/bsd/drm2/dist/include/uapi/drm/ |
| i915_drm.h | 114 * Different engines serve different roles, and there may be more than one
117 * operations to be performed on a certain subset of engines, or for providing
577 * value reports the support of context isolation for individual engines by
1005 * clients or engines (i.e. suballocating objects), the implicit tracking
1230 * conditions which prevent the report of which engines are busy from
1232 * object is idle, the result of the ioctl, that all engines are idle,
1245 * The high word (bits 16:31) are a bitmask of which engines classes
1246 * are currently reading from the object. Multiple engines may be
1253 * execution engines, e.g. multiple media engines, which ar
1713 struct i915_engine_class_instance engines[0]; member in struct:i915_context_engines_load_balance
1751 struct i915_engine_class_instance engines[0]; member in struct:i915_context_engines_bond
1768 struct i915_engine_class_instance engines[0]; member in struct:i915_context_param_engines
2229 struct drm_i915_engine_info engines[]; member in struct:drm_i915_query_engine_info
[all...] |
