1 /* $NetBSD: epgpio.c,v 1.8 2021/11/21 08:25:26 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2005 HAMAJIMA Katsuomi. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: epgpio.c,v 1.8 2021/11/21 08:25:26 skrll Exp $"); 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/device.h> 35 #include <sys/bus.h> 36 #include <machine/intr.h> 37 #include <sys/gpio.h> 38 #include <dev/gpio/gpiovar.h> 39 #include <arm/ep93xx/ep93xxvar.h> 40 #include <arm/ep93xx/epsocvar.h> 41 #include <arm/ep93xx/epgpioreg.h> 42 #include <arm/ep93xx/epgpiovar.h> 43 #include "opt_ep93xx_gpio_mask.h" 44 #include "gpio.h" 45 #include "locators.h" 46 47 #ifdef EPGPIO_DEBUG 48 int epgpio_debug = EPGPIO_DEBUG; 49 #define DPRINTFN(n,x) if (epgpio_debug>(n)) printf x; 50 #else 51 #define DPRINTFN(n,x) 52 #endif 53 54 #define EPGPIO_NPORTS 8 55 #define EPGPIO_NPINS 8 56 57 struct port_info { 58 struct epgpio_softc *sc; 59 int unit; 60 #if NGPIO > 0 61 struct gpio_chipset_tag gpio_chipset; 62 gpio_pin_t pins[EPGPIO_NPINS]; 63 int gpio_mask; 64 int gpio_npins; 65 #endif 66 bus_size_t pxdr; 67 bus_size_t pxddr; 68 bus_size_t xinten; 69 bus_size_t xinttype1; 70 bus_size_t xinttype2; 71 bus_size_t xeoi; 72 bus_size_t xdb; 73 }; 74 75 struct intr_req { 76 int irq; 77 int (*ih_func)(void *); 78 int (*ireq_func)(void *); 79 void *ireq_arg; 80 void *cookie; 81 }; 82 83 struct epgpio_softc { 84 bus_space_tag_t sc_iot; 85 bus_space_handle_t sc_ioh; 86 struct port_info sc_port[EPGPIO_NPORTS]; 87 struct intr_req sc_ireq_combine; 88 struct intr_req sc_ireq_f[EPGPIO_NPINS]; 89 }; 90 91 static int epgpio_match(device_t, cfdata_t, void *); 92 static void epgpio_attach(device_t, device_t, void *); 93 94 #if NGPIO > 0 95 static int epgpiobus_print(void *, const char *); 96 static int epgpio_pin_read(void *, int); 97 static void epgpio_pin_write(void *, int, int); 98 static void epgpio_pin_ctl(void *, int, int); 99 #endif 100 101 static int epgpio_search(device_t, cfdata_t, const int *, void *); 102 static int epgpio_print(void *, const char *); 103 104 static int epgpio_intr_combine(void* arg); 105 static int epgpio_intr_f(void* arg, int); 106 static int epgpio_intr_0(void* arg); 107 static int epgpio_intr_1(void* arg); 108 static int epgpio_intr_2(void* arg); 109 static int epgpio_intr_3(void* arg); 110 static int epgpio_intr_4(void* arg); 111 static int epgpio_intr_5(void* arg); 112 static int epgpio_intr_6(void* arg); 113 static int epgpio_intr_7(void* arg); 114 115 static void epgpio_bit_set(struct epgpio_softc *, bus_size_t, int); 116 static void epgpio_bit_clear(struct epgpio_softc *, bus_size_t, int); 117 118 CFATTACH_DECL_NEW(epgpio, sizeof(struct epgpio_softc), 119 epgpio_match, epgpio_attach, NULL, NULL); 120 121 static int 122 epgpio_match(device_t parent, cfdata_t match, void *aux) 123 { 124 return 2; 125 } 126 127 static void 128 epgpio_attach(device_t parent, device_t self, void *aux) 129 { 130 struct epgpio_softc *sc = device_private(self); 131 struct epsoc_attach_args *sa = aux; 132 struct port_info *pi; 133 #if NGPIO > 0 134 struct gpiobus_attach_args gba; 135 int dir, val; 136 int i, j, pin; 137 #endif 138 139 printf("\n"); 140 sc->sc_iot = sa->sa_iot; 141 142 if (bus_space_map(sa->sa_iot, sa->sa_addr, 143 sa->sa_size, 0, &sc->sc_ioh)){ 144 printf("%s: Cannot map registers", device_xname(self)); 145 return; 146 } 147 148 /* PORT A */ 149 pi = &sc->sc_port[0]; 150 pi->unit = 0; 151 pi->sc = sc; 152 pi->pxdr = EP93XX_GPIO_PADR; 153 pi->pxddr = EP93XX_GPIO_PADDR; 154 pi->xinten = EP93XX_GPIO_AIntEn; 155 pi->xinttype1 = EP93XX_GPIO_AIntType1; 156 pi->xinttype2 = EP93XX_GPIO_AIntType2; 157 pi->xeoi = EP93XX_GPIO_AEOI; 158 pi->xdb = EP93XX_GPIO_ADB; 159 #if NGPIO > 0 160 pi->gpio_mask = EPGPIO_PORT_A_MASK; 161 #endif 162 bus_space_write_4(sc->sc_iot, sc->sc_ioh, pi->xinten, 0); 163 /* PORT B */ 164 pi = &sc->sc_port[1]; 165 pi->unit = 1; 166 pi->sc = sc; 167 pi->pxdr = EP93XX_GPIO_PBDR; 168 pi->pxddr = EP93XX_GPIO_PBDDR; 169 pi->xinten = EP93XX_GPIO_BIntEn; 170 pi->xinttype1 = EP93XX_GPIO_BIntType1; 171 pi->xinttype2 = EP93XX_GPIO_BIntType2; 172 pi->xeoi = EP93XX_GPIO_BEOI; 173 pi->xdb = EP93XX_GPIO_BDB; 174 #if NGPIO > 0 175 pi->gpio_mask = EPGPIO_PORT_B_MASK; 176 #endif 177 bus_space_write_4(sc->sc_iot, sc->sc_ioh, pi->xinten, 0); 178 /* PORT C */ 179 pi = &sc->sc_port[2]; 180 pi->unit = 2; 181 pi->sc = sc; 182 pi->pxdr = EP93XX_GPIO_PCDR; 183 pi->pxddr = EP93XX_GPIO_PCDDR; 184 pi->xinten = pi->xinttype1 = pi->xinttype2 = pi->xeoi = pi->xdb = -1; 185 #if NGPIO > 0 186 pi->gpio_mask = EPGPIO_PORT_C_MASK; 187 #endif 188 /* PORT D */ 189 pi = &sc->sc_port[3]; 190 pi->unit = 3; 191 pi->sc = sc; 192 pi->pxdr = EP93XX_GPIO_PDDR; 193 pi->pxddr = EP93XX_GPIO_PDDDR; 194 pi->xinten = pi->xinttype1 = pi->xinttype2 = pi->xeoi = pi->xdb = -1; 195 #if NGPIO > 0 196 pi->gpio_mask = EPGPIO_PORT_D_MASK; 197 #endif 198 /* PORT E */ 199 pi = &sc->sc_port[4]; 200 pi->unit = 4; 201 pi->sc = sc; 202 pi->pxdr = EP93XX_GPIO_PEDR; 203 pi->pxddr = EP93XX_GPIO_PEDDR; 204 pi->xinten = pi->xinttype1 = pi->xinttype2 = pi->xeoi = pi->xdb = -1; 205 #if NGPIO > 0 206 pi->gpio_mask = EPGPIO_PORT_E_MASK; 207 #endif 208 /* PORT F */ 209 pi = &sc->sc_port[5]; 210 pi->unit = 5; 211 pi->sc = sc; 212 pi->pxdr = EP93XX_GPIO_PFDR; 213 pi->pxddr = EP93XX_GPIO_PFDDR; 214 pi->xinten = EP93XX_GPIO_FIntEn; 215 pi->xinttype1 = EP93XX_GPIO_FIntType1; 216 pi->xinttype2 = EP93XX_GPIO_FIntType2; 217 pi->xeoi = EP93XX_GPIO_FEOI; 218 pi->xdb = EP93XX_GPIO_FDB; 219 #if NGPIO > 0 220 pi->gpio_mask = EPGPIO_PORT_F_MASK; 221 #endif 222 bus_space_write_4(sc->sc_iot, sc->sc_ioh, pi->xinten, 0); 223 /* PORT G */ 224 pi = &sc->sc_port[6]; 225 pi->unit = 6; 226 pi->sc = sc; 227 pi->pxdr = EP93XX_GPIO_PGDR; 228 pi->pxddr = EP93XX_GPIO_PGDDR; 229 pi->xinten = pi->xinttype1 = pi->xinttype2 = pi->xeoi = pi->xdb = -1; 230 #if NGPIO > 0 231 pi->gpio_mask = EPGPIO_PORT_G_MASK; 232 #endif 233 /* PORT H */ 234 pi = &sc->sc_port[7]; 235 pi->unit = 7; 236 pi->sc = sc; 237 pi->pxdr = EP93XX_GPIO_PHDR; 238 pi->pxddr = EP93XX_GPIO_PHDDR; 239 pi->xinten = pi->xinttype1 = pi->xinttype2 = pi->xeoi = pi->xdb = -1; 240 #if NGPIO > 0 241 pi->gpio_mask = EPGPIO_PORT_H_MASK; 242 #endif 243 244 /* PORT A & B */ 245 sc->sc_ireq_combine.irq = EP93XX_GPIO_INTR; 246 sc->sc_ireq_combine.ih_func = epgpio_intr_combine; 247 /* PORT F */ 248 sc->sc_ireq_f[0].irq = EP93XX_GPIO0_INTR; 249 sc->sc_ireq_f[0].ih_func = epgpio_intr_0; 250 sc->sc_ireq_f[1].irq = EP93XX_GPIO1_INTR; 251 sc->sc_ireq_f[1].ih_func = epgpio_intr_1; 252 sc->sc_ireq_f[2].irq = EP93XX_GPIO2_INTR; 253 sc->sc_ireq_f[2].ih_func = epgpio_intr_2; 254 sc->sc_ireq_f[3].irq = EP93XX_GPIO3_INTR; 255 sc->sc_ireq_f[3].ih_func = epgpio_intr_3; 256 sc->sc_ireq_f[4].irq = EP93XX_GPIO4_INTR; 257 sc->sc_ireq_f[4].ih_func = epgpio_intr_4; 258 sc->sc_ireq_f[5].irq = EP93XX_GPIO5_INTR; 259 sc->sc_ireq_f[5].ih_func = epgpio_intr_5; 260 sc->sc_ireq_f[6].irq = EP93XX_GPIO6_INTR; 261 sc->sc_ireq_f[6].ih_func = epgpio_intr_6; 262 sc->sc_ireq_f[7].irq = EP93XX_GPIO7_INTR; 263 sc->sc_ireq_f[7].ih_func = epgpio_intr_7; 264 265 #if NGPIO > 0 266 /* initialize and attach gpio(4) */ 267 for (i = 0; i < EPGPIO_NPORTS; i++) { 268 pi = &sc->sc_port[i]; 269 /* 270 * If this port is completely disabled for gpio attachment, 271 * then skip it. 272 */ 273 if (pi->gpio_mask == 0x00) 274 continue; 275 276 dir = bus_space_read_4(sc->sc_iot, sc->sc_ioh, pi->pxddr) & 0xff; 277 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, pi->pxdr) & 0xff; 278 279 /* 280 * pin_num doesn't seem to be used for anything in the GPIO 281 * code. So we're going to use it to refer to the REAL pin 282 * on the port. Just to keep things straight below: 283 * 284 * pin - The pin number as seen by the GPIO code 285 * j - The ACTUAL pin on the port 286 */ 287 288 for (j = 0, pin = 0; j < EPGPIO_NPINS; j++) { 289 if (pi->gpio_mask & (1 << j)) { 290 pi->pins[pin].pin_num = j; 291 pi->pins[pin].pin_caps = (GPIO_PIN_INPUT 292 | GPIO_PIN_OUTPUT); 293 if((dir >> j) & 0x01) 294 pi->pins[pin].pin_flags = 295 GPIO_PIN_OUTPUT; 296 else 297 pi->pins[pin].pin_flags = 298 GPIO_PIN_INPUT; 299 if((val >> j) & 0x01) 300 pi->pins[pin].pin_state = GPIO_PIN_HIGH; 301 else 302 pi->pins[pin].pin_state = GPIO_PIN_LOW; 303 pin++; 304 } 305 } 306 pi->gpio_chipset.gp_cookie = pi; 307 pi->gpio_chipset.gp_pin_read = epgpio_pin_read; 308 pi->gpio_chipset.gp_pin_write = epgpio_pin_write; 309 pi->gpio_chipset.gp_pin_ctl = epgpio_pin_ctl; 310 gba.gba_gc = &pi->gpio_chipset; 311 gba.gba_pins = pi->pins; 312 gba.gba_npins = pin; 313 config_found(self, &gba, epgpiobus_print, 314 CFARGS(.iattr = "gpiobus")); 315 } 316 #endif 317 318 config_search(self, NULL, 319 CFARGS(.search = epgpio_search, 320 .iattr = "epgpio")); 321 } 322 323 #if NGPIO > 0 324 static int 325 epgpiobus_print(void *aux, const char *name) 326 { 327 struct gpiobus_attach_args *gba = aux; 328 struct port_info *pi = (struct port_info *)gba->gba_gc->gp_cookie; 329 330 gpiobus_print(aux, name); 331 aprint_normal(": port %c", pi->unit+'A'); 332 333 return (UNCONF); 334 } 335 #endif 336 337 338 static int 339 epgpio_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 340 { 341 struct epgpio_softc *sc = device_private(parent); 342 struct epgpio_attach_args ga; 343 344 ga.ga_gc = sc; 345 ga.ga_iot = sc->sc_iot; 346 ga.ga_port = cf->cf_loc[EPGPIOCF_PORT]; 347 ga.ga_bit1 = cf->cf_loc[EPGPIOCF_BIT1]; 348 ga.ga_bit2 = cf->cf_loc[EPGPIOCF_BIT2]; 349 350 if (config_probe(parent, cf, &ga)) 351 config_attach(parent, cf, &ga, epgpio_print, CFARGS_NONE); 352 353 return 0; 354 } 355 356 static int 357 epgpio_print(void *aux, const char *name) 358 { 359 struct epgpio_attach_args *ga = aux; 360 struct epgpio_softc *sc = ga->ga_gc; 361 362 aprint_normal(":"); 363 if (ga->ga_port > -1) 364 aprint_normal(" port %c", sc->sc_port[ga->ga_port].unit+'A'); 365 if (ga->ga_bit1 > -1) 366 aprint_normal(" bit1 %d", ga->ga_bit1); 367 if (ga->ga_bit2 > -1) 368 aprint_normal(" bit2 %d", ga->ga_bit2); 369 370 return (UNCONF); 371 } 372 373 int 374 epgpio_read(struct epgpio_softc *sc, epgpio_port port, int bit) 375 { 376 struct port_info *pi = &sc->sc_port[port]; 377 378 #if NGPIO > 0 379 pi->pins[bit].pin_caps = 0; 380 #endif 381 return (bus_space_read_4(sc->sc_iot, sc->sc_ioh, pi->pxdr) >> bit) & 1; 382 } 383 384 void 385 epgpio_set(struct epgpio_softc *sc, epgpio_port port, int bit) 386 { 387 struct port_info *pi = &sc->sc_port[port]; 388 389 #if NGPIO > 0 390 pi->pins[bit].pin_caps = 0; 391 #endif 392 epgpio_bit_set(sc, pi->pxdr, bit); 393 } 394 395 void 396 epgpio_clear(struct epgpio_softc *sc, epgpio_port port, int bit) 397 { 398 struct port_info *pi = &sc->sc_port[port]; 399 400 #if NGPIO > 0 401 pi->pins[bit].pin_caps = 0; 402 #endif 403 epgpio_bit_clear(sc, pi->pxdr, bit); 404 } 405 406 void 407 epgpio_in(struct epgpio_softc *sc, epgpio_port port, int bit) 408 { 409 struct port_info *pi = &sc->sc_port[port]; 410 411 #if NGPIO > 0 412 pi->pins[bit].pin_caps = 0; 413 #endif 414 epgpio_bit_clear(sc, pi->pxddr, bit); 415 } 416 417 void 418 epgpio_out(struct epgpio_softc *sc, epgpio_port port, int bit) 419 { 420 struct port_info *pi = &sc->sc_port[port]; 421 422 #if NGPIO > 0 423 pi->pins[bit].pin_caps = 0; 424 #endif 425 epgpio_bit_set(sc, pi->pxddr, bit); 426 } 427 428 void * 429 epgpio_intr_establish(struct epgpio_softc *sc, epgpio_port port, int bit, 430 int flag, int ipl, int (*ireq_func)(void *), void *arg) { 431 struct port_info *pi; 432 struct intr_req *intq; 433 434 DPRINTFN(1, ("epgpio_intr_establish: port=%d, bit=%d, flag=%#x\n",port,bit,flag)); 435 436 if (bit < 0 || bit >= EPGPIO_NPINS) 437 return 0; 438 439 switch (port) { 440 case PORT_A: 441 case PORT_B: 442 intq = &sc->sc_ireq_combine; 443 break; 444 case PORT_F: 445 intq = &sc->sc_ireq_f[bit]; 446 break; 447 default: 448 return 0; 449 }; 450 451 if (intq->ireq_func) 452 return 0; /* already used */ 453 454 intq->ireq_func = ireq_func; 455 intq->ireq_arg = arg; 456 457 pi = &sc->sc_port[port]; 458 epgpio_bit_clear(sc, pi->xinten, bit); 459 epgpio_in(sc, port, bit); 460 #if NGPIO > 0 461 pi->pins[bit].pin_caps = 0; 462 #endif 463 464 if (flag & EDGE_TRIGGER) 465 epgpio_bit_set(sc, pi->xinttype1, bit); 466 else /* LEVEL_SENSE */ 467 epgpio_bit_clear(sc, pi->xinttype1, bit); 468 if (flag & RISING_EDGE) /* or HIGH_LEVEL */ 469 epgpio_bit_set(sc, pi->xinttype2, bit); 470 else /* FALLING_EDGE or LOW_LEVEL */ 471 epgpio_bit_clear(sc, pi->xinttype2, bit); 472 if (flag & DEBOUNCE) 473 epgpio_bit_set(sc, pi->xdb, bit); 474 else 475 epgpio_bit_clear(sc, pi->xdb, bit); 476 477 if (!intq->cookie) 478 intq->cookie = ep93xx_intr_establish(intq->irq, ipl, 479 intq->ih_func, pi); 480 bus_space_write_4(sc->sc_iot, sc->sc_ioh, pi->xeoi, 1 << bit); 481 epgpio_bit_set(sc, pi->xinten, bit); 482 return intq->cookie; 483 } 484 485 void 486 epgpio_intr_disestablish(struct epgpio_softc *sc, epgpio_port port, int bit) 487 { 488 struct port_info *pi; 489 struct intr_req *intq; 490 491 DPRINTFN(1, ("epgpio_intr_disestablish: port=%d, bit=%d\n",port,bit)); 492 493 if (bit < 0 || bit >= EPGPIO_NPINS) 494 return; 495 496 switch (port) { 497 case PORT_A: 498 case PORT_B: 499 intq = &sc->sc_ireq_combine; 500 break; 501 case PORT_F: 502 intq = &sc->sc_ireq_f[bit]; 503 break; 504 default: 505 return; 506 }; 507 508 if (!intq->ireq_func) 509 return; 510 511 pi = &sc->sc_port[port]; 512 epgpio_bit_clear(sc, pi->xinten, bit); 513 intq->ireq_func = 0; 514 intq->ireq_arg = 0; 515 ep93xx_intr_disestablish(intq->cookie); 516 intq->cookie = 0; 517 } 518 519 static int 520 epgpio_intr_combine(void *arg) 521 { 522 struct port_info *pi = arg; 523 struct epgpio_softc *sc = pi->sc; 524 struct intr_req *intq = &sc->sc_ireq_combine; 525 int err = 0; 526 527 DPRINTFN(1, ("epgpio_intr_combine\n")); 528 529 if (intq->ireq_func) 530 err = (*intq->ireq_func)(intq->ireq_arg); 531 epgpio_bit_set(sc, pi->xeoi, 0xff); 532 return err; 533 } 534 535 static int 536 epgpio_intr_f(void *arg, int bit) 537 { 538 struct port_info *pi = arg; 539 struct epgpio_softc *sc = pi->sc; 540 struct intr_req *intq = &sc->sc_ireq_f[bit]; 541 int err = 0; 542 543 DPRINTFN(1, ("epgpio_intr_%d\n", bit)); 544 545 if (intq->ireq_func) 546 err = (*intq->ireq_func)(intq->ireq_arg); 547 epgpio_bit_set(sc, pi->xeoi, bit); 548 return err; 549 } 550 551 static int 552 epgpio_intr_0(void *arg) 553 { 554 return epgpio_intr_f(arg, 0); 555 } 556 557 static int 558 epgpio_intr_1(void *arg) 559 { 560 return epgpio_intr_f(arg, 1); 561 } 562 563 static int 564 epgpio_intr_2(void *arg) 565 { 566 return epgpio_intr_f(arg, 2); 567 } 568 569 static int 570 epgpio_intr_3(void *arg) 571 { 572 return epgpio_intr_f(arg, 3); 573 } 574 575 static int 576 epgpio_intr_4(void *arg) 577 { 578 return epgpio_intr_f(arg, 4); 579 } 580 581 static int 582 epgpio_intr_5(void *arg) 583 { 584 return epgpio_intr_f(arg, 5); 585 } 586 587 static int 588 epgpio_intr_6(void *arg) 589 { 590 return epgpio_intr_f(arg, 6); 591 } 592 593 static int 594 epgpio_intr_7(void *arg) 595 { 596 return epgpio_intr_f(arg, 7); 597 } 598 599 #if NGPIO > 0 600 static int 601 epgpio_pin_read(void *arg, int pin) 602 { 603 struct port_info *pi = arg; 604 struct epgpio_softc *sc = pi->sc; 605 606 pin %= pi->gpio_npins; 607 if (!pi->pins[pin].pin_caps) 608 return 0; /* EBUSY? */ 609 610 return (bus_space_read_4(sc->sc_iot, sc->sc_ioh, 611 pi->pxdr) >> pi->pins[pin].pin_num) & 1; 612 } 613 614 static void 615 epgpio_pin_write(void *arg, int pin, int val) 616 { 617 struct port_info *pi = arg; 618 struct epgpio_softc *sc = pi->sc; 619 620 pin %= pi->gpio_npins; 621 if (!pi->pins[pin].pin_caps) 622 return; 623 624 if (val) 625 epgpio_bit_set(sc, pi->pxdr, pi->pins[pin].pin_num); 626 else 627 epgpio_bit_clear(sc, pi->pxdr, pi->pins[pin].pin_num); 628 } 629 630 static void 631 epgpio_pin_ctl(void *arg, int pin, int flags) 632 { 633 struct port_info *pi = arg; 634 struct epgpio_softc *sc = pi->sc; 635 636 pin %= pi->gpio_npins; 637 if (!pi->pins[pin].pin_caps) 638 return; 639 640 if (flags & GPIO_PIN_INPUT) 641 epgpio_bit_clear(sc, pi->pxddr, pi->pins[pin].pin_num); 642 else if (flags & GPIO_PIN_OUTPUT) 643 epgpio_bit_set(sc, pi->pxddr, pi->pins[pin].pin_num); 644 } 645 #endif 646 647 static void 648 epgpio_bit_set(struct epgpio_softc *sc, bus_size_t reg, int bit) 649 { 650 int t = bus_space_read_4(sc->sc_iot, sc->sc_ioh, reg) & 0xff; 651 bus_space_write_4(sc->sc_iot, sc->sc_ioh, reg, t | (1 << bit)); 652 } 653 654 static void 655 epgpio_bit_clear(struct epgpio_softc *sc, bus_size_t reg, int bit) 656 { 657 int t = bus_space_read_4(sc->sc_iot, sc->sc_ioh, reg) & 0xff; 658 bus_space_write_4(sc->sc_iot, sc->sc_ioh, reg, t & ~(1 << bit)); 659 } 660
Indexes created Sat Sep 20 22:09:52 GMT 2025