1 /* $NetBSD: rtwphy.c,v 1.17 2019/11/10 21:16:35 chs Exp $ */ 2 /*- 3 * Copyright (c) 2004, 2005 David Young. All rights reserved. 4 * 5 * Programmed for NetBSD by David Young. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY 17 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 19 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David 20 * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 22 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 24 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 27 * OF SUCH DAMAGE. 28 */ 29 /* 30 * Control the Philips SA2400 RF front-end and the baseband processor 31 * built into the Realtek RTL8180. 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: rtwphy.c,v 1.17 2019/11/10 21:16:35 chs Exp $"); 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/types.h> 40 #include <sys/device.h> 41 42 #include <sys/bus.h> 43 44 #include <net/if.h> 45 #include <net/if_media.h> 46 #include <net/if_ether.h> 47 48 #include <net80211/ieee80211_netbsd.h> 49 #include <net80211/ieee80211_radiotap.h> 50 #include <net80211/ieee80211_var.h> 51 52 #include <dev/ic/rtwreg.h> 53 #include <dev/ic/max2820reg.h> 54 #include <dev/ic/sa2400reg.h> 55 #include <dev/ic/rtwvar.h> 56 #include <dev/ic/rtwphyio.h> 57 #include <dev/ic/rtwphy.h> 58 59 static int rtw_max2820_pwrstate(struct rtw_rf *, enum rtw_pwrstate); 60 static int rtw_sa2400_pwrstate(struct rtw_rf *, enum rtw_pwrstate); 61 62 #define GCT_WRITE(__gr, __addr, __val, __label) \ 63 do { \ 64 if (rtw_rfbus_write(&(__gr)->gr_bus, RTW_RFCHIPID_GCT, \ 65 (__addr), (__val)) == -1) \ 66 goto __label; \ 67 } while(0) 68 69 static int 70 rtw_bbp_preinit(struct rtw_regs *regs, u_int antatten0, int dflantb, 71 u_int freq) 72 { 73 u_int antatten = antatten0; 74 if (dflantb) 75 antatten |= RTW_BBP_ANTATTEN_DFLANTB; 76 if (freq == 2484) /* channel 14 */ 77 antatten |= RTW_BBP_ANTATTEN_CHAN14; 78 return rtw_bbp_write(regs, RTW_BBP_ANTATTEN, antatten); 79 } 80 81 static int 82 rtw_bbp_init(struct rtw_regs *regs, struct rtw_bbpset *bb, int antdiv, 83 int dflantb, uint8_t cs_threshold, u_int freq) 84 { 85 int rc; 86 uint32_t sys2, sys3; 87 88 sys2 = bb->bb_sys2; 89 if (antdiv) 90 sys2 |= RTW_BBP_SYS2_ANTDIV; 91 sys3 = bb->bb_sys3 | 92 __SHIFTIN(cs_threshold, RTW_BBP_SYS3_CSTHRESH_MASK); 93 94 #define RTW_BBP_WRITE_OR_RETURN(reg, val) \ 95 if ((rc = rtw_bbp_write(regs, reg, val)) != 0) \ 96 return rc; 97 98 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_SYS1, bb->bb_sys1); 99 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_TXAGC, bb->bb_txagc); 100 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_LNADET, bb->bb_lnadet); 101 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_IFAGCINI, bb->bb_ifagcini); 102 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_IFAGCLIMIT, bb->bb_ifagclimit); 103 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_IFAGCDET, bb->bb_ifagcdet); 104 105 if ((rc = rtw_bbp_preinit(regs, bb->bb_antatten, dflantb, freq)) != 0) 106 return rc; 107 108 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_TRL, bb->bb_trl); 109 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_SYS2, sys2); 110 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_SYS3, sys3); 111 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_CHESTLIM, bb->bb_chestlim); 112 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_CHSQLIM, bb->bb_chsqlim); 113 return 0; 114 } 115 116 static int 117 rtw_sa2400_txpower(struct rtw_rf *rf, uint8_t opaque_txpower) 118 { 119 struct rtw_sa2400 *sa = (struct rtw_sa2400 *)rf; 120 struct rtw_rfbus *bus = &sa->sa_bus; 121 122 return rtw_rfbus_write(bus, RTW_RFCHIPID_PHILIPS, SA2400_TX, 123 opaque_txpower); 124 } 125 126 /* make sure we're using the same settings as the reference driver */ 127 static void 128 verify_syna(u_int freq, uint32_t val) 129 { 130 #ifdef DIAGNOSTIC 131 uint32_t expected_val = ~val; 132 133 switch (freq) { 134 case 2412: 135 expected_val = 0x0000096c; /* ch 1 */ 136 break; 137 case 2417: 138 expected_val = 0x00080970; /* ch 2 */ 139 break; 140 case 2422: 141 expected_val = 0x00100974; /* ch 3 */ 142 break; 143 case 2427: 144 expected_val = 0x00180978; /* ch 4 */ 145 break; 146 case 2432: 147 expected_val = 0x00000980; /* ch 5 */ 148 break; 149 case 2437: 150 expected_val = 0x00080984; /* ch 6 */ 151 break; 152 case 2442: 153 expected_val = 0x00100988; /* ch 7 */ 154 break; 155 case 2447: 156 expected_val = 0x0018098c; /* ch 8 */ 157 break; 158 case 2452: 159 expected_val = 0x00000994; /* ch 9 */ 160 break; 161 case 2457: 162 expected_val = 0x00080998; /* ch 10 */ 163 break; 164 case 2462: 165 expected_val = 0x0010099c; /* ch 11 */ 166 break; 167 case 2467: 168 expected_val = 0x001809a0; /* ch 12 */ 169 break; 170 case 2472: 171 expected_val = 0x000009a8; /* ch 13 */ 172 break; 173 case 2484: 174 expected_val = 0x000009b4; /* ch 14 */ 175 break; 176 } 177 KASSERT(val == expected_val); 178 #endif 179 } 180 181 /* freq is in MHz */ 182 static int 183 rtw_sa2400_tune(struct rtw_rf *rf, u_int freq) 184 { 185 struct rtw_sa2400 *sa = (struct rtw_sa2400 *)rf; 186 struct rtw_rfbus *bus = &sa->sa_bus; 187 int rc; 188 uint32_t syna, synb, sync; 189 190 /* XO = 44MHz, R = 11, hence N is in units of XO / R = 4MHz. 191 * 192 * The channel spacing (5MHz) is not divisible by 4MHz, so 193 * we set the fractional part of N to compensate. 194 */ 195 int n = freq / 4, nf = (freq % 4) * 2; 196 197 syna = __SHIFTIN(nf, SA2400_SYNA_NF_MASK) | __SHIFTIN(n, SA2400_SYNA_N_MASK); 198 verify_syna(freq, syna); 199 200 /* Divide the 44MHz crystal down to 4MHz. Set the fractional 201 * compensation charge pump value to agree with the fractional 202 * modulus. 203 */ 204 synb = __SHIFTIN(11, SA2400_SYNB_R_MASK) | SA2400_SYNB_L_NORMAL | 205 SA2400_SYNB_ON | SA2400_SYNB_ONE | 206 __SHIFTIN(80, SA2400_SYNB_FC_MASK); /* agrees w/ SA2400_SYNA_FM = 0 */ 207 208 sync = SA2400_SYNC_CP_NORMAL; 209 210 if ((rc = rtw_rfbus_write(bus, RTW_RFCHIPID_PHILIPS, SA2400_SYNA, 211 syna)) != 0) 212 return rc; 213 if ((rc = rtw_rfbus_write(bus, RTW_RFCHIPID_PHILIPS, SA2400_SYNB, 214 synb)) != 0) 215 return rc; 216 if ((rc = rtw_rfbus_write(bus, RTW_RFCHIPID_PHILIPS, SA2400_SYNC, 217 sync)) != 0) 218 return rc; 219 return rtw_rfbus_write(bus, RTW_RFCHIPID_PHILIPS, SA2400_SYND, 0x0); 220 } 221 222 static int 223 rtw_sa2400_pwrstate(struct rtw_rf *rf, enum rtw_pwrstate power) 224 { 225 struct rtw_sa2400 *sa = (struct rtw_sa2400 *)rf; 226 struct rtw_rfbus *bus = &sa->sa_bus; 227 uint32_t opmode; 228 opmode = SA2400_OPMODE_DEFAULTS; 229 switch (power) { 230 case RTW_ON: 231 opmode |= SA2400_OPMODE_MODE_TXRX; 232 break; 233 case RTW_SLEEP: 234 opmode |= SA2400_OPMODE_MODE_WAIT; 235 break; 236 case RTW_OFF: 237 opmode |= SA2400_OPMODE_MODE_SLEEP; 238 break; 239 } 240 241 if (sa->sa_digphy) 242 opmode |= SA2400_OPMODE_DIGIN; 243 244 return rtw_rfbus_write(bus, RTW_RFCHIPID_PHILIPS, SA2400_OPMODE, 245 opmode); 246 } 247 248 static int 249 rtw_sa2400_manrx_init(struct rtw_sa2400 *sa) 250 { 251 uint32_t manrx; 252 253 /* XXX we are not supposed to be in RXMGC mode when we do 254 * this? 255 */ 256 manrx = SA2400_MANRX_AHSN; 257 manrx |= SA2400_MANRX_TEN; 258 manrx |= __SHIFTIN(1023, SA2400_MANRX_RXGAIN_MASK); 259 260 return rtw_rfbus_write(&sa->sa_bus, RTW_RFCHIPID_PHILIPS, SA2400_MANRX, 261 manrx); 262 } 263 264 static int 265 rtw_sa2400_vcocal_start(struct rtw_sa2400 *sa, int start) 266 { 267 uint32_t opmode; 268 269 opmode = SA2400_OPMODE_DEFAULTS; 270 if (start) 271 opmode |= SA2400_OPMODE_MODE_VCOCALIB; 272 else 273 opmode |= SA2400_OPMODE_MODE_SLEEP; 274 275 if (sa->sa_digphy) 276 opmode |= SA2400_OPMODE_DIGIN; 277 278 return rtw_rfbus_write(&sa->sa_bus, RTW_RFCHIPID_PHILIPS, SA2400_OPMODE, 279 opmode); 280 } 281 282 static int 283 rtw_sa2400_vco_calibration(struct rtw_sa2400 *sa) 284 { 285 int rc; 286 /* calibrate VCO */ 287 if ((rc = rtw_sa2400_vcocal_start(sa, 1)) != 0) 288 return rc; 289 DELAY(2200); /* 2.2 milliseconds */ 290 /* XXX superfluous: SA2400 automatically entered SLEEP mode. */ 291 return rtw_sa2400_vcocal_start(sa, 0); 292 } 293 294 static int 295 rtw_sa2400_filter_calibration(struct rtw_sa2400 *sa) 296 { 297 uint32_t opmode; 298 299 opmode = SA2400_OPMODE_DEFAULTS | SA2400_OPMODE_MODE_FCALIB; 300 if (sa->sa_digphy) 301 opmode |= SA2400_OPMODE_DIGIN; 302 303 return rtw_rfbus_write(&sa->sa_bus, RTW_RFCHIPID_PHILIPS, SA2400_OPMODE, 304 opmode); 305 } 306 307 static int 308 rtw_sa2400_dc_calibration(struct rtw_sa2400 *sa) 309 { 310 struct rtw_rf *rf = &sa->sa_rf; 311 int rc; 312 uint32_t dccal; 313 314 (*rf->rf_continuous_tx_cb)(rf->rf_continuous_tx_arg, 1); 315 316 dccal = SA2400_OPMODE_DEFAULTS | SA2400_OPMODE_MODE_TXRX; 317 318 rc = rtw_rfbus_write(&sa->sa_bus, RTW_RFCHIPID_PHILIPS, SA2400_OPMODE, 319 dccal); 320 if (rc != 0) 321 return rc; 322 323 DELAY(5); /* DCALIB after being in Tx mode for 5 324 * microseconds 325 */ 326 327 dccal &= ~SA2400_OPMODE_MODE_MASK; 328 dccal |= SA2400_OPMODE_MODE_DCALIB; 329 330 rc = rtw_rfbus_write(&sa->sa_bus, RTW_RFCHIPID_PHILIPS, SA2400_OPMODE, 331 dccal); 332 if (rc != 0) 333 return rc; 334 335 DELAY(20); /* calibration takes at most 20 microseconds */ 336 337 (*rf->rf_continuous_tx_cb)(rf->rf_continuous_tx_arg, 0); 338 339 return 0; 340 } 341 342 static int 343 rtw_sa2400_agc_init(struct rtw_sa2400 *sa) 344 { 345 uint32_t agc; 346 347 agc = __SHIFTIN(25, SA2400_AGC_MAXGAIN_MASK); 348 agc |= __SHIFTIN(7, SA2400_AGC_BBPDELAY_MASK); 349 agc |= __SHIFTIN(15, SA2400_AGC_LNADELAY_MASK); 350 agc |= __SHIFTIN(27, SA2400_AGC_RXONDELAY_MASK); 351 352 return rtw_rfbus_write(&sa->sa_bus, RTW_RFCHIPID_PHILIPS, SA2400_AGC, 353 agc); 354 } 355 356 static void 357 rtw_sa2400_destroy(struct rtw_rf *rf) 358 { 359 struct rtw_sa2400 *sa = (struct rtw_sa2400 *)rf; 360 memset(sa, 0, sizeof(*sa)); 361 free(sa, M_DEVBUF); 362 } 363 364 static int 365 rtw_sa2400_calibrate(struct rtw_rf *rf, u_int freq) 366 { 367 struct rtw_sa2400 *sa = (struct rtw_sa2400 *)rf; 368 int i, rc; 369 370 /* XXX reference driver calibrates VCO twice. Is it a bug? */ 371 for (i = 0; i < 2; i++) { 372 if ((rc = rtw_sa2400_vco_calibration(sa)) != 0) 373 return rc; 374 } 375 /* VCO calibration erases synthesizer registers, so re-tune */ 376 if ((rc = rtw_sa2400_tune(rf, freq)) != 0) 377 return rc; 378 if ((rc = rtw_sa2400_filter_calibration(sa)) != 0) 379 return rc; 380 /* analog PHY needs DC calibration */ 381 if (!sa->sa_digphy) 382 return rtw_sa2400_dc_calibration(sa); 383 return 0; 384 } 385 386 static int 387 rtw_sa2400_init(struct rtw_rf *rf, u_int freq, uint8_t opaque_txpower, 388 enum rtw_pwrstate power) 389 { 390 struct rtw_sa2400 *sa = (struct rtw_sa2400 *)rf; 391 int rc; 392 393 if ((rc = rtw_sa2400_txpower(rf, opaque_txpower)) != 0) 394 return rc; 395 396 /* skip configuration if it's time to sleep or to power-down. */ 397 if (power == RTW_SLEEP || power == RTW_OFF) 398 return rtw_sa2400_pwrstate(rf, power); 399 400 /* go to sleep for configuration */ 401 if ((rc = rtw_sa2400_pwrstate(rf, RTW_SLEEP)) != 0) 402 return rc; 403 404 if ((rc = rtw_sa2400_tune(rf, freq)) != 0) 405 return rc; 406 if ((rc = rtw_sa2400_agc_init(sa)) != 0) 407 return rc; 408 if ((rc = rtw_sa2400_manrx_init(sa)) != 0) 409 return rc; 410 if ((rc = rtw_sa2400_calibrate(rf, freq)) != 0) 411 return rc; 412 413 /* enter Tx/Rx mode */ 414 return rtw_sa2400_pwrstate(rf, power); 415 } 416 417 struct rtw_rf * 418 rtw_sa2400_create(struct rtw_regs *regs, rtw_rf_write_t rf_write, int digphy) 419 { 420 struct rtw_sa2400 *sa; 421 struct rtw_rfbus *bus; 422 struct rtw_rf *rf; 423 struct rtw_bbpset *bb; 424 425 sa = malloc(sizeof(*sa), M_DEVBUF, M_WAITOK | M_ZERO); 426 sa->sa_digphy = digphy; 427 428 rf = &sa->sa_rf; 429 bus = &sa->sa_bus; 430 431 rf->rf_init = rtw_sa2400_init; 432 rf->rf_destroy = rtw_sa2400_destroy; 433 rf->rf_txpower = rtw_sa2400_txpower; 434 rf->rf_tune = rtw_sa2400_tune; 435 rf->rf_pwrstate = rtw_sa2400_pwrstate; 436 bb = &rf->rf_bbpset; 437 438 /* XXX magic */ 439 bb->bb_antatten = RTW_BBP_ANTATTEN_PHILIPS_MAGIC; 440 bb->bb_chestlim = 0x00; 441 bb->bb_chsqlim = 0xa0; 442 bb->bb_ifagcdet = 0x64; 443 bb->bb_ifagcini = 0x90; 444 bb->bb_ifagclimit = 0x1a; 445 bb->bb_lnadet = 0xe0; 446 bb->bb_sys1 = 0x98; 447 bb->bb_sys2 = 0x47; 448 bb->bb_sys3 = 0x90; 449 bb->bb_trl = 0x88; 450 bb->bb_txagc = 0x38; 451 452 bus->b_regs = regs; 453 bus->b_write = rf_write; 454 455 return &sa->sa_rf; 456 } 457 458 static int 459 rtw_grf5101_txpower(struct rtw_rf *rf, uint8_t opaque_txpower) 460 { 461 struct rtw_grf5101 *gr = (struct rtw_grf5101 *)rf; 462 463 GCT_WRITE(gr, 0x15, 0, err); 464 GCT_WRITE(gr, 0x06, opaque_txpower, err); 465 GCT_WRITE(gr, 0x15, 0x10, err); 466 GCT_WRITE(gr, 0x15, 0x00, err); 467 return 0; 468 err: 469 return -1; 470 } 471 472 static int 473 rtw_grf5101_pwrstate(struct rtw_rf *rf, enum rtw_pwrstate power) 474 { 475 struct rtw_grf5101 *gr = (struct rtw_grf5101 *)rf; 476 switch (power) { 477 case RTW_OFF: 478 case RTW_SLEEP: 479 GCT_WRITE(gr, 0x07, 0x0000, err); 480 GCT_WRITE(gr, 0x1f, 0x0045, err); 481 GCT_WRITE(gr, 0x1f, 0x0005, err); 482 GCT_WRITE(gr, 0x00, 0x08e4, err); 483 default: 484 break; 485 case RTW_ON: 486 GCT_WRITE(gr, 0x1f, 0x0001, err); 487 DELAY(10); 488 GCT_WRITE(gr, 0x1f, 0x0001, err); 489 DELAY(10); 490 GCT_WRITE(gr, 0x1f, 0x0041, err); 491 DELAY(10); 492 GCT_WRITE(gr, 0x1f, 0x0061, err); 493 DELAY(10); 494 GCT_WRITE(gr, 0x00, 0x0ae4, err); 495 DELAY(10); 496 GCT_WRITE(gr, 0x07, 0x1000, err); 497 DELAY(100); 498 break; 499 } 500 501 return 0; 502 err: 503 return -1; 504 } 505 506 static int 507 rtw_grf5101_tune(struct rtw_rf *rf, u_int freq) 508 { 509 int channel; 510 struct rtw_grf5101 *gr = (struct rtw_grf5101 *)rf; 511 512 if (freq == 2484) 513 channel = 14; 514 else if ((channel = (freq - 2412) / 5 + 1) < 1 || channel > 13) { 515 RTW_DPRINTF(RTW_DEBUG_PHY, 516 ("%s: invalid channel %d (freq %d)\n", __func__, channel, 517 freq)); 518 return -1; 519 } 520 521 GCT_WRITE(gr, 0x07, 0, err); 522 GCT_WRITE(gr, 0x0b, channel - 1, err); 523 GCT_WRITE(gr, 0x07, 0x1000, err); 524 return 0; 525 err: 526 return -1; 527 } 528 529 static int 530 rtw_grf5101_init(struct rtw_rf *rf, u_int freq, uint8_t opaque_txpower, 531 enum rtw_pwrstate power) 532 { 533 int rc; 534 struct rtw_grf5101 *gr = (struct rtw_grf5101 *)rf; 535 536 /* 537 * These values have been derived from the rtl8180-sa2400 538 * Linux driver. It is unknown what they all do, GCT refuse 539 * to release any documentation so these are more than 540 * likely sub optimal settings 541 */ 542 543 GCT_WRITE(gr, 0x01, 0x1a23, err); 544 GCT_WRITE(gr, 0x02, 0x4971, err); 545 GCT_WRITE(gr, 0x03, 0x41de, err); 546 GCT_WRITE(gr, 0x04, 0x2d80, err); 547 548 GCT_WRITE(gr, 0x05, 0x61ff, err); 549 550 GCT_WRITE(gr, 0x06, 0x0, err); 551 552 GCT_WRITE(gr, 0x08, 0x7533, err); 553 GCT_WRITE(gr, 0x09, 0xc401, err); 554 GCT_WRITE(gr, 0x0a, 0x0, err); 555 GCT_WRITE(gr, 0x0c, 0x1c7, err); 556 GCT_WRITE(gr, 0x0d, 0x29d3, err); 557 GCT_WRITE(gr, 0x0e, 0x2e8, err); 558 GCT_WRITE(gr, 0x10, 0x192, err); 559 GCT_WRITE(gr, 0x11, 0x248, err); 560 GCT_WRITE(gr, 0x12, 0x0, err); 561 GCT_WRITE(gr, 0x13, 0x20c4, err); 562 GCT_WRITE(gr, 0x14, 0xf4fc, err); 563 GCT_WRITE(gr, 0x15, 0x0, err); 564 GCT_WRITE(gr, 0x16, 0x1500, err); 565 566 if ((rc = rtw_grf5101_txpower(rf, opaque_txpower)) != 0) 567 return rc; 568 569 if ((rc = rtw_grf5101_tune(rf, freq)) != 0) 570 return rc; 571 572 return 0; 573 err: 574 return -1; 575 } 576 577 static void 578 rtw_grf5101_destroy(struct rtw_rf *rf) 579 { 580 struct rtw_grf5101 *gr = (struct rtw_grf5101 *)rf; 581 memset(gr, 0, sizeof(*gr)); 582 free(gr, M_DEVBUF); 583 } 584 585 struct rtw_rf * 586 rtw_grf5101_create(struct rtw_regs *regs, rtw_rf_write_t rf_write, 587 int digphy) 588 { 589 struct rtw_grf5101 *gr; 590 struct rtw_rfbus *bus; 591 struct rtw_rf *rf; 592 struct rtw_bbpset *bb; 593 594 gr = malloc(sizeof(*gr), M_DEVBUF, M_WAITOK | M_ZERO); 595 596 rf = &gr->gr_rf; 597 bus = &gr->gr_bus; 598 599 rf->rf_init = rtw_grf5101_init; 600 rf->rf_destroy = rtw_grf5101_destroy; 601 rf->rf_txpower = rtw_grf5101_txpower; 602 rf->rf_tune = rtw_grf5101_tune; 603 rf->rf_pwrstate = rtw_grf5101_pwrstate; 604 bb = &rf->rf_bbpset; 605 606 /* XXX magic */ 607 bb->bb_antatten = RTW_BBP_ANTATTEN_GCT_MAGIC; 608 bb->bb_chestlim = 0x00; 609 bb->bb_chsqlim = 0xa0; 610 bb->bb_ifagcdet = 0x64; 611 bb->bb_ifagcini = 0x90; 612 bb->bb_ifagclimit = 0x1e; 613 bb->bb_lnadet = 0xc0; 614 bb->bb_sys1 = 0xa8; 615 bb->bb_sys2 = 0x47; 616 bb->bb_sys3 = 0x9b; 617 bb->bb_trl = 0x88; 618 bb->bb_txagc = 0x08; 619 620 bus->b_regs = regs; 621 bus->b_write = rf_write; 622 623 return &gr->gr_rf; 624 } 625 626 /* freq is in MHz */ 627 static int 628 rtw_max2820_tune(struct rtw_rf *rf, u_int freq) 629 { 630 struct rtw_max2820 *mx = (struct rtw_max2820 *)rf; 631 struct rtw_rfbus *bus = &mx->mx_bus; 632 633 if (freq < 2400 || freq > 2499) 634 return -1; 635 636 return rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_CHANNEL, 637 __SHIFTIN(freq - 2400, MAX2820_CHANNEL_CF_MASK)); 638 } 639 640 static void 641 rtw_max2820_destroy(struct rtw_rf *rf) 642 { 643 struct rtw_max2820 *mx = (struct rtw_max2820 *)rf; 644 memset(mx, 0, sizeof(*mx)); 645 free(mx, M_DEVBUF); 646 } 647 648 static int 649 rtw_max2820_init(struct rtw_rf *rf, u_int freq, uint8_t opaque_txpower, 650 enum rtw_pwrstate power) 651 { 652 struct rtw_max2820 *mx = (struct rtw_max2820 *)rf; 653 struct rtw_rfbus *bus = &mx->mx_bus; 654 int rc; 655 656 if ((rc = rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_TEST, 657 MAX2820_TEST_DEFAULT)) != 0) 658 return rc; 659 660 if ((rc = rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_ENABLE, 661 MAX2820_ENABLE_DEFAULT)) != 0) 662 return rc; 663 664 /* skip configuration if it's time to sleep or to power-down. */ 665 if ((rc = rtw_max2820_pwrstate(rf, power)) != 0) 666 return rc; 667 else if (power == RTW_OFF || power == RTW_SLEEP) 668 return 0; 669 670 if ((rc = rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_SYNTH, 671 MAX2820_SYNTH_R_44MHZ)) != 0) 672 return rc; 673 674 if ((rc = rtw_max2820_tune(rf, freq)) != 0) 675 return rc; 676 677 /* XXX The MAX2820 datasheet indicates that 1C and 2C should not 678 * be changed from 7, however, the reference driver sets them 679 * to 4 and 1, respectively. 680 */ 681 if ((rc = rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_RECEIVE, 682 MAX2820_RECEIVE_DL_DEFAULT | 683 __SHIFTIN(4, MAX2820A_RECEIVE_1C_MASK) | 684 __SHIFTIN(1, MAX2820A_RECEIVE_2C_MASK))) != 0) 685 return rc; 686 687 return rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_TRANSMIT, 688 MAX2820_TRANSMIT_PA_DEFAULT); 689 } 690 691 static int 692 rtw_max2820_txpower(struct rtw_rf *rf, uint8_t opaque_txpower) 693 { 694 /* TBD */ 695 return 0; 696 } 697 698 static int 699 rtw_max2820_pwrstate(struct rtw_rf *rf, enum rtw_pwrstate power) 700 { 701 uint32_t enable; 702 struct rtw_max2820 *mx; 703 struct rtw_rfbus *bus; 704 705 mx = (struct rtw_max2820 *)rf; 706 bus = &mx->mx_bus; 707 708 switch (power) { 709 case RTW_OFF: 710 case RTW_SLEEP: 711 default: 712 enable = 0x0; 713 break; 714 case RTW_ON: 715 enable = MAX2820_ENABLE_DEFAULT; 716 break; 717 } 718 return rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_ENABLE, enable); 719 } 720 721 struct rtw_rf * 722 rtw_max2820_create(struct rtw_regs *regs, rtw_rf_write_t rf_write, int is_a) 723 { 724 struct rtw_max2820 *mx; 725 struct rtw_rfbus *bus; 726 struct rtw_rf *rf; 727 struct rtw_bbpset *bb; 728 729 mx = malloc(sizeof(*mx), M_DEVBUF, M_WAITOK | M_ZERO); 730 mx->mx_is_a = is_a; 731 732 rf = &mx->mx_rf; 733 bus = &mx->mx_bus; 734 735 rf->rf_init = rtw_max2820_init; 736 rf->rf_destroy = rtw_max2820_destroy; 737 rf->rf_txpower = rtw_max2820_txpower; 738 rf->rf_tune = rtw_max2820_tune; 739 rf->rf_pwrstate = rtw_max2820_pwrstate; 740 bb = &rf->rf_bbpset; 741 742 /* XXX magic */ 743 bb->bb_antatten = RTW_BBP_ANTATTEN_MAXIM_MAGIC; 744 bb->bb_chestlim = 0; 745 bb->bb_chsqlim = 159; 746 bb->bb_ifagcdet = 100; 747 bb->bb_ifagcini = 144; 748 bb->bb_ifagclimit = 26; 749 bb->bb_lnadet = 248; 750 bb->bb_sys1 = 136; 751 bb->bb_sys2 = 71; 752 bb->bb_sys3 = 155; 753 bb->bb_trl = 136; 754 bb->bb_txagc = 8; 755 756 bus->b_regs = regs; 757 bus->b_write = rf_write; 758 759 return &mx->mx_rf; 760 } 761 762 /* freq is in MHz */ 763 int 764 rtw_phy_init(struct rtw_regs *regs, struct rtw_rf *rf, uint8_t opaque_txpower, 765 uint8_t cs_threshold, u_int freq, int antdiv, int dflantb, 766 enum rtw_pwrstate power) 767 { 768 int rc; 769 RTW_DPRINTF(RTW_DEBUG_PHY, 770 ("%s: txpower %u csthresh %u freq %u antdiv %u dflantb %u " 771 "pwrstate %s\n", __func__, opaque_txpower, cs_threshold, freq, 772 antdiv, dflantb, rtw_pwrstate_string(power))); 773 774 /* XXX is this really necessary? */ 775 if ((rc = rtw_rf_txpower(rf, opaque_txpower)) != 0) 776 return rc; 777 if ((rc = rtw_bbp_preinit(regs, rf->rf_bbpset.bb_antatten, dflantb, 778 freq)) != 0) 779 return rc; 780 if ((rc = rtw_rf_tune(rf, freq)) != 0) 781 return rc; 782 /* initialize RF */ 783 if ((rc = rtw_rf_init(rf, freq, opaque_txpower, power)) != 0) 784 return rc; 785 #if 0 /* what is this redundant tx power setting here for? */ 786 if ((rc = rtw_rf_txpower(rf, opaque_txpower)) != 0) 787 return rc; 788 #endif 789 return rtw_bbp_init(regs, &rf->rf_bbpset, antdiv, dflantb, 790 cs_threshold, freq); 791 } 792
Indexes created Sat Sep 20 22:09:52 GMT 2025