1 /* $NetBSD: kfd_pm4_headers_ai.h,v 1.2 2021/12/18 23:44:59 riastradh Exp $ */ 2 3 /* 4 * Copyright 2016 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 26 #ifndef F32_MES_PM4_PACKETS_H 27 #define F32_MES_PM4_PACKETS_H 28 29 #ifndef PM4_MES_HEADER_DEFINED 30 #define PM4_MES_HEADER_DEFINED 31 union PM4_MES_TYPE_3_HEADER { 32 struct { 33 uint32_t reserved1 : 8; /* < reserved */ 34 uint32_t opcode : 8; /* < IT opcode */ 35 uint32_t count : 14;/* < number of DWORDs - 1 in the 36 * information body. 37 */ 38 uint32_t type : 2; /* < packet identifier. 39 * It should be 3 for type 3 packets 40 */ 41 }; 42 uint32_t u32All; 43 }; 44 #endif /* PM4_MES_HEADER_DEFINED */ 45 46 /*--------------------MES_SET_RESOURCES--------------------*/ 47 48 #ifndef PM4_MES_SET_RESOURCES_DEFINED 49 #define PM4_MES_SET_RESOURCES_DEFINED 50 enum mes_set_resources_queue_type_enum { 51 queue_type__mes_set_resources__kernel_interface_queue_kiq = 0, 52 queue_type__mes_set_resources__hsa_interface_queue_hiq = 1, 53 queue_type__mes_set_resources__hsa_debug_interface_queue = 4 54 }; 55 56 57 struct pm4_mes_set_resources { 58 union { 59 union PM4_MES_TYPE_3_HEADER header; /* header */ 60 uint32_t ordinal1; 61 }; 62 63 union { 64 struct { 65 uint32_t vmid_mask:16; 66 uint32_t unmap_latency:8; 67 uint32_t reserved1:5; 68 enum mes_set_resources_queue_type_enum queue_type:3; 69 } bitfields2; 70 uint32_t ordinal2; 71 }; 72 73 uint32_t queue_mask_lo; 74 uint32_t queue_mask_hi; 75 uint32_t gws_mask_lo; 76 uint32_t gws_mask_hi; 77 78 union { 79 struct { 80 uint32_t oac_mask:16; 81 uint32_t reserved2:16; 82 } bitfields7; 83 uint32_t ordinal7; 84 }; 85 86 union { 87 struct { 88 uint32_t gds_heap_base:10; 89 uint32_t reserved3:1; 90 uint32_t gds_heap_size:10; 91 uint32_t reserved4:11; 92 } bitfields8; 93 uint32_t ordinal8; 94 }; 95 96 }; 97 #endif 98 99 /*--------------------MES_RUN_LIST--------------------*/ 100 101 #ifndef PM4_MES_RUN_LIST_DEFINED 102 #define PM4_MES_RUN_LIST_DEFINED 103 104 struct pm4_mes_runlist { 105 union { 106 union PM4_MES_TYPE_3_HEADER header; /* header */ 107 uint32_t ordinal1; 108 }; 109 110 union { 111 struct { 112 uint32_t reserved1:2; 113 uint32_t ib_base_lo:30; 114 } bitfields2; 115 uint32_t ordinal2; 116 }; 117 118 uint32_t ib_base_hi; 119 120 union { 121 struct { 122 uint32_t ib_size:20; 123 uint32_t chain:1; 124 uint32_t offload_polling:1; 125 uint32_t chained_runlist_idle_disable:1; 126 uint32_t valid:1; 127 uint32_t process_cnt:4; 128 uint32_t reserved3:4; 129 } bitfields4; 130 uint32_t ordinal4; 131 }; 132 133 }; 134 #endif 135 136 /*--------------------MES_MAP_PROCESS--------------------*/ 137 138 #ifndef PM4_MES_MAP_PROCESS_DEFINED 139 #define PM4_MES_MAP_PROCESS_DEFINED 140 141 struct pm4_mes_map_process { 142 union { 143 union PM4_MES_TYPE_3_HEADER header; /* header */ 144 uint32_t ordinal1; 145 }; 146 147 union { 148 struct { 149 uint32_t pasid:16; 150 uint32_t reserved1:8; 151 uint32_t diq_enable:1; 152 uint32_t process_quantum:7; 153 } bitfields2; 154 uint32_t ordinal2; 155 }; 156 157 uint32_t vm_context_page_table_base_addr_lo32; 158 159 uint32_t vm_context_page_table_base_addr_hi32; 160 161 uint32_t sh_mem_bases; 162 163 uint32_t sh_mem_config; 164 165 uint32_t sq_shader_tba_lo; 166 167 uint32_t sq_shader_tba_hi; 168 169 uint32_t sq_shader_tma_lo; 170 171 uint32_t sq_shader_tma_hi; 172 173 uint32_t reserved6; 174 175 uint32_t gds_addr_lo; 176 177 uint32_t gds_addr_hi; 178 179 union { 180 struct { 181 uint32_t num_gws:7; 182 uint32_t sdma_enable:1; 183 uint32_t num_oac:4; 184 uint32_t gds_size_hi:4; 185 uint32_t gds_size:6; 186 uint32_t num_queues:10; 187 } bitfields14; 188 uint32_t ordinal14; 189 }; 190 191 uint32_t completion_signal_lo; 192 193 uint32_t completion_signal_hi; 194 195 }; 196 197 #endif 198 199 /*--------------------MES_MAP_PROCESS_VM--------------------*/ 200 201 #ifndef PM4_MES_MAP_PROCESS_VM_DEFINED 202 #define PM4_MES_MAP_PROCESS_VM_DEFINED 203 204 struct PM4_MES_MAP_PROCESS_VM { 205 union { 206 union PM4_MES_TYPE_3_HEADER header; /* header */ 207 uint32_t ordinal1; 208 }; 209 210 uint32_t reserved1; 211 212 uint32_t vm_context_cntl; 213 214 uint32_t reserved2; 215 216 uint32_t vm_context_page_table_end_addr_lo32; 217 218 uint32_t vm_context_page_table_end_addr_hi32; 219 220 uint32_t vm_context_page_table_start_addr_lo32; 221 222 uint32_t vm_context_page_table_start_addr_hi32; 223 224 uint32_t reserved3; 225 226 uint32_t reserved4; 227 228 uint32_t reserved5; 229 230 uint32_t reserved6; 231 232 uint32_t reserved7; 233 234 uint32_t reserved8; 235 236 uint32_t completion_signal_lo32; 237 238 uint32_t completion_signal_hi32; 239 240 }; 241 #endif 242 243 /*--------------------MES_MAP_QUEUES--------------------*/ 244 245 #ifndef PM4_MES_MAP_QUEUES_VI_DEFINED 246 #define PM4_MES_MAP_QUEUES_VI_DEFINED 247 enum mes_map_queues_queue_sel_enum { 248 queue_sel__mes_map_queues__map_to_specified_queue_slots_vi = 0, 249 queue_sel__mes_map_queues__map_to_hws_determined_queue_slots_vi = 1 250 }; 251 252 enum mes_map_queues_queue_type_enum { 253 queue_type__mes_map_queues__normal_compute_vi = 0, 254 queue_type__mes_map_queues__debug_interface_queue_vi = 1, 255 queue_type__mes_map_queues__normal_latency_static_queue_vi = 2, 256 queue_type__mes_map_queues__low_latency_static_queue_vi = 3 257 }; 258 259 enum mes_map_queues_engine_sel_enum { 260 engine_sel__mes_map_queues__compute_vi = 0, 261 engine_sel__mes_map_queues__sdma0_vi = 2, 262 engine_sel__mes_map_queues__sdma1_vi = 3 263 }; 264 265 enum mes_map_queues_extended_engine_sel_enum { 266 extended_engine_sel__mes_map_queues__legacy_engine_sel = 0, 267 extended_engine_sel__mes_map_queues__sdma0_to_7_sel = 1 268 }; 269 270 struct pm4_mes_map_queues { 271 union { 272 union PM4_MES_TYPE_3_HEADER header; /* header */ 273 uint32_t ordinal1; 274 }; 275 276 union { 277 struct { 278 uint32_t reserved1:2; 279 enum mes_map_queues_extended_engine_sel_enum extended_engine_sel:2; 280 enum mes_map_queues_queue_sel_enum queue_sel:2; 281 uint32_t reserved5:6; 282 uint32_t gws_control_queue:1; 283 uint32_t reserved2:8; 284 enum mes_map_queues_queue_type_enum queue_type:3; 285 uint32_t reserved3:2; 286 enum mes_map_queues_engine_sel_enum engine_sel:3; 287 uint32_t num_queues:3; 288 } bitfields2; 289 uint32_t ordinal2; 290 }; 291 292 union { 293 struct { 294 uint32_t reserved3:1; 295 uint32_t check_disable:1; 296 uint32_t doorbell_offset:26; 297 uint32_t reserved4:4; 298 } bitfields3; 299 uint32_t ordinal3; 300 }; 301 302 uint32_t mqd_addr_lo; 303 uint32_t mqd_addr_hi; 304 uint32_t wptr_addr_lo; 305 uint32_t wptr_addr_hi; 306 }; 307 #endif 308 309 /*--------------------MES_QUERY_STATUS--------------------*/ 310 311 #ifndef PM4_MES_QUERY_STATUS_DEFINED 312 #define PM4_MES_QUERY_STATUS_DEFINED 313 enum mes_query_status_interrupt_sel_enum { 314 interrupt_sel__mes_query_status__completion_status = 0, 315 interrupt_sel__mes_query_status__process_status = 1, 316 interrupt_sel__mes_query_status__queue_status = 2 317 }; 318 319 enum mes_query_status_command_enum { 320 command__mes_query_status__interrupt_only = 0, 321 command__mes_query_status__fence_only_immediate = 1, 322 command__mes_query_status__fence_only_after_write_ack = 2, 323 command__mes_query_status__fence_wait_for_write_ack_send_interrupt = 3 324 }; 325 326 enum mes_query_status_engine_sel_enum { 327 engine_sel__mes_query_status__compute = 0, 328 engine_sel__mes_query_status__sdma0_queue = 2, 329 engine_sel__mes_query_status__sdma1_queue = 3 330 }; 331 332 struct pm4_mes_query_status { 333 union { 334 union PM4_MES_TYPE_3_HEADER header; /* header */ 335 uint32_t ordinal1; 336 }; 337 338 union { 339 struct { 340 uint32_t context_id:28; 341 enum mes_query_status_interrupt_sel_enum interrupt_sel:2; 342 enum mes_query_status_command_enum command:2; 343 } bitfields2; 344 uint32_t ordinal2; 345 }; 346 347 union { 348 struct { 349 uint32_t pasid:16; 350 uint32_t reserved1:16; 351 } bitfields3a; 352 struct { 353 uint32_t reserved2:2; 354 uint32_t doorbell_offset:26; 355 enum mes_query_status_engine_sel_enum engine_sel:3; 356 uint32_t reserved3:1; 357 } bitfields3b; 358 uint32_t ordinal3; 359 }; 360 361 uint32_t addr_lo; 362 uint32_t addr_hi; 363 uint32_t data_lo; 364 uint32_t data_hi; 365 }; 366 #endif 367 368 /*--------------------MES_UNMAP_QUEUES--------------------*/ 369 370 #ifndef PM4_MES_UNMAP_QUEUES_DEFINED 371 #define PM4_MES_UNMAP_QUEUES_DEFINED 372 enum mes_unmap_queues_action_enum { 373 action__mes_unmap_queues__preempt_queues = 0, 374 action__mes_unmap_queues__reset_queues = 1, 375 action__mes_unmap_queues__disable_process_queues = 2, 376 action__mes_unmap_queues__reserved = 3 377 }; 378 379 enum mes_unmap_queues_queue_sel_enum { 380 queue_sel__mes_unmap_queues__perform_request_on_specified_queues = 0, 381 queue_sel__mes_unmap_queues__perform_request_on_pasid_queues = 1, 382 queue_sel__mes_unmap_queues__unmap_all_queues = 2, 383 queue_sel__mes_unmap_queues__unmap_all_non_static_queues = 3 384 }; 385 386 enum mes_unmap_queues_engine_sel_enum { 387 engine_sel__mes_unmap_queues__compute = 0, 388 engine_sel__mes_unmap_queues__sdma0 = 2, 389 engine_sel__mes_unmap_queues__sdmal = 3 390 }; 391 392 enum mes_unmap_queues_extended_engine_sel_enum { 393 extended_engine_sel__mes_unmap_queues__legacy_engine_sel = 0, 394 extended_engine_sel__mes_unmap_queues__sdma0_to_7_sel = 1 395 }; 396 397 struct pm4_mes_unmap_queues { 398 union { 399 union PM4_MES_TYPE_3_HEADER header; /* header */ 400 uint32_t ordinal1; 401 }; 402 403 union { 404 struct { 405 enum mes_unmap_queues_action_enum action:2; 406 enum mes_unmap_queues_extended_engine_sel_enum extended_engine_sel:2; 407 enum mes_unmap_queues_queue_sel_enum queue_sel:2; 408 uint32_t reserved2:20; 409 enum mes_unmap_queues_engine_sel_enum engine_sel:3; 410 uint32_t num_queues:3; 411 } bitfields2; 412 uint32_t ordinal2; 413 }; 414 415 union { 416 struct { 417 uint32_t pasid:16; 418 uint32_t reserved3:16; 419 } bitfields3a; 420 struct { 421 uint32_t reserved4:2; 422 uint32_t doorbell_offset0:26; 423 int32_t reserved5:4; 424 } bitfields3b; 425 uint32_t ordinal3; 426 }; 427 428 union { 429 struct { 430 uint32_t reserved6:2; 431 uint32_t doorbell_offset1:26; 432 uint32_t reserved7:4; 433 } bitfields4; 434 uint32_t ordinal4; 435 }; 436 437 union { 438 struct { 439 uint32_t reserved8:2; 440 uint32_t doorbell_offset2:26; 441 uint32_t reserved9:4; 442 } bitfields5; 443 uint32_t ordinal5; 444 }; 445 446 union { 447 struct { 448 uint32_t reserved10:2; 449 uint32_t doorbell_offset3:26; 450 uint32_t reserved11:4; 451 } bitfields6; 452 uint32_t ordinal6; 453 }; 454 }; 455 #endif 456 457 #ifndef PM4_MEC_RELEASE_MEM_DEFINED 458 #define PM4_MEC_RELEASE_MEM_DEFINED 459 460 enum mec_release_mem_event_index_enum { 461 event_index__mec_release_mem__end_of_pipe = 5, 462 event_index__mec_release_mem__shader_done = 6 463 }; 464 465 enum mec_release_mem_cache_policy_enum { 466 cache_policy__mec_release_mem__lru = 0, 467 cache_policy__mec_release_mem__stream = 1 468 }; 469 470 enum mec_release_mem_pq_exe_status_enum { 471 pq_exe_status__mec_release_mem__default = 0, 472 pq_exe_status__mec_release_mem__phase_update = 1 473 }; 474 475 enum mec_release_mem_dst_sel_enum { 476 dst_sel__mec_release_mem__memory_controller = 0, 477 dst_sel__mec_release_mem__tc_l2 = 1, 478 dst_sel__mec_release_mem__queue_write_pointer_register = 2, 479 dst_sel__mec_release_mem__queue_write_pointer_poll_mask_bit = 3 480 }; 481 482 enum mec_release_mem_int_sel_enum { 483 int_sel__mec_release_mem__none = 0, 484 int_sel__mec_release_mem__send_interrupt_only = 1, 485 int_sel__mec_release_mem__send_interrupt_after_write_confirm = 2, 486 int_sel__mec_release_mem__send_data_after_write_confirm = 3, 487 int_sel__mec_release_mem__unconditionally_send_int_ctxid = 4, 488 int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_32_bit_compare = 5, 489 int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_64_bit_compare = 6 490 }; 491 492 enum mec_release_mem_data_sel_enum { 493 data_sel__mec_release_mem__none = 0, 494 data_sel__mec_release_mem__send_32_bit_low = 1, 495 data_sel__mec_release_mem__send_64_bit_data = 2, 496 data_sel__mec_release_mem__send_gpu_clock_counter = 3, 497 data_sel__mec_release_mem__send_cp_perfcounter_hi_lo = 4, 498 data_sel__mec_release_mem__store_gds_data_to_memory = 5 499 }; 500 501 struct pm4_mec_release_mem { 502 union { 503 union PM4_MES_TYPE_3_HEADER header; /*header */ 504 unsigned int ordinal1; 505 }; 506 507 union { 508 struct { 509 unsigned int event_type:6; 510 unsigned int reserved1:2; 511 enum mec_release_mem_event_index_enum event_index:4; 512 unsigned int tcl1_vol_action_ena:1; 513 unsigned int tc_vol_action_ena:1; 514 unsigned int reserved2:1; 515 unsigned int tc_wb_action_ena:1; 516 unsigned int tcl1_action_ena:1; 517 unsigned int tc_action_ena:1; 518 uint32_t reserved3:1; 519 uint32_t tc_nc_action_ena:1; 520 uint32_t tc_wc_action_ena:1; 521 uint32_t tc_md_action_ena:1; 522 uint32_t reserved4:3; 523 enum mec_release_mem_cache_policy_enum cache_policy:2; 524 uint32_t reserved5:2; 525 enum mec_release_mem_pq_exe_status_enum pq_exe_status:1; 526 uint32_t reserved6:2; 527 } bitfields2; 528 unsigned int ordinal2; 529 }; 530 531 union { 532 struct { 533 uint32_t reserved7:16; 534 enum mec_release_mem_dst_sel_enum dst_sel:2; 535 uint32_t reserved8:6; 536 enum mec_release_mem_int_sel_enum int_sel:3; 537 uint32_t reserved9:2; 538 enum mec_release_mem_data_sel_enum data_sel:3; 539 } bitfields3; 540 unsigned int ordinal3; 541 }; 542 543 union { 544 struct { 545 uint32_t reserved10:2; 546 unsigned int address_lo_32b:30; 547 } bitfields4; 548 struct { 549 uint32_t reserved11:3; 550 uint32_t address_lo_64b:29; 551 } bitfields4b; 552 uint32_t reserved12; 553 unsigned int ordinal4; 554 }; 555 556 union { 557 uint32_t address_hi; 558 uint32_t reserved13; 559 uint32_t ordinal5; 560 }; 561 562 union { 563 uint32_t data_lo; 564 uint32_t cmp_data_lo; 565 struct { 566 uint32_t dw_offset:16; 567 uint32_t num_dwords:16; 568 } bitfields6c; 569 uint32_t reserved14; 570 uint32_t ordinal6; 571 }; 572 573 union { 574 uint32_t data_hi; 575 uint32_t cmp_data_hi; 576 uint32_t reserved15; 577 uint32_t reserved16; 578 uint32_t ordinal7; 579 }; 580 581 uint32_t int_ctxid; 582 583 }; 584 585 #endif 586 587 enum { 588 CACHE_FLUSH_AND_INV_TS_EVENT = 0x00000014 589 }; 590 #endif 591 592
Indexes created Thu Sep 25 16:09:42 GMT 2025