1 /* $NetBSD: cpufunc_asm_fa526.S,v 1.8 2022/10/20 06:58:38 skrll Exp $ */ 2 /*- 3 * Copyright (c) 2008 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Matt Thomas <matt (at) 3am-software.com> 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include "assym.h" 32 #include <machine/asm.h> 33 #include <arm/locore.h> 34 35 #define CACHELINE_SIZE 16 36 37 ENTRY(fa526_setttb) 38 cmp r1, #0 @ need to flush the cache / tlb? 39 beq 1f @ nope, so don't 40 mov r2, #0 41 mcr p15, 0, r2, c7, c14, 0 /* clean and invalidate D$ */ 42 mcr p15, 0, r2, c7, c5, 0 /* invalidate I$ */ 43 mcr p15, 0, r2, c7, c5, 6 /* invalidate BTB */ 44 mcr p15, 0, r2, c7, c10, 4 /* drain write and fill buffer */ 45 1: 46 mcr p15, 0, r0, c2, c0, 0 /* Write the TTB */ 47 48 /* If we have updated the TTB we must flush the TLB */ 49 mcrne p15, 0, r1, c8, c7, 0 /* invalidate I+D TLB */ 50 51 /* Make sure that pipeline is emptied */ 52 mov r0, r0 53 mov r0, r0 54 mov pc, lr 55 END(fa526_setttb) 56 57 /* 58 * TLB functions 59 */ 60 ENTRY(fa526_tlb_flushID_SE) 61 mcr p15, 0, r0, c8, c7, 1 /* flush Utlb single entry */ 62 #if PAGE_SIZE == 2 * L2_S_SIZE 63 add r0, r0, #L2_S_SIZE 64 mcr p15, 0, r0, c8, c7, 1 /* flush Utlb single entry */ 65 #endif 66 mov pc, lr 67 END(fa526_tlb_flushID_SE) 68 69 /* 70 * TLB functions 71 */ 72 ENTRY(fa526_tlb_flushI_SE) 73 mcr p15, 0, r0, c8, c5, 1 /* flush Itlb single entry */ 74 #if PAGE_SIZE == 2 * L2_S_SIZE 75 add r0, r0, #L2_S_SIZE 76 mcr p15, 0, r0, c8, c5, 1 /* flush Itlb single entry */ 77 #endif 78 mov pc, lr 79 END(fa526_tlb_flushI_SE) 80 81 ENTRY(fa526_cpu_sleep) 82 mov r0, #0 83 mcr p15, 0, r0, c7, c5, 5 /* Enter sleep mode */ 84 mov pc, lr 85 END(fa526_cpu_sleep) 86 87 ENTRY(fa526_flush_prefetchbuf) 88 mov r0, #0 89 mcr p15, 0, r0, c7, c5, 4 /* Pre-fetch flush */ 90 mov pc, lr 91 END(fa526_flush_prefetchbuf) 92 93 /* 94 * Cache functions 95 */ 96 ENTRY(fa526_idcache_wbinv_all) 97 mov r0, #0 98 mcr p15, 0, r0, c7, c14, 0 /* clean and invalidate D$ */ 99 mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ */ 100 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ 101 mov pc, lr 102 END(fa526_idcache_wbinv_all) 103 104 ENTRY(fa526_icache_sync_all) 105 mov r0, #0 106 mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ */ 107 mov pc, lr 108 END(fa526_icache_sync_all) 109 110 ENTRY(fa526_dcache_wbinv_all) 111 mov r0, #0 112 mcr p15, 0, r0, c7, c14, 0 /* clean and invalidate D$ */ 113 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ 114 mov pc, lr 115 END(fa526_dcache_wbinv_all) 116 117 /* 118 * Soft functions 119 */ 120 ENTRY(fa526_dcache_wbinv_range) 121 cmp r1, #0x4000 122 bhs _C_LABEL(fa526_dcache_wbinv_all) 123 124 and r2, r0, #(CACHELINE_SIZE-1) 125 add r1, r1, r2 126 bic r0, r0, #(CACHELINE_SIZE-1) 127 128 1: mcr p15, 0, r0, c7, c14, 1 /* clean and invalidate D$ entry */ 129 add r0, r0, #CACHELINE_SIZE 130 subs r1, r1, #CACHELINE_SIZE 131 bhi 1b 132 133 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ 134 mov pc, lr 135 END(fa526_dcache_wbinv_range) 136 137 ENTRY(fa526_dcache_wb_range) 138 cmp r1, #0x4000 139 bls 1f 140 141 mov r0, #0 142 mcr p15, 0, r0, c7, c10, 0 /* clean entire D$ */ 143 b 3f 144 145 1: and r2, r0, #(CACHELINE_SIZE-1) 146 add r1, r1, r2 147 bic r0, r0, #(CACHELINE_SIZE-1) 148 149 2: mcr p15, 0, r0, c7, c10, 1 /* clean D$ entry */ 150 add r0, r0, #CACHELINE_SIZE 151 subs r1, r1, #CACHELINE_SIZE 152 bhi 2b 153 154 3: mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ 155 mov pc, lr 156 END(fa526_dcache_wb_range) 157 158 ENTRY(fa526_dcache_inv_range) 159 and r2, r0, #(CACHELINE_SIZE-1) 160 add r1, r1, r2 161 bic r0, r0, #(CACHELINE_SIZE-1) 162 163 1: mcr p15, 0, r0, c7, c6, 1 /* invalidate D$ single entry */ 164 add r0, r0, #CACHELINE_SIZE 165 subs r1, r1, #CACHELINE_SIZE 166 bhi 1b 167 168 mov pc, lr 169 END(fa526_dcache_inv_range) 170 171 ENTRY(fa526_idcache_wbinv_range) 172 cmp r1, #0x4000 173 bhs _C_LABEL(fa526_idcache_wbinv_all) 174 175 and r2, r0, #(CACHELINE_SIZE-1) 176 add r1, r1, r2 177 bic r0, r0, #(CACHELINE_SIZE-1) 178 179 1: mcr p15, 0, r0, c7, c14, 1 /* clean and invalidate D$ entry */ 180 mcr p15, 0, r0, c7, c5, 1 /* invalidate I$ entry */ 181 add r0, r0, #CACHELINE_SIZE 182 subs r1, r1, #CACHELINE_SIZE 183 bhi 1b 184 185 2: mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ 186 mov pc, lr 187 END(fa526_idcache_wbinv_range) 188 189 ENTRY(fa526_icache_sync_range) 190 cmp r1, #0x4000 191 bhs _C_LABEL(fa526_icache_sync_all) 192 193 and r2, r0, #(CACHELINE_SIZE-1) 194 add r1, r1, r2 195 bic r0, r0, #(CACHELINE_SIZE-1) 196 197 1: mcr p15, 0, r0, c7, c10, 1 /* clean D$ entry */ 198 mcr p15, 0, r0, c7, c5, 1 /* invalidate I$ entry */ 199 add r0, r0, #CACHELINE_SIZE 200 subs r1, r1, #CACHELINE_SIZE 201 bhi 1b 202 203 2: mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ 204 mov pc, lr 205 END(fa526_icache_sync_range) 206 207 ENTRY(fa526_flush_brnchtgt_E) 208 mov r0, #0 209 mcr p15, 0, r0, c7, c5, 6 /* invalidate BTB cache */ 210 mov pc, lr 211 END(fa526_flush_brnchtgt_E) 212 213 ENTRY(fa526_context_switch) 214 /* 215 * CF_CACHE_PURGE_ID will *ALWAYS* be called prior to this. 216 * Thus the data cache will contain only kernel data and the 217 * instruction cache will contain only kernel code, and all 218 * kernel mappings are shared by all processes. 219 */ 220 221 mcr p15, 0, r0, c2, c0, 0 /* Write the TTB */ 222 223 /* If we have updated the TTB we must flush the TLB */ 224 mov r0, #0 225 mcr p15, 0, r0, c8, c7, 0 /* flush the I+D tlb */ 226 227 /* Make sure that pipeline is emptied */ 228 mov r0, r0 229 mov r0, r0 230 mov pc, lr 231 END(fa526_context_switch) 232
Indexes created Sat Sep 20 22:09:52 GMT 2025