| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/ |
| amdgpu_arcturus_ppt.c | 360 uint32_t *feature_mask, uint32_t num)
366 memset(feature_mask, 0xFF, sizeof(uint32_t) * num);
742 uint32_t feature_mask)
751 (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
766 (feature_mask & FEATURE_DPM_UCLK_MASK)) {
781 (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
1960 uint32_t feature_mask[2]; local in function:arcturus_is_dpm_running
1962 ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
1965 feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
1966 ((uint64_t)feature_mask[1] << 32))
[all...] |
| amdgpu_navi10_ppt.c | 52 #define FEATURE_MASK(feature) (1ULL << feature)
54 FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
55 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \
56 FEATURE_MASK(FEATURE_DPM_GFX_PACE_BIT) | \
57 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \
58 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \
59 FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT) | \
60 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \
61 FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT))
336 uint32_t *feature_mask, uint32_t num
1197 uint32_t feature_mask[2]; local in function:navi10_is_dpm_running
[all...] |
| amdgpu_smu.c | 77 uint32_t feature_mask[2] = { 0 }; local in function:smu_sys_get_pp_feature_mask
85 ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
90 feature_mask[1], feature_mask[0]);
116 uint64_t feature_mask,
126 feature_low = (feature_mask >> 0 ) & 0xffffffff;
127 feature_high = (feature_mask >> 32) & 0xffffffff;
152 (unsigned long *)(&feature_mask), SMU_FEATURE_MAX);
155 (unsigned long *)(&feature_mask), SMU_FEATURE_MAX);
164 uint32_t feature_mask[2] = { 0 } local in function:smu_sys_set_pp_feature_mask
[all...] |
| amdgpu_smu_v11_0.c | 838 uint32_t feature_mask[2]; local in function:smu_v11_0_set_allowed_mask
844 bitmap_copy((unsigned long *)feature_mask, feature->allowed, 64);
847 feature_mask[1]);
852 feature_mask[0]);
862 uint32_t *feature_mask, uint32_t num)
868 if (!feature_mask || num < 2)
886 feature_mask[0] = feature_mask_low;
887 feature_mask[1] = feature_mask_high;
889 bitmap_copy((unsigned long *)feature_mask, feature->enabled,
900 uint32_t feature_mask[2] local in function:smu_v11_0_system_features_control
[all...] |
| amdgpu_vega20_ppt.c | 600 #define FEATURE_MASK(feature) (1ULL << feature)
603 uint32_t *feature_mask, uint32_t num)
608 memset(feature_mask, 0, sizeof(uint32_t) * num);
610 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
611 | FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)
612 | FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
613 | FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)
614 | FEATURE_MASK(FEATURE_DPM_UVD_BIT)
615 | FEATURE_MASK(FEATURE_DPM_VCE_BIT
2849 uint32_t feature_mask[2]; local in function:vega20_is_dpm_running
[all...] |
| /src/sys/external/bsd/ena-com/ |
| ena_com.c | 892 u32 feature_mask = 1 << feature_id; local in function:ena_com_check_supported_feature_id
896 !(ena_dev->supported_features & feature_mask))
|
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/ |
| amdgpu_vega10_hwmgr.c | 125 hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true;
127 hwmgr->feature_mask & PP_SOCCLK_DPM_MASK ? false : true;
129 hwmgr->feature_mask & PP_MCLK_DPM_MASK ? false : true;
131 hwmgr->feature_mask & PP_PCIE_DPM_MASK ? false : true;
134 hwmgr->feature_mask & PP_DCEFCLK_DPM_MASK ? false : true;
136 if (hwmgr->feature_mask & PP_POWER_CONTAINMENT_MASK) {
143 hwmgr->feature_mask & PP_CLOCK_STRETCH_MASK ? true : false;
146 hwmgr->feature_mask & PP_ULV_MASK ? true : false;
149 hwmgr->feature_mask & PP_SCLK_DEEP_SLEEP_MASK ? true : false;
158 hwmgr->feature_mask & PP_AVFS_MASK ? true : false
2843 uint32_t i, feature_mask = 0; local in function:vega10_stop_dpm
2882 uint32_t i, feature_mask = 0; local in function:vega10_start_dpm
5343 uint32_t feature_mask = 0; local in function:vega10_disable_power_features_for_compute_performance
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/ |
| hwmgr.h | 791 uint32_t feature_mask; member in struct:pp_hwmgr
|
