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      1 //===-- ARMFixupKinds.h - ARM Specific Fixup Entries ------------*- C++ -*-===//
      2 //
      3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
      4 // See https://llvm.org/LICENSE.txt for license information.
      5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
      6 //
      7 //===----------------------------------------------------------------------===//
      8 
      9 #ifndef LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMFIXUPKINDS_H
     10 #define LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMFIXUPKINDS_H
     11 
     12 #include "llvm/MC/MCFixup.h"
     13 
     14 namespace llvm {
     15 namespace ARM {
     16 enum Fixups {
     17   // 12-bit PC relative relocation for symbol addresses
     18   fixup_arm_ldst_pcrel_12 = FirstTargetFixupKind,
     19 
     20   // Equivalent to fixup_arm_ldst_pcrel_12, with the 16-bit halfwords reordered.
     21   fixup_t2_ldst_pcrel_12,
     22 
     23   // 10-bit PC relative relocation for symbol addresses used in
     24   // LDRD/LDRH/LDRB/etc. instructions. All bits are encoded.
     25   fixup_arm_pcrel_10_unscaled,
     26   // 10-bit PC relative relocation for symbol addresses used in VFP instructions
     27   // where the lower 2 bits are not encoded (so it's encoded as an 8-bit
     28   // immediate).
     29   fixup_arm_pcrel_10,
     30   // Equivalent to fixup_arm_pcrel_10, accounting for the short-swapped encoding
     31   // of Thumb2 instructions.
     32   fixup_t2_pcrel_10,
     33   // 9-bit PC relative relocation for symbol addresses used in VFP instructions
     34   // where bit 0 not encoded (so it's encoded as an 8-bit immediate).
     35   fixup_arm_pcrel_9,
     36   // Equivalent to fixup_arm_pcrel_9, accounting for the short-swapped encoding
     37   // of Thumb2 instructions.
     38   fixup_t2_pcrel_9,
     39   // 12-bit immediate value.
     40   fixup_arm_ldst_abs_12,
     41   // 10-bit PC relative relocation for symbol addresses where the lower 2 bits
     42   // are not encoded (so it's encoded as an 8-bit immediate).
     43   fixup_thumb_adr_pcrel_10,
     44   // 12-bit PC relative relocation for the ADR instruction.
     45   fixup_arm_adr_pcrel_12,
     46   // 12-bit PC relative relocation for the ADR instruction.
     47   fixup_t2_adr_pcrel_12,
     48   // 24-bit PC relative relocation for conditional branch instructions.
     49   fixup_arm_condbranch,
     50   // 24-bit PC relative relocation for branch instructions. (unconditional)
     51   fixup_arm_uncondbranch,
     52   // 20-bit PC relative relocation for Thumb2 direct uconditional branch
     53   // instructions.
     54   fixup_t2_condbranch,
     55   // 20-bit PC relative relocation for Thumb2 direct branch unconditional branch
     56   // instructions.
     57   fixup_t2_uncondbranch,
     58 
     59   // 12-bit fixup for Thumb B instructions.
     60   fixup_arm_thumb_br,
     61 
     62   // The following fixups handle the ARM BL instructions. These can be
     63   // conditionalised; however, the ARM ELF ABI requires a different relocation
     64   // in that case: R_ARM_JUMP24 instead of R_ARM_CALL. The difference is that
     65   // R_ARM_CALL is allowed to change the instruction to a BLX inline, which has
     66   // no conditional version; R_ARM_JUMP24 would have to insert a veneer.
     67   //
     68   // MachO does not draw a distinction between the two cases, so it will treat
     69   // fixup_arm_uncondbl and fixup_arm_condbl as identical fixups.
     70 
     71   // Fixup for unconditional ARM BL instructions.
     72   fixup_arm_uncondbl,
     73 
     74   // Fixup for ARM BL instructions with nontrivial conditionalisation.
     75   fixup_arm_condbl,
     76 
     77   // Fixup for ARM BLX instructions.
     78   fixup_arm_blx,
     79 
     80   // Fixup for Thumb BL instructions.
     81   fixup_arm_thumb_bl,
     82 
     83   // Fixup for Thumb BLX instructions.
     84   fixup_arm_thumb_blx,
     85 
     86   // Fixup for Thumb branch instructions.
     87   fixup_arm_thumb_cb,
     88 
     89   // Fixup for Thumb load/store from constant pool instrs.
     90   fixup_arm_thumb_cp,
     91 
     92   // Fixup for Thumb conditional branching instructions.
     93   fixup_arm_thumb_bcc,
     94 
     95   // The next two are for the movt/movw pair
     96   // the 16bit imm field are split into imm{15-12} and imm{11-0}
     97   fixup_arm_movt_hi16, // :upper16:
     98   fixup_arm_movw_lo16, // :lower16:
     99   fixup_t2_movt_hi16,  // :upper16:
    100   fixup_t2_movw_lo16,  // :lower16:
    101 
    102   // Fixup for mod_imm
    103   fixup_arm_mod_imm,
    104 
    105   // Fixup for Thumb2 8-bit rotated operand
    106   fixup_t2_so_imm,
    107 
    108   // Fixups for Branch Future.
    109   fixup_bf_branch,
    110   fixup_bf_target,
    111   fixup_bfl_target,
    112   fixup_bfc_target,
    113   fixup_bfcsel_else_target,
    114   fixup_wls,
    115   fixup_le,
    116 
    117   // Marker
    118   LastTargetFixupKind,
    119   NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind
    120 };
    121 }
    122 } // namespace llvm
    123 
    124 #endif
    125