1 /* $NetBSD: i915_pci.c,v 1.5 2024/01/14 22:15:15 riastradh Exp $ */ 2 3 /* 4 * Copyright 2016 Intel Corporation 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 23 * IN THE SOFTWARE. 24 * 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: i915_pci.c,v 1.5 2024/01/14 22:15:15 riastradh Exp $"); 29 30 #include <linux/console.h> 31 #include <linux/vga_switcheroo.h> 32 33 #include <drm/drm_drv.h> 34 35 #include "display/intel_fbdev.h" 36 37 #include "i915_drv.h" 38 #include "i915_perf.h" 39 #include "i915_globals.h" 40 #include "i915_selftest.h" 41 42 #define PLATFORM(x) .platform = (x) 43 #define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1) 44 45 #define I845_PIPE_OFFSETS \ 46 .pipe_offsets = { \ 47 [TRANSCODER_A] = PIPE_A_OFFSET, \ 48 }, \ 49 .trans_offsets = { \ 50 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 51 } 52 53 #define I9XX_PIPE_OFFSETS \ 54 .pipe_offsets = { \ 55 [TRANSCODER_A] = PIPE_A_OFFSET, \ 56 [TRANSCODER_B] = PIPE_B_OFFSET, \ 57 }, \ 58 .trans_offsets = { \ 59 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 60 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 61 } 62 63 #define IVB_PIPE_OFFSETS \ 64 .pipe_offsets = { \ 65 [TRANSCODER_A] = PIPE_A_OFFSET, \ 66 [TRANSCODER_B] = PIPE_B_OFFSET, \ 67 [TRANSCODER_C] = PIPE_C_OFFSET, \ 68 }, \ 69 .trans_offsets = { \ 70 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 71 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 72 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 73 } 74 75 #define HSW_PIPE_OFFSETS \ 76 .pipe_offsets = { \ 77 [TRANSCODER_A] = PIPE_A_OFFSET, \ 78 [TRANSCODER_B] = PIPE_B_OFFSET, \ 79 [TRANSCODER_C] = PIPE_C_OFFSET, \ 80 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \ 81 }, \ 82 .trans_offsets = { \ 83 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 84 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 85 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 86 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \ 87 } 88 89 #define CHV_PIPE_OFFSETS \ 90 .pipe_offsets = { \ 91 [TRANSCODER_A] = PIPE_A_OFFSET, \ 92 [TRANSCODER_B] = PIPE_B_OFFSET, \ 93 [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \ 94 }, \ 95 .trans_offsets = { \ 96 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 97 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 98 [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \ 99 } 100 101 #define I845_CURSOR_OFFSETS \ 102 .cursor_offsets = { \ 103 [PIPE_A] = CURSOR_A_OFFSET, \ 104 } 105 106 #define I9XX_CURSOR_OFFSETS \ 107 .cursor_offsets = { \ 108 [PIPE_A] = CURSOR_A_OFFSET, \ 109 [PIPE_B] = CURSOR_B_OFFSET, \ 110 } 111 112 #define CHV_CURSOR_OFFSETS \ 113 .cursor_offsets = { \ 114 [PIPE_A] = CURSOR_A_OFFSET, \ 115 [PIPE_B] = CURSOR_B_OFFSET, \ 116 [PIPE_C] = CHV_CURSOR_C_OFFSET, \ 117 } 118 119 #define IVB_CURSOR_OFFSETS \ 120 .cursor_offsets = { \ 121 [PIPE_A] = CURSOR_A_OFFSET, \ 122 [PIPE_B] = IVB_CURSOR_B_OFFSET, \ 123 [PIPE_C] = IVB_CURSOR_C_OFFSET, \ 124 } 125 126 #define TGL_CURSOR_OFFSETS \ 127 .cursor_offsets = { \ 128 [PIPE_A] = CURSOR_A_OFFSET, \ 129 [PIPE_B] = IVB_CURSOR_B_OFFSET, \ 130 [PIPE_C] = IVB_CURSOR_C_OFFSET, \ 131 [PIPE_D] = TGL_CURSOR_D_OFFSET, \ 132 } 133 134 #define I9XX_COLORS \ 135 .color = { .gamma_lut_size = 256 } 136 #define I965_COLORS \ 137 .color = { .gamma_lut_size = 129, \ 138 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 139 } 140 #define ILK_COLORS \ 141 .color = { .gamma_lut_size = 1024 } 142 #define IVB_COLORS \ 143 .color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 } 144 #define CHV_COLORS \ 145 .color = { .degamma_lut_size = 65, .gamma_lut_size = 257, \ 146 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 147 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 148 } 149 #define GLK_COLORS \ 150 .color = { .degamma_lut_size = 33, .gamma_lut_size = 1024, \ 151 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \ 152 DRM_COLOR_LUT_EQUAL_CHANNELS, \ 153 } 154 155 /* Keep in gen based order, and chronological order within a gen */ 156 157 #define GEN_DEFAULT_PAGE_SIZES \ 158 .page_sizes = I915_GTT_PAGE_SIZE_4K 159 160 #define GEN_DEFAULT_REGIONS \ 161 .memory_regions = REGION_SMEM | REGION_STOLEN 162 163 #define I830_FEATURES \ 164 GEN(2), \ 165 .is_mobile = 1, \ 166 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 167 .display.has_overlay = 1, \ 168 .display.cursor_needs_physical = 1, \ 169 .display.overlay_needs_physical = 1, \ 170 .display.has_gmch = 1, \ 171 .gpu_reset_clobbers_display = true, \ 172 .hws_needs_physical = 1, \ 173 .unfenced_needs_alignment = 1, \ 174 .engine_mask = BIT(RCS0), \ 175 .has_snoop = true, \ 176 .has_coherent_ggtt = false, \ 177 I9XX_PIPE_OFFSETS, \ 178 I9XX_CURSOR_OFFSETS, \ 179 I9XX_COLORS, \ 180 GEN_DEFAULT_PAGE_SIZES, \ 181 GEN_DEFAULT_REGIONS 182 183 #define I845_FEATURES \ 184 GEN(2), \ 185 .pipe_mask = BIT(PIPE_A), \ 186 .display.has_overlay = 1, \ 187 .display.overlay_needs_physical = 1, \ 188 .display.has_gmch = 1, \ 189 .gpu_reset_clobbers_display = true, \ 190 .hws_needs_physical = 1, \ 191 .unfenced_needs_alignment = 1, \ 192 .engine_mask = BIT(RCS0), \ 193 .has_snoop = true, \ 194 .has_coherent_ggtt = false, \ 195 I845_PIPE_OFFSETS, \ 196 I845_CURSOR_OFFSETS, \ 197 I9XX_COLORS, \ 198 GEN_DEFAULT_PAGE_SIZES, \ 199 GEN_DEFAULT_REGIONS 200 201 static const struct intel_device_info i830_info = { 202 I830_FEATURES, 203 PLATFORM(INTEL_I830), 204 }; 205 206 static const struct intel_device_info i845g_info = { 207 I845_FEATURES, 208 PLATFORM(INTEL_I845G), 209 }; 210 211 static const struct intel_device_info i85x_info = { 212 I830_FEATURES, 213 PLATFORM(INTEL_I85X), 214 .display.has_fbc = 1, 215 }; 216 217 static const struct intel_device_info i865g_info = { 218 I845_FEATURES, 219 PLATFORM(INTEL_I865G), 220 }; 221 222 #define GEN3_FEATURES \ 223 GEN(3), \ 224 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 225 .display.has_gmch = 1, \ 226 .gpu_reset_clobbers_display = true, \ 227 .engine_mask = BIT(RCS0), \ 228 .has_snoop = true, \ 229 .has_coherent_ggtt = true, \ 230 I9XX_PIPE_OFFSETS, \ 231 I9XX_CURSOR_OFFSETS, \ 232 I9XX_COLORS, \ 233 GEN_DEFAULT_PAGE_SIZES, \ 234 GEN_DEFAULT_REGIONS 235 236 static const struct intel_device_info i915g_info = { 237 GEN3_FEATURES, 238 PLATFORM(INTEL_I915G), 239 .has_coherent_ggtt = false, 240 .display.cursor_needs_physical = 1, 241 .display.has_overlay = 1, 242 .display.overlay_needs_physical = 1, 243 .hws_needs_physical = 1, 244 .unfenced_needs_alignment = 1, 245 }; 246 247 static const struct intel_device_info i915gm_info = { 248 GEN3_FEATURES, 249 PLATFORM(INTEL_I915GM), 250 .is_mobile = 1, 251 .display.cursor_needs_physical = 1, 252 .display.has_overlay = 1, 253 .display.overlay_needs_physical = 1, 254 .display.supports_tv = 1, 255 .display.has_fbc = 1, 256 .hws_needs_physical = 1, 257 .unfenced_needs_alignment = 1, 258 }; 259 260 static const struct intel_device_info i945g_info = { 261 GEN3_FEATURES, 262 PLATFORM(INTEL_I945G), 263 .display.has_hotplug = 1, 264 .display.cursor_needs_physical = 1, 265 .display.has_overlay = 1, 266 .display.overlay_needs_physical = 1, 267 .hws_needs_physical = 1, 268 .unfenced_needs_alignment = 1, 269 }; 270 271 static const struct intel_device_info i945gm_info = { 272 GEN3_FEATURES, 273 PLATFORM(INTEL_I945GM), 274 .is_mobile = 1, 275 .display.has_hotplug = 1, 276 .display.cursor_needs_physical = 1, 277 .display.has_overlay = 1, 278 .display.overlay_needs_physical = 1, 279 .display.supports_tv = 1, 280 .display.has_fbc = 1, 281 .hws_needs_physical = 1, 282 .unfenced_needs_alignment = 1, 283 }; 284 285 static const struct intel_device_info g33_info = { 286 GEN3_FEATURES, 287 PLATFORM(INTEL_G33), 288 .display.has_hotplug = 1, 289 .display.has_overlay = 1, 290 }; 291 292 static const struct intel_device_info pnv_g_info = { 293 GEN3_FEATURES, 294 PLATFORM(INTEL_PINEVIEW), 295 .display.has_hotplug = 1, 296 .display.has_overlay = 1, 297 }; 298 299 static const struct intel_device_info pnv_m_info = { 300 GEN3_FEATURES, 301 PLATFORM(INTEL_PINEVIEW), 302 .is_mobile = 1, 303 .display.has_hotplug = 1, 304 .display.has_overlay = 1, 305 }; 306 307 #define GEN4_FEATURES \ 308 GEN(4), \ 309 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 310 .display.has_hotplug = 1, \ 311 .display.has_gmch = 1, \ 312 .gpu_reset_clobbers_display = true, \ 313 .engine_mask = BIT(RCS0), \ 314 .has_snoop = true, \ 315 .has_coherent_ggtt = true, \ 316 I9XX_PIPE_OFFSETS, \ 317 I9XX_CURSOR_OFFSETS, \ 318 I965_COLORS, \ 319 GEN_DEFAULT_PAGE_SIZES, \ 320 GEN_DEFAULT_REGIONS 321 322 static const struct intel_device_info i965g_info = { 323 GEN4_FEATURES, 324 PLATFORM(INTEL_I965G), 325 .display.has_overlay = 1, 326 .hws_needs_physical = 1, 327 .has_snoop = false, 328 }; 329 330 static const struct intel_device_info i965gm_info = { 331 GEN4_FEATURES, 332 PLATFORM(INTEL_I965GM), 333 .is_mobile = 1, 334 .display.has_fbc = 1, 335 .display.has_overlay = 1, 336 .display.supports_tv = 1, 337 .hws_needs_physical = 1, 338 .has_snoop = false, 339 }; 340 341 static const struct intel_device_info g45_info = { 342 GEN4_FEATURES, 343 PLATFORM(INTEL_G45), 344 .engine_mask = BIT(RCS0) | BIT(VCS0), 345 .gpu_reset_clobbers_display = false, 346 }; 347 348 static const struct intel_device_info gm45_info = { 349 GEN4_FEATURES, 350 PLATFORM(INTEL_GM45), 351 .is_mobile = 1, 352 .display.has_fbc = 1, 353 .display.supports_tv = 1, 354 .engine_mask = BIT(RCS0) | BIT(VCS0), 355 .gpu_reset_clobbers_display = false, 356 }; 357 358 #define GEN5_FEATURES \ 359 GEN(5), \ 360 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 361 .display.has_hotplug = 1, \ 362 .engine_mask = BIT(RCS0) | BIT(VCS0), \ 363 .has_snoop = true, \ 364 .has_coherent_ggtt = true, \ 365 /* ilk does support rc6, but we do not implement [power] contexts */ \ 366 .has_rc6 = 0, \ 367 I9XX_PIPE_OFFSETS, \ 368 I9XX_CURSOR_OFFSETS, \ 369 ILK_COLORS, \ 370 GEN_DEFAULT_PAGE_SIZES, \ 371 GEN_DEFAULT_REGIONS 372 373 static const struct intel_device_info ilk_d_info = { 374 GEN5_FEATURES, 375 PLATFORM(INTEL_IRONLAKE), 376 }; 377 378 static const struct intel_device_info ilk_m_info = { 379 GEN5_FEATURES, 380 PLATFORM(INTEL_IRONLAKE), 381 .is_mobile = 1, 382 .display.has_fbc = 1, 383 }; 384 385 #define GEN6_FEATURES \ 386 GEN(6), \ 387 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 388 .display.has_hotplug = 1, \ 389 .display.has_fbc = 1, \ 390 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \ 391 .has_coherent_ggtt = true, \ 392 .has_llc = 1, \ 393 .has_rc6 = 1, \ 394 .has_rc6p = 1, \ 395 .has_rps = true, \ 396 .ppgtt_type = INTEL_PPGTT_ALIASING, \ 397 .ppgtt_size = 31, \ 398 I9XX_PIPE_OFFSETS, \ 399 I9XX_CURSOR_OFFSETS, \ 400 ILK_COLORS, \ 401 GEN_DEFAULT_PAGE_SIZES, \ 402 GEN_DEFAULT_REGIONS 403 404 #define SNB_D_PLATFORM \ 405 GEN6_FEATURES, \ 406 PLATFORM(INTEL_SANDYBRIDGE) 407 408 static const struct intel_device_info snb_d_gt1_info = { 409 SNB_D_PLATFORM, 410 .gt = 1, 411 }; 412 413 static const struct intel_device_info snb_d_gt2_info = { 414 SNB_D_PLATFORM, 415 .gt = 2, 416 }; 417 418 #define SNB_M_PLATFORM \ 419 GEN6_FEATURES, \ 420 PLATFORM(INTEL_SANDYBRIDGE), \ 421 .is_mobile = 1 422 423 424 static const struct intel_device_info snb_m_gt1_info = { 425 SNB_M_PLATFORM, 426 .gt = 1, 427 }; 428 429 static const struct intel_device_info snb_m_gt2_info = { 430 SNB_M_PLATFORM, 431 .gt = 2, 432 }; 433 434 #define GEN7_FEATURES \ 435 GEN(7), \ 436 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \ 437 .display.has_hotplug = 1, \ 438 .display.has_fbc = 1, \ 439 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \ 440 .has_coherent_ggtt = true, \ 441 .has_llc = 1, \ 442 .has_rc6 = 1, \ 443 .has_rc6p = 1, \ 444 .has_rps = true, \ 445 .ppgtt_type = INTEL_PPGTT_ALIASING, \ 446 .ppgtt_size = 31, \ 447 IVB_PIPE_OFFSETS, \ 448 IVB_CURSOR_OFFSETS, \ 449 IVB_COLORS, \ 450 GEN_DEFAULT_PAGE_SIZES, \ 451 GEN_DEFAULT_REGIONS 452 453 #define IVB_D_PLATFORM \ 454 GEN7_FEATURES, \ 455 PLATFORM(INTEL_IVYBRIDGE), \ 456 .has_l3_dpf = 1 457 458 static const struct intel_device_info ivb_d_gt1_info = { 459 IVB_D_PLATFORM, 460 .gt = 1, 461 }; 462 463 static const struct intel_device_info ivb_d_gt2_info = { 464 IVB_D_PLATFORM, 465 .gt = 2, 466 }; 467 468 #define IVB_M_PLATFORM \ 469 GEN7_FEATURES, \ 470 PLATFORM(INTEL_IVYBRIDGE), \ 471 .is_mobile = 1, \ 472 .has_l3_dpf = 1 473 474 static const struct intel_device_info ivb_m_gt1_info = { 475 IVB_M_PLATFORM, 476 .gt = 1, 477 }; 478 479 static const struct intel_device_info ivb_m_gt2_info = { 480 IVB_M_PLATFORM, 481 .gt = 2, 482 }; 483 484 static const struct intel_device_info ivb_q_info = { 485 GEN7_FEATURES, 486 PLATFORM(INTEL_IVYBRIDGE), 487 .gt = 2, 488 .pipe_mask = 0, /* legal, last one wins */ 489 .has_l3_dpf = 1, 490 }; 491 492 static const struct intel_device_info vlv_info = { 493 PLATFORM(INTEL_VALLEYVIEW), 494 GEN(7), 495 .is_lp = 1, 496 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), 497 .has_runtime_pm = 1, 498 .has_rc6 = 1, 499 .has_rps = true, 500 .display.has_gmch = 1, 501 .display.has_hotplug = 1, 502 .ppgtt_type = INTEL_PPGTT_ALIASING, 503 .ppgtt_size = 31, 504 .has_snoop = true, 505 .has_coherent_ggtt = false, 506 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), 507 .display_mmio_offset = VLV_DISPLAY_BASE, 508 I9XX_PIPE_OFFSETS, 509 I9XX_CURSOR_OFFSETS, 510 I965_COLORS, 511 GEN_DEFAULT_PAGE_SIZES, 512 GEN_DEFAULT_REGIONS, 513 }; 514 515 #define G75_FEATURES \ 516 GEN7_FEATURES, \ 517 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \ 518 .display.has_ddi = 1, \ 519 .has_fpga_dbg = 1, \ 520 .display.has_psr = 1, \ 521 .display.has_dp_mst = 1, \ 522 .has_rc6p = 0 /* RC6p removed-by HSW */, \ 523 HSW_PIPE_OFFSETS, \ 524 .has_runtime_pm = 1 525 526 #define HSW_PLATFORM \ 527 G75_FEATURES, \ 528 PLATFORM(INTEL_HASWELL), \ 529 .has_l3_dpf = 1 530 531 static const struct intel_device_info hsw_gt1_info = { 532 HSW_PLATFORM, 533 .gt = 1, 534 }; 535 536 static const struct intel_device_info hsw_gt2_info = { 537 HSW_PLATFORM, 538 .gt = 2, 539 }; 540 541 static const struct intel_device_info hsw_gt3_info = { 542 HSW_PLATFORM, 543 .gt = 3, 544 }; 545 546 #define GEN8_FEATURES \ 547 G75_FEATURES, \ 548 GEN(8), \ 549 .has_logical_ring_contexts = 1, \ 550 .ppgtt_type = INTEL_PPGTT_FULL, \ 551 .ppgtt_size = 48, \ 552 .has_64bit_reloc = 1, \ 553 .has_reset_engine = 1 554 555 #define BDW_PLATFORM \ 556 GEN8_FEATURES, \ 557 PLATFORM(INTEL_BROADWELL) 558 559 static const struct intel_device_info bdw_gt1_info = { 560 BDW_PLATFORM, 561 .gt = 1, 562 }; 563 564 static const struct intel_device_info bdw_gt2_info = { 565 BDW_PLATFORM, 566 .gt = 2, 567 }; 568 569 static const struct intel_device_info bdw_rsvd_info = { 570 BDW_PLATFORM, 571 .gt = 3, 572 /* According to the device ID those devices are GT3, they were 573 * previously treated as not GT3, keep it like that. 574 */ 575 }; 576 577 static const struct intel_device_info bdw_gt3_info = { 578 BDW_PLATFORM, 579 .gt = 3, 580 .engine_mask = 581 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), 582 }; 583 584 static const struct intel_device_info chv_info = { 585 PLATFORM(INTEL_CHERRYVIEW), 586 GEN(8), 587 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 588 .display.has_hotplug = 1, 589 .is_lp = 1, 590 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), 591 .has_64bit_reloc = 1, 592 .has_runtime_pm = 1, 593 .has_rc6 = 1, 594 .has_rps = true, 595 .has_logical_ring_contexts = 1, 596 .display.has_gmch = 1, 597 .ppgtt_type = INTEL_PPGTT_ALIASING, 598 .ppgtt_size = 32, 599 .has_reset_engine = 1, 600 .has_snoop = true, 601 .has_coherent_ggtt = false, 602 .display_mmio_offset = VLV_DISPLAY_BASE, 603 CHV_PIPE_OFFSETS, 604 CHV_CURSOR_OFFSETS, 605 CHV_COLORS, 606 GEN_DEFAULT_PAGE_SIZES, 607 GEN_DEFAULT_REGIONS, 608 }; 609 610 #define GEN9_DEFAULT_PAGE_SIZES \ 611 .page_sizes = I915_GTT_PAGE_SIZE_4K | \ 612 I915_GTT_PAGE_SIZE_64K 613 614 #define GEN9_FEATURES \ 615 GEN8_FEATURES, \ 616 GEN(9), \ 617 GEN9_DEFAULT_PAGE_SIZES, \ 618 .has_logical_ring_preemption = 1, \ 619 .display.has_csr = 1, \ 620 .has_gt_uc = 1, \ 621 .display.has_hdcp = 1, \ 622 .display.has_ipc = 1, \ 623 .ddb_size = 896 624 625 #define SKL_PLATFORM \ 626 GEN9_FEATURES, \ 627 PLATFORM(INTEL_SKYLAKE) 628 629 static const struct intel_device_info skl_gt1_info = { 630 SKL_PLATFORM, 631 .gt = 1, 632 }; 633 634 static const struct intel_device_info skl_gt2_info = { 635 SKL_PLATFORM, 636 .gt = 2, 637 }; 638 639 #define SKL_GT3_PLUS_PLATFORM \ 640 SKL_PLATFORM, \ 641 .engine_mask = \ 642 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1) 643 644 645 static const struct intel_device_info skl_gt3_info = { 646 SKL_GT3_PLUS_PLATFORM, 647 .gt = 3, 648 }; 649 650 static const struct intel_device_info skl_gt4_info = { 651 SKL_GT3_PLUS_PLATFORM, 652 .gt = 4, 653 }; 654 655 #define GEN9_LP_FEATURES \ 656 GEN(9), \ 657 .is_lp = 1, \ 658 .display.has_hotplug = 1, \ 659 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \ 660 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \ 661 .has_64bit_reloc = 1, \ 662 .display.has_ddi = 1, \ 663 .has_fpga_dbg = 1, \ 664 .display.has_fbc = 1, \ 665 .display.has_hdcp = 1, \ 666 .display.has_psr = 1, \ 667 .has_runtime_pm = 1, \ 668 .display.has_csr = 1, \ 669 .has_rc6 = 1, \ 670 .has_rps = true, \ 671 .display.has_dp_mst = 1, \ 672 .has_logical_ring_contexts = 1, \ 673 .has_logical_ring_preemption = 1, \ 674 .has_gt_uc = 1, \ 675 .ppgtt_type = INTEL_PPGTT_FULL, \ 676 .ppgtt_size = 48, \ 677 .has_reset_engine = 1, \ 678 .has_snoop = true, \ 679 .has_coherent_ggtt = false, \ 680 .display.has_ipc = 1, \ 681 HSW_PIPE_OFFSETS, \ 682 IVB_CURSOR_OFFSETS, \ 683 IVB_COLORS, \ 684 GEN9_DEFAULT_PAGE_SIZES, \ 685 GEN_DEFAULT_REGIONS 686 687 static const struct intel_device_info bxt_info = { 688 GEN9_LP_FEATURES, 689 PLATFORM(INTEL_BROXTON), 690 .ddb_size = 512, 691 }; 692 693 static const struct intel_device_info glk_info = { 694 GEN9_LP_FEATURES, 695 PLATFORM(INTEL_GEMINILAKE), 696 .ddb_size = 1024, 697 GLK_COLORS, 698 }; 699 700 #define KBL_PLATFORM \ 701 GEN9_FEATURES, \ 702 PLATFORM(INTEL_KABYLAKE) 703 704 static const struct intel_device_info kbl_gt1_info = { 705 KBL_PLATFORM, 706 .gt = 1, 707 }; 708 709 static const struct intel_device_info kbl_gt2_info = { 710 KBL_PLATFORM, 711 .gt = 2, 712 }; 713 714 static const struct intel_device_info kbl_gt3_info = { 715 KBL_PLATFORM, 716 .gt = 3, 717 .engine_mask = 718 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), 719 }; 720 721 #define CFL_PLATFORM \ 722 GEN9_FEATURES, \ 723 PLATFORM(INTEL_COFFEELAKE) 724 725 static const struct intel_device_info cfl_gt1_info = { 726 CFL_PLATFORM, 727 .gt = 1, 728 }; 729 730 static const struct intel_device_info cfl_gt2_info = { 731 CFL_PLATFORM, 732 .gt = 2, 733 }; 734 735 static const struct intel_device_info cfl_gt3_info = { 736 CFL_PLATFORM, 737 .gt = 3, 738 .engine_mask = 739 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), 740 }; 741 742 #define GEN10_FEATURES \ 743 GEN9_FEATURES, \ 744 GEN(10), \ 745 .ddb_size = 1024, \ 746 .display.has_dsc = 1, \ 747 .has_coherent_ggtt = false, \ 748 GLK_COLORS 749 750 static const struct intel_device_info cnl_info = { 751 GEN10_FEATURES, 752 PLATFORM(INTEL_CANNONLAKE), 753 .gt = 2, 754 }; 755 756 #define GEN11_DEFAULT_PAGE_SIZES \ 757 .page_sizes = I915_GTT_PAGE_SIZE_4K | \ 758 I915_GTT_PAGE_SIZE_64K | \ 759 I915_GTT_PAGE_SIZE_2M 760 761 #define GEN11_FEATURES \ 762 GEN10_FEATURES, \ 763 GEN11_DEFAULT_PAGE_SIZES, \ 764 .pipe_offsets = { \ 765 [TRANSCODER_A] = PIPE_A_OFFSET, \ 766 [TRANSCODER_B] = PIPE_B_OFFSET, \ 767 [TRANSCODER_C] = PIPE_C_OFFSET, \ 768 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \ 769 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \ 770 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \ 771 }, \ 772 .trans_offsets = { \ 773 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 774 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 775 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 776 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \ 777 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \ 778 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \ 779 }, \ 780 GEN(11), \ 781 .ddb_size = 2048, \ 782 .has_logical_ring_elsq = 1, \ 783 .color = { .degamma_lut_size = 33, .gamma_lut_size = 262145 } 784 785 static const struct intel_device_info icl_info = { 786 GEN11_FEATURES, 787 PLATFORM(INTEL_ICELAKE), 788 .engine_mask = 789 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), 790 }; 791 792 static const struct intel_device_info ehl_info = { 793 GEN11_FEATURES, 794 PLATFORM(INTEL_ELKHARTLAKE), 795 .require_force_probe = 1, 796 .engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0), 797 .ppgtt_size = 36, 798 }; 799 800 #define GEN12_FEATURES \ 801 GEN11_FEATURES, \ 802 GEN(12), \ 803 .pipe_offsets = { \ 804 [TRANSCODER_A] = PIPE_A_OFFSET, \ 805 [TRANSCODER_B] = PIPE_B_OFFSET, \ 806 [TRANSCODER_C] = PIPE_C_OFFSET, \ 807 [TRANSCODER_D] = PIPE_D_OFFSET, \ 808 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \ 809 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \ 810 }, \ 811 .trans_offsets = { \ 812 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 813 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 814 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 815 [TRANSCODER_D] = TRANSCODER_D_OFFSET, \ 816 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \ 817 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \ 818 }, \ 819 TGL_CURSOR_OFFSETS, \ 820 .has_global_mocs = 1, \ 821 .display.has_dsb = 1 822 823 static const struct intel_device_info tgl_info = { 824 GEN12_FEATURES, 825 PLATFORM(INTEL_TIGERLAKE), 826 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), 827 .require_force_probe = 1, 828 .display.has_modular_fia = 1, 829 .engine_mask = 830 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), 831 .has_rps = false, /* XXX disabled for debugging */ 832 }; 833 834 #define GEN12_DGFX_FEATURES \ 835 GEN12_FEATURES, \ 836 .is_dgfx = 1 837 838 #undef GEN 839 #undef PLATFORM 840 841 /* 842 * Make sure any device matches here are from most specific to most 843 * general. For example, since the Quanta match is based on the subsystem 844 * and subvendor IDs, we need it to come before the more general IVB 845 * PCI ID matches, otherwise we'll use the wrong info struct above. 846 */ 847 static const struct pci_device_id pciidlist[] = { 848 INTEL_I830_IDS(&i830_info), 849 INTEL_I845G_IDS(&i845g_info), 850 INTEL_I85X_IDS(&i85x_info), 851 INTEL_I865G_IDS(&i865g_info), 852 INTEL_I915G_IDS(&i915g_info), 853 INTEL_I915GM_IDS(&i915gm_info), 854 INTEL_I945G_IDS(&i945g_info), 855 INTEL_I945GM_IDS(&i945gm_info), 856 INTEL_I965G_IDS(&i965g_info), 857 INTEL_G33_IDS(&g33_info), 858 INTEL_I965GM_IDS(&i965gm_info), 859 INTEL_GM45_IDS(&gm45_info), 860 INTEL_G45_IDS(&g45_info), 861 INTEL_PINEVIEW_G_IDS(&pnv_g_info), 862 INTEL_PINEVIEW_M_IDS(&pnv_m_info), 863 INTEL_IRONLAKE_D_IDS(&ilk_d_info), 864 INTEL_IRONLAKE_M_IDS(&ilk_m_info), 865 INTEL_SNB_D_GT1_IDS(&snb_d_gt1_info), 866 INTEL_SNB_D_GT2_IDS(&snb_d_gt2_info), 867 INTEL_SNB_M_GT1_IDS(&snb_m_gt1_info), 868 INTEL_SNB_M_GT2_IDS(&snb_m_gt2_info), 869 INTEL_IVB_Q_IDS(&ivb_q_info), /* must be first IVB */ 870 INTEL_IVB_M_GT1_IDS(&ivb_m_gt1_info), 871 INTEL_IVB_M_GT2_IDS(&ivb_m_gt2_info), 872 INTEL_IVB_D_GT1_IDS(&ivb_d_gt1_info), 873 INTEL_IVB_D_GT2_IDS(&ivb_d_gt2_info), 874 INTEL_HSW_GT1_IDS(&hsw_gt1_info), 875 INTEL_HSW_GT2_IDS(&hsw_gt2_info), 876 INTEL_HSW_GT3_IDS(&hsw_gt3_info), 877 INTEL_VLV_IDS(&vlv_info), 878 INTEL_BDW_GT1_IDS(&bdw_gt1_info), 879 INTEL_BDW_GT2_IDS(&bdw_gt2_info), 880 INTEL_BDW_GT3_IDS(&bdw_gt3_info), 881 INTEL_BDW_RSVD_IDS(&bdw_rsvd_info), 882 INTEL_CHV_IDS(&chv_info), 883 INTEL_SKL_GT1_IDS(&skl_gt1_info), 884 INTEL_SKL_GT2_IDS(&skl_gt2_info), 885 INTEL_SKL_GT3_IDS(&skl_gt3_info), 886 INTEL_SKL_GT4_IDS(&skl_gt4_info), 887 INTEL_BXT_IDS(&bxt_info), 888 INTEL_GLK_IDS(&glk_info), 889 INTEL_KBL_GT1_IDS(&kbl_gt1_info), 890 INTEL_KBL_GT2_IDS(&kbl_gt2_info), 891 INTEL_KBL_GT3_IDS(&kbl_gt3_info), 892 INTEL_KBL_GT4_IDS(&kbl_gt3_info), 893 INTEL_AML_KBL_GT2_IDS(&kbl_gt2_info), 894 INTEL_CFL_S_GT1_IDS(&cfl_gt1_info), 895 INTEL_CFL_S_GT2_IDS(&cfl_gt2_info), 896 INTEL_CFL_H_GT1_IDS(&cfl_gt1_info), 897 INTEL_CFL_H_GT2_IDS(&cfl_gt2_info), 898 INTEL_CFL_U_GT2_IDS(&cfl_gt2_info), 899 INTEL_CFL_U_GT3_IDS(&cfl_gt3_info), 900 INTEL_WHL_U_GT1_IDS(&cfl_gt1_info), 901 INTEL_WHL_U_GT2_IDS(&cfl_gt2_info), 902 INTEL_AML_CFL_GT2_IDS(&cfl_gt2_info), 903 INTEL_WHL_U_GT3_IDS(&cfl_gt3_info), 904 INTEL_CML_GT1_IDS(&cfl_gt1_info), 905 INTEL_CML_GT2_IDS(&cfl_gt2_info), 906 INTEL_CML_U_GT1_IDS(&cfl_gt1_info), 907 INTEL_CML_U_GT2_IDS(&cfl_gt2_info), 908 INTEL_CNL_IDS(&cnl_info), 909 INTEL_ICL_11_IDS(&icl_info), 910 INTEL_EHL_IDS(&ehl_info), 911 INTEL_TGL_12_IDS(&tgl_info), 912 {0, 0, 0} 913 }; 914 MODULE_DEVICE_TABLE(pci, pciidlist); 915 916 #ifdef __NetBSD__ 917 918 /* XXX Kludge to expose this to NetBSD driver attachment goop. */ 919 const struct pci_device_id *const i915_device_ids = pciidlist; 920 const size_t i915_n_device_ids = __arraycount(pciidlist); 921 922 #else 923 static void i915_pci_remove(struct pci_dev *pdev) 924 { 925 struct drm_i915_private *i915; 926 927 i915 = pci_get_drvdata(pdev); 928 if (!i915) /* driver load aborted, nothing to cleanup */ 929 return; 930 931 i915_driver_remove(i915); 932 pci_set_drvdata(pdev, NULL); 933 934 drm_dev_put(&i915->drm); 935 } 936 937 /* is device_id present in comma separated list of ids */ 938 static bool force_probe(u16 device_id, const char *devices) 939 { 940 char *s, *p, *tok; 941 bool ret; 942 943 /* FIXME: transitional */ 944 if (i915_modparams.alpha_support) { 945 DRM_INFO("i915.alpha_support is deprecated, use i915.force_probe=%04x instead\n", 946 device_id); 947 return true; 948 } 949 950 if (!devices || !*devices) 951 return false; 952 953 /* match everything */ 954 if (strcmp(devices, "*") == 0) 955 return true; 956 957 s = kstrdup(devices, GFP_KERNEL); 958 if (!s) 959 return false; 960 961 for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) { 962 u16 val; 963 964 if (kstrtou16(tok, 16, &val) == 0 && val == device_id) { 965 ret = true; 966 break; 967 } 968 } 969 970 kfree(s); 971 972 return ret; 973 } 974 975 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 976 { 977 struct intel_device_info *intel_info = 978 (struct intel_device_info *) ent->driver_data; 979 int err; 980 981 if (intel_info->require_force_probe && 982 !force_probe(pdev->device, i915_modparams.force_probe)) { 983 DRM_INFO("Your graphics device %04x is not properly supported by the driver in this\n" 984 "kernel version. To force driver probe anyway, use i915.force_probe=%04x\n" 985 "module parameter or CONFIG_DRM_I915_FORCE_PROBE=%04x configuration option,\n" 986 "or (recommended) check for kernel updates.\n", 987 pdev->device, pdev->device, pdev->device); 988 return -ENODEV; 989 } 990 991 /* Only bind to function 0 of the device. Early generations 992 * used function 1 as a placeholder for multi-head. This causes 993 * us confusion instead, especially on the systems where both 994 * functions have the same PCI-ID! 995 */ 996 if (PCI_FUNC(pdev->devfn)) 997 return -ENODEV; 998 999 #ifndef __NetBSD__ /* XXX vga switcheroo */ 1000 /* 1001 * apple-gmux is needed on dual GPU MacBook Pro 1002 * to probe the panel if we're the inactive GPU. 1003 */ 1004 if (vga_switcheroo_client_probe_defer(pdev)) 1005 return -EPROBE_DEFER; 1006 #endif 1007 1008 err = i915_driver_probe(pdev, ent); 1009 if (err) 1010 return err; 1011 1012 if (i915_inject_probe_failure(pci_get_drvdata(pdev))) { 1013 i915_pci_remove(pdev); 1014 return -ENODEV; 1015 } 1016 1017 err = i915_live_selftests(pdev); 1018 if (err) { 1019 i915_pci_remove(pdev); 1020 return err > 0 ? -ENOTTY : err; 1021 } 1022 1023 err = i915_perf_selftests(pdev); 1024 if (err) { 1025 i915_pci_remove(pdev); 1026 return err > 0 ? -ENOTTY : err; 1027 } 1028 1029 return 0; 1030 } 1031 1032 #ifndef __NetBSD__ 1033 static struct pci_driver i915_pci_driver = { 1034 .name = DRIVER_NAME, 1035 .id_table = pciidlist, 1036 .probe = i915_pci_probe, 1037 .remove = i915_pci_remove, 1038 .driver.pm = &i915_pm_ops, 1039 }; 1040 #endif 1041 1042 static int __init i915_init(void) 1043 { 1044 bool use_kms = true; 1045 int err; 1046 1047 err = i915_globals_init(); 1048 if (err) 1049 return err; 1050 1051 err = i915_mock_selftests(); 1052 if (err) 1053 return err > 0 ? 0 : err; 1054 1055 /* 1056 * Enable KMS by default, unless explicitly overriden by 1057 * either the i915.modeset prarameter or by the 1058 * vga_text_mode_force boot option. 1059 */ 1060 1061 if (i915_modparams.modeset == 0) 1062 use_kms = false; 1063 1064 if (vgacon_text_force() && i915_modparams.modeset == -1) 1065 use_kms = false; 1066 1067 if (!use_kms) { 1068 /* Silently fail loading to not upset userspace. */ 1069 DRM_DEBUG_DRIVER("KMS disabled.\n"); 1070 return 0; 1071 } 1072 1073 err = pci_register_driver(&i915_pci_driver); 1074 if (err) 1075 return err; 1076 1077 i915_perf_sysctl_register(); 1078 return 0; 1079 } 1080 1081 static void __exit i915_exit(void) 1082 { 1083 if (!i915_pci_driver.driver.owner) 1084 return; 1085 1086 i915_perf_sysctl_unregister(); 1087 pci_unregister_driver(&i915_pci_driver); 1088 i915_globals_exit(); 1089 } 1090 1091 module_init(i915_init); 1092 module_exit(i915_exit); 1093 1094 #endif 1095 1096 MODULE_AUTHOR("Tungsten Graphics, Inc."); 1097 MODULE_AUTHOR("Intel Corporation"); 1098 1099 MODULE_DESCRIPTION(DRIVER_DESC); 1100 MODULE_LICENSE("GPL and additional rights"); 1101
Indexes created Sat Sep 20 22:09:52 GMT 2025