1 /* $NetBSD: amdgpu_dm.c,v 1.5 2021/12/26 21:00:14 riastradh Exp $ */ 2 3 /* 4 * Copyright 2015 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: AMD 25 * 26 */ 27 28 /* The caprices of the preprocessor require that this be declared right here */ 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: amdgpu_dm.c,v 1.5 2021/12/26 21:00:14 riastradh Exp $"); 31 32 #define CREATE_TRACE_POINTS 33 34 #include "dm_services_types.h" 35 #include "dc.h" 36 #include "dc/inc/core_types.h" 37 #include "dal_asic_id.h" 38 #include "dmub/inc/dmub_srv.h" 39 #include "dc/inc/hw/dmcu.h" 40 #include "dc/inc/hw/abm.h" 41 #include "dc/dc_dmub_srv.h" 42 43 #include "vid.h" 44 #include "amdgpu.h" 45 #include "amdgpu_display.h" 46 #include "amdgpu_ucode.h" 47 #include "atom.h" 48 #include "amdgpu_dm.h" 49 #ifdef CONFIG_DRM_AMD_DC_HDCP 50 #include "amdgpu_dm_hdcp.h" 51 #include <drm/drm_hdcp.h> 52 #endif 53 #include "amdgpu_pm.h" 54 55 #include "amd_shared.h" 56 #include "amdgpu_dm_irq.h" 57 #include "dm_helpers.h" 58 #include "amdgpu_dm_mst_types.h" 59 #if defined(CONFIG_DEBUG_FS) 60 #include "amdgpu_dm_debugfs.h" 61 #endif 62 63 #include "ivsrcid/ivsrcid_vislands30.h" 64 65 #include <linux/module.h> 66 #include <linux/moduleparam.h> 67 #include <linux/version.h> 68 #include <linux/types.h> 69 #include <linux/pm_runtime.h> 70 #include <linux/pci.h> 71 #include <linux/firmware.h> 72 #include <linux/component.h> 73 74 #include <drm/drm_atomic.h> 75 #include <drm/drm_atomic_uapi.h> 76 #include <drm/drm_atomic_helper.h> 77 #include <drm/drm_dp_mst_helper.h> 78 #include <drm/drm_fb_helper.h> 79 #include <drm/drm_fourcc.h> 80 #include <drm/drm_edid.h> 81 #include <drm/drm_vblank.h> 82 #include <drm/drm_audio_component.h> 83 #include <drm/drm_hdcp.h> 84 85 #if defined(CONFIG_DRM_AMD_DC_DCN) 86 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h" 87 88 #include "dcn/dcn_1_0_offset.h" 89 #include "dcn/dcn_1_0_sh_mask.h" 90 #include "soc15_hw_ip.h" 91 #include "vega10_ip_offset.h" 92 93 #include "soc15_common.h" 94 #endif 95 96 #include "modules/inc/mod_freesync.h" 97 #include "modules/power/power_helpers.h" 98 #include "modules/inc/mod_info_packet.h" 99 100 #include <linux/nbsd-namespace.h> 101 102 #define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin" 103 MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB); 104 105 #define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin" 106 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU); 107 108 /* Number of bytes in PSP header for firmware. */ 109 #define PSP_HEADER_BYTES 0x100 110 111 /* Number of bytes in PSP footer for firmware. */ 112 #define PSP_FOOTER_BYTES 0x100 113 114 /** 115 * DOC: overview 116 * 117 * The AMDgpu display manager, **amdgpu_dm** (or even simpler, 118 * **dm**) sits between DRM and DC. It acts as a liason, converting DRM 119 * requests into DC requests, and DC responses into DRM responses. 120 * 121 * The root control structure is &struct amdgpu_display_manager. 122 */ 123 124 /* basic init/fini API */ 125 static int amdgpu_dm_init(struct amdgpu_device *adev); 126 static void amdgpu_dm_fini(struct amdgpu_device *adev); 127 128 /* 129 * initializes drm_device display related structures, based on the information 130 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector, 131 * drm_encoder, drm_mode_config 132 * 133 * Returns 0 on success 134 */ 135 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev); 136 /* removes and deallocates the drm structures, created by the above function */ 137 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm); 138 139 static void 140 amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector); 141 142 static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, 143 struct drm_plane *plane, 144 unsigned long possible_crtcs, 145 const struct dc_plane_cap *plane_cap); 146 static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, 147 struct drm_plane *plane, 148 uint32_t link_index); 149 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, 150 struct amdgpu_dm_connector *amdgpu_dm_connector, 151 uint32_t link_index, 152 struct amdgpu_encoder *amdgpu_encoder); 153 static int amdgpu_dm_encoder_init(struct drm_device *dev, 154 struct amdgpu_encoder *aencoder, 155 uint32_t link_index); 156 157 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector); 158 159 static int amdgpu_dm_atomic_commit(struct drm_device *dev, 160 struct drm_atomic_state *state, 161 bool nonblock); 162 163 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state); 164 165 static int amdgpu_dm_atomic_check(struct drm_device *dev, 166 struct drm_atomic_state *state); 167 168 static void handle_cursor_update(struct drm_plane *plane, 169 struct drm_plane_state *old_plane_state); 170 171 static void amdgpu_dm_set_psr_caps(struct dc_link *link); 172 static bool amdgpu_dm_psr_enable(struct dc_stream_state *stream); 173 static bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream); 174 static bool amdgpu_dm_psr_disable(struct dc_stream_state *stream); 175 176 177 /* 178 * dm_vblank_get_counter 179 * 180 * @brief 181 * Get counter for number of vertical blanks 182 * 183 * @param 184 * struct amdgpu_device *adev - [in] desired amdgpu device 185 * int disp_idx - [in] which CRTC to get the counter from 186 * 187 * @return 188 * Counter for vertical blanks 189 */ 190 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc) 191 { 192 if (crtc >= adev->mode_info.num_crtc) 193 return 0; 194 else { 195 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc]; 196 struct dm_crtc_state *acrtc_state = to_dm_crtc_state( 197 acrtc->base.state); 198 199 200 if (acrtc_state->stream == NULL) { 201 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n", 202 crtc); 203 return 0; 204 } 205 206 return dc_stream_get_vblank_counter(acrtc_state->stream); 207 } 208 } 209 210 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, 211 u32 *vbl, u32 *position) 212 { 213 uint32_t v_blank_start, v_blank_end, h_position, v_position; 214 215 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) 216 return -EINVAL; 217 else { 218 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc]; 219 struct dm_crtc_state *acrtc_state = to_dm_crtc_state( 220 acrtc->base.state); 221 222 if (acrtc_state->stream == NULL) { 223 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n", 224 crtc); 225 return 0; 226 } 227 228 /* 229 * TODO rework base driver to use values directly. 230 * for now parse it back into reg-format 231 */ 232 dc_stream_get_scanoutpos(acrtc_state->stream, 233 &v_blank_start, 234 &v_blank_end, 235 &h_position, 236 &v_position); 237 238 *position = v_position | (h_position << 16); 239 *vbl = v_blank_start | (v_blank_end << 16); 240 } 241 242 return 0; 243 } 244 245 static bool dm_is_idle(void *handle) 246 { 247 /* XXX todo */ 248 return true; 249 } 250 251 static int dm_wait_for_idle(void *handle) 252 { 253 /* XXX todo */ 254 return 0; 255 } 256 257 static bool dm_check_soft_reset(void *handle) 258 { 259 return false; 260 } 261 262 static int dm_soft_reset(void *handle) 263 { 264 /* XXX todo */ 265 return 0; 266 } 267 268 static struct amdgpu_crtc * 269 get_crtc_by_otg_inst(struct amdgpu_device *adev, 270 int otg_inst) 271 { 272 struct drm_device *dev = adev->ddev; 273 struct drm_crtc *crtc; 274 struct amdgpu_crtc *amdgpu_crtc; 275 276 if (otg_inst == -1) { 277 WARN_ON(1); 278 return adev->mode_info.crtcs[0]; 279 } 280 281 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 282 amdgpu_crtc = to_amdgpu_crtc(crtc); 283 284 if (amdgpu_crtc->otg_inst == otg_inst) 285 return amdgpu_crtc; 286 } 287 288 return NULL; 289 } 290 291 static inline bool amdgpu_dm_vrr_active(struct dm_crtc_state *dm_state) 292 { 293 return dm_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE || 294 dm_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED; 295 } 296 297 /** 298 * dm_pflip_high_irq() - Handle pageflip interrupt 299 * @interrupt_params: ignored 300 * 301 * Handles the pageflip interrupt by notifying all interested parties 302 * that the pageflip has been completed. 303 */ 304 static void dm_pflip_high_irq(void *interrupt_params) 305 { 306 struct amdgpu_crtc *amdgpu_crtc; 307 struct common_irq_params *irq_params = interrupt_params; 308 struct amdgpu_device *adev = irq_params->adev; 309 unsigned long flags; 310 struct drm_pending_vblank_event *e; 311 struct dm_crtc_state *acrtc_state; 312 uint32_t vpos, hpos, v_blank_start, v_blank_end; 313 bool vrr_active; 314 315 amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP); 316 317 /* IRQ could occur when in initial stage */ 318 /* TODO work and BO cleanup */ 319 if (amdgpu_crtc == NULL) { 320 DRM_DEBUG_DRIVER("CRTC is null, returning.\n"); 321 return; 322 } 323 324 spin_lock_irqsave(&adev->ddev->event_lock, flags); 325 326 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){ 327 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n", 328 amdgpu_crtc->pflip_status, 329 AMDGPU_FLIP_SUBMITTED, 330 amdgpu_crtc->crtc_id, 331 amdgpu_crtc); 332 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 333 return; 334 } 335 336 /* page flip completed. */ 337 e = amdgpu_crtc->event; 338 amdgpu_crtc->event = NULL; 339 340 if (!e) 341 WARN_ON(1); 342 343 acrtc_state = to_dm_crtc_state(amdgpu_crtc->base.state); 344 vrr_active = amdgpu_dm_vrr_active(acrtc_state); 345 346 /* Fixed refresh rate, or VRR scanout position outside front-porch? */ 347 if (!vrr_active || 348 !dc_stream_get_scanoutpos(acrtc_state->stream, &v_blank_start, 349 &v_blank_end, &hpos, &vpos) || 350 (vpos < v_blank_start)) { 351 /* Update to correct count and vblank timestamp if racing with 352 * vblank irq. This also updates to the correct vblank timestamp 353 * even in VRR mode, as scanout is past the front-porch atm. 354 */ 355 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base); 356 357 /* Wake up userspace by sending the pageflip event with proper 358 * count and timestamp of vblank of flip completion. 359 */ 360 if (e) { 361 drm_crtc_send_vblank_event(&amdgpu_crtc->base, e); 362 363 /* Event sent, so done with vblank for this flip */ 364 drm_crtc_vblank_put_locked(&amdgpu_crtc->base); 365 } 366 } else if (e) { 367 /* VRR active and inside front-porch: vblank count and 368 * timestamp for pageflip event will only be up to date after 369 * drm_crtc_handle_vblank() has been executed from late vblank 370 * irq handler after start of back-porch (vline 0). We queue the 371 * pageflip event for send-out by drm_crtc_handle_vblank() with 372 * updated timestamp and count, once it runs after us. 373 * 374 * We need to open-code this instead of using the helper 375 * drm_crtc_arm_vblank_event(), as that helper would 376 * call drm_crtc_accurate_vblank_count(), which we must 377 * not call in VRR mode while we are in front-porch! 378 */ 379 380 /* sequence will be replaced by real count during send-out. */ 381 e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base); 382 e->pipe = amdgpu_crtc->crtc_id; 383 384 list_add_tail(&e->base.link, &adev->ddev->vblank_event_list); 385 e = NULL; 386 } 387 388 /* Keep track of vblank of this flip for flip throttling. We use the 389 * cooked hw counter, as that one incremented at start of this vblank 390 * of pageflip completion, so last_flip_vblank is the forbidden count 391 * for queueing new pageflips if vsync + VRR is enabled. 392 */ 393 amdgpu_crtc->last_flip_vblank = amdgpu_get_vblank_counter_kms(adev->ddev, 394 amdgpu_crtc->crtc_id); 395 396 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; 397 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 398 399 DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n", 400 amdgpu_crtc->crtc_id, amdgpu_crtc, 401 vrr_active, (int) !e); 402 } 403 404 static void dm_vupdate_high_irq(void *interrupt_params) 405 { 406 struct common_irq_params *irq_params = interrupt_params; 407 struct amdgpu_device *adev = irq_params->adev; 408 struct amdgpu_crtc *acrtc; 409 struct dm_crtc_state *acrtc_state; 410 unsigned long flags; 411 412 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE); 413 414 if (acrtc) { 415 acrtc_state = to_dm_crtc_state(acrtc->base.state); 416 417 DRM_DEBUG_DRIVER("crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id, 418 amdgpu_dm_vrr_active(acrtc_state)); 419 420 /* Core vblank handling is done here after end of front-porch in 421 * vrr mode, as vblank timestamping will give valid results 422 * while now done after front-porch. This will also deliver 423 * page-flip completion events that have been queued to us 424 * if a pageflip happened inside front-porch. 425 */ 426 if (amdgpu_dm_vrr_active(acrtc_state)) { 427 drm_crtc_handle_vblank(&acrtc->base); 428 429 /* BTR processing for pre-DCE12 ASICs */ 430 if (acrtc_state->stream && 431 adev->family < AMDGPU_FAMILY_AI) { 432 spin_lock_irqsave(&adev->ddev->event_lock, flags); 433 mod_freesync_handle_v_update( 434 adev->dm.freesync_module, 435 acrtc_state->stream, 436 &acrtc_state->vrr_params); 437 438 dc_stream_adjust_vmin_vmax( 439 adev->dm.dc, 440 acrtc_state->stream, 441 &acrtc_state->vrr_params.adjust); 442 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 443 } 444 } 445 } 446 } 447 448 /** 449 * dm_crtc_high_irq() - Handles CRTC interrupt 450 * @interrupt_params: ignored 451 * 452 * Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK 453 * event handler. 454 */ 455 static void dm_crtc_high_irq(void *interrupt_params) 456 { 457 struct common_irq_params *irq_params = interrupt_params; 458 struct amdgpu_device *adev = irq_params->adev; 459 struct amdgpu_crtc *acrtc; 460 struct dm_crtc_state *acrtc_state; 461 unsigned long flags; 462 463 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK); 464 465 if (acrtc) { 466 acrtc_state = to_dm_crtc_state(acrtc->base.state); 467 468 DRM_DEBUG_DRIVER("crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id, 469 amdgpu_dm_vrr_active(acrtc_state)); 470 471 /* Core vblank handling at start of front-porch is only possible 472 * in non-vrr mode, as only there vblank timestamping will give 473 * valid results while done in front-porch. Otherwise defer it 474 * to dm_vupdate_high_irq after end of front-porch. 475 */ 476 if (!amdgpu_dm_vrr_active(acrtc_state)) 477 drm_crtc_handle_vblank(&acrtc->base); 478 479 /* Following stuff must happen at start of vblank, for crc 480 * computation and below-the-range btr support in vrr mode. 481 */ 482 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base); 483 484 if (acrtc_state->stream && adev->family >= AMDGPU_FAMILY_AI && 485 acrtc_state->vrr_params.supported && 486 acrtc_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE) { 487 spin_lock_irqsave(&adev->ddev->event_lock, flags); 488 mod_freesync_handle_v_update( 489 adev->dm.freesync_module, 490 acrtc_state->stream, 491 &acrtc_state->vrr_params); 492 493 dc_stream_adjust_vmin_vmax( 494 adev->dm.dc, 495 acrtc_state->stream, 496 &acrtc_state->vrr_params.adjust); 497 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 498 } 499 } 500 } 501 502 #if defined(CONFIG_DRM_AMD_DC_DCN) 503 /** 504 * dm_dcn_crtc_high_irq() - Handles VStartup interrupt for DCN generation ASICs 505 * @interrupt params - interrupt parameters 506 * 507 * Notify DRM's vblank event handler at VSTARTUP 508 * 509 * Unlike DCE hardware, we trigger the handler at VSTARTUP. at which: 510 * * We are close enough to VUPDATE - the point of no return for hw 511 * * We are in the fixed portion of variable front porch when vrr is enabled 512 * * We are before VUPDATE, where double-buffered vrr registers are swapped 513 * 514 * It is therefore the correct place to signal vblank, send user flip events, 515 * and update VRR. 516 */ 517 static void dm_dcn_crtc_high_irq(void *interrupt_params) 518 { 519 struct common_irq_params *irq_params = interrupt_params; 520 struct amdgpu_device *adev = irq_params->adev; 521 struct amdgpu_crtc *acrtc; 522 struct dm_crtc_state *acrtc_state; 523 unsigned long flags; 524 525 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK); 526 527 if (!acrtc) 528 return; 529 530 acrtc_state = to_dm_crtc_state(acrtc->base.state); 531 532 DRM_DEBUG_DRIVER("crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id, 533 amdgpu_dm_vrr_active(acrtc_state)); 534 535 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base); 536 drm_crtc_handle_vblank(&acrtc->base); 537 538 spin_lock_irqsave(&adev->ddev->event_lock, flags); 539 540 if (acrtc_state->vrr_params.supported && 541 acrtc_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE) { 542 mod_freesync_handle_v_update( 543 adev->dm.freesync_module, 544 acrtc_state->stream, 545 &acrtc_state->vrr_params); 546 547 dc_stream_adjust_vmin_vmax( 548 adev->dm.dc, 549 acrtc_state->stream, 550 &acrtc_state->vrr_params.adjust); 551 } 552 553 if (acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED) { 554 if (acrtc->event) { 555 drm_crtc_send_vblank_event(&acrtc->base, acrtc->event); 556 acrtc->event = NULL; 557 drm_crtc_vblank_put(&acrtc->base); 558 } 559 acrtc->pflip_status = AMDGPU_FLIP_NONE; 560 } 561 562 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 563 } 564 #endif 565 566 static int dm_set_clockgating_state(void *handle, 567 enum amd_clockgating_state state) 568 { 569 return 0; 570 } 571 572 static int dm_set_powergating_state(void *handle, 573 enum amd_powergating_state state) 574 { 575 return 0; 576 } 577 578 /* Prototypes of private functions */ 579 static int dm_early_init(void* handle); 580 581 /* Allocate memory for FBC compressed data */ 582 static void amdgpu_dm_fbc_init(struct drm_connector *connector) 583 { 584 struct drm_device *dev = connector->dev; 585 struct amdgpu_device *adev = dev->dev_private; 586 struct dm_comressor_info *compressor = &adev->dm.compressor; 587 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector); 588 struct drm_display_mode *mode; 589 unsigned long max_size = 0; 590 591 if (adev->dm.dc->fbc_compressor == NULL) 592 return; 593 594 if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP) 595 return; 596 597 if (compressor->bo_ptr) 598 return; 599 600 601 list_for_each_entry(mode, &connector->modes, head) { 602 if (max_size < mode->htotal * mode->vtotal) 603 max_size = mode->htotal * mode->vtotal; 604 } 605 606 if (max_size) { 607 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE, 608 AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr, 609 &compressor->gpu_addr, &compressor->cpu_addr); 610 611 if (r) 612 DRM_ERROR("DM: Failed to initialize FBC\n"); 613 else { 614 adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr; 615 DRM_INFO("DM: FBC alloc %lu\n", max_size*4); 616 } 617 618 } 619 620 } 621 622 #ifndef __NetBSD__ /* XXX amdgpu audio */ 623 static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port, 624 int pipe, bool *enabled, 625 unsigned char *buf, int max_bytes) 626 { 627 struct drm_device *dev = dev_get_drvdata(kdev); 628 struct amdgpu_device *adev = dev->dev_private; 629 struct drm_connector *connector; 630 struct drm_connector_list_iter conn_iter; 631 struct amdgpu_dm_connector *aconnector; 632 int ret = 0; 633 634 *enabled = false; 635 636 mutex_lock(&adev->dm.audio_lock); 637 638 drm_connector_list_iter_begin(dev, &conn_iter); 639 drm_for_each_connector_iter(connector, &conn_iter) { 640 aconnector = to_amdgpu_dm_connector(connector); 641 if (aconnector->audio_inst != port) 642 continue; 643 644 *enabled = true; 645 ret = drm_eld_size(connector->eld); 646 memcpy(buf, connector->eld, min(max_bytes, ret)); 647 648 break; 649 } 650 drm_connector_list_iter_end(&conn_iter); 651 652 mutex_unlock(&adev->dm.audio_lock); 653 654 DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled); 655 656 return ret; 657 } 658 659 static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = { 660 .get_eld = amdgpu_dm_audio_component_get_eld, 661 }; 662 663 static int amdgpu_dm_audio_component_bind(struct device *kdev, 664 struct device *hda_kdev, void *data) 665 { 666 struct drm_device *dev = dev_get_drvdata(kdev); 667 struct amdgpu_device *adev = dev->dev_private; 668 struct drm_audio_component *acomp = data; 669 670 acomp->ops = &amdgpu_dm_audio_component_ops; 671 acomp->dev = kdev; 672 adev->dm.audio_component = acomp; 673 674 return 0; 675 } 676 677 static void amdgpu_dm_audio_component_unbind(struct device *kdev, 678 struct device *hda_kdev, void *data) 679 { 680 struct drm_device *dev = dev_get_drvdata(kdev); 681 struct amdgpu_device *adev = dev->dev_private; 682 struct drm_audio_component *acomp = data; 683 684 acomp->ops = NULL; 685 acomp->dev = NULL; 686 adev->dm.audio_component = NULL; 687 } 688 689 static const struct component_ops amdgpu_dm_audio_component_bind_ops = { 690 .bind = amdgpu_dm_audio_component_bind, 691 .unbind = amdgpu_dm_audio_component_unbind, 692 }; 693 #endif 694 695 static int amdgpu_dm_audio_init(struct amdgpu_device *adev) 696 { 697 int i, ret; 698 699 if (!amdgpu_audio) 700 return 0; 701 702 adev->mode_info.audio.enabled = true; 703 704 adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count; 705 706 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 707 adev->mode_info.audio.pin[i].channels = -1; 708 adev->mode_info.audio.pin[i].rate = -1; 709 adev->mode_info.audio.pin[i].bits_per_sample = -1; 710 adev->mode_info.audio.pin[i].status_bits = 0; 711 adev->mode_info.audio.pin[i].category_code = 0; 712 adev->mode_info.audio.pin[i].connected = false; 713 adev->mode_info.audio.pin[i].id = 714 adev->dm.dc->res_pool->audios[i]->inst; 715 adev->mode_info.audio.pin[i].offset = 0; 716 } 717 718 #ifdef __NetBSD__ /* XXX amdgpu audio */ 719 __USE(ret); 720 #else 721 ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops); 722 if (ret < 0) 723 return ret; 724 #endif 725 726 adev->dm.audio_registered = true; 727 728 return 0; 729 } 730 731 static void amdgpu_dm_audio_fini(struct amdgpu_device *adev) 732 { 733 if (!amdgpu_audio) 734 return; 735 736 if (!adev->mode_info.audio.enabled) 737 return; 738 739 if (adev->dm.audio_registered) { 740 #ifndef __NetBSD__ /* XXX amdgpu audio */ 741 component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops); 742 #endif 743 adev->dm.audio_registered = false; 744 } 745 746 /* TODO: Disable audio? */ 747 748 adev->mode_info.audio.enabled = false; 749 } 750 751 void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin) 752 { 753 struct drm_audio_component *acomp = adev->dm.audio_component; 754 755 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) { 756 DRM_DEBUG_KMS("Notify ELD: %d\n", pin); 757 758 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, 759 pin, -1); 760 } 761 } 762 763 static int dm_dmub_hw_init(struct amdgpu_device *adev) 764 { 765 const struct dmcub_firmware_header_v1_0 *hdr; 766 struct dmub_srv *dmub_srv = adev->dm.dmub_srv; 767 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info; 768 const struct firmware *dmub_fw = adev->dm.dmub_fw; 769 struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu; 770 struct abm *abm = adev->dm.dc->res_pool->abm; 771 struct dmub_srv_hw_params hw_params; 772 enum dmub_status status; 773 const unsigned char *fw_inst_const, *fw_bss_data; 774 uint32_t i, fw_inst_const_size, fw_bss_data_size; 775 bool has_hw_support; 776 777 if (!dmub_srv) 778 /* DMUB isn't supported on the ASIC. */ 779 return 0; 780 781 if (!fb_info) { 782 DRM_ERROR("No framebuffer info for DMUB service.\n"); 783 return -EINVAL; 784 } 785 786 if (!dmub_fw) { 787 /* Firmware required for DMUB support. */ 788 DRM_ERROR("No firmware provided for DMUB.\n"); 789 return -EINVAL; 790 } 791 792 status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support); 793 if (status != DMUB_STATUS_OK) { 794 DRM_ERROR("Error checking HW support for DMUB: %d\n", status); 795 return -EINVAL; 796 } 797 798 if (!has_hw_support) { 799 DRM_INFO("DMUB unsupported on ASIC\n"); 800 return 0; 801 } 802 803 hdr = (const struct dmcub_firmware_header_v1_0 *)dmub_fw->data; 804 805 fw_inst_const = dmub_fw->data + 806 le32_to_cpu(hdr->header.ucode_array_offset_bytes) + 807 PSP_HEADER_BYTES; 808 809 fw_bss_data = dmub_fw->data + 810 le32_to_cpu(hdr->header.ucode_array_offset_bytes) + 811 le32_to_cpu(hdr->inst_const_bytes); 812 813 /* Copy firmware and bios info into FB memory. */ 814 fw_inst_const_size = le32_to_cpu(hdr->inst_const_bytes) - 815 PSP_HEADER_BYTES - PSP_FOOTER_BYTES; 816 817 fw_bss_data_size = le32_to_cpu(hdr->bss_data_bytes); 818 819 memcpy(fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr, fw_inst_const, 820 fw_inst_const_size); 821 memcpy(fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr, fw_bss_data, 822 fw_bss_data_size); 823 memcpy(fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr, adev->bios, 824 adev->bios_size); 825 826 /* Reset regions that need to be reset. */ 827 memset(fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr, 0, 828 fb_info->fb[DMUB_WINDOW_4_MAILBOX].size); 829 830 memset(fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr, 0, 831 fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size); 832 833 memset(fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr, 0, 834 fb_info->fb[DMUB_WINDOW_6_FW_STATE].size); 835 836 /* Initialize hardware. */ 837 memset(&hw_params, 0, sizeof(hw_params)); 838 hw_params.fb_base = adev->gmc.fb_start; 839 hw_params.fb_offset = adev->gmc.aper_base; 840 841 if (dmcu) 842 hw_params.psp_version = dmcu->psp_version; 843 844 for (i = 0; i < fb_info->num_fb; ++i) 845 hw_params.fb[i] = &fb_info->fb[i]; 846 847 status = dmub_srv_hw_init(dmub_srv, &hw_params); 848 if (status != DMUB_STATUS_OK) { 849 DRM_ERROR("Error initializing DMUB HW: %d\n", status); 850 return -EINVAL; 851 } 852 853 /* Wait for firmware load to finish. */ 854 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000); 855 if (status != DMUB_STATUS_OK) 856 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status); 857 858 /* Init DMCU and ABM if available. */ 859 if (dmcu && abm) { 860 dmcu->funcs->dmcu_init(dmcu); 861 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu); 862 } 863 864 adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv); 865 if (!adev->dm.dc->ctx->dmub_srv) { 866 DRM_ERROR("Couldn't allocate DC DMUB server!\n"); 867 return -ENOMEM; 868 } 869 870 DRM_INFO("DMUB hardware initialized: version=0x%08X\n", 871 adev->dm.dmcub_fw_version); 872 873 return 0; 874 } 875 876 static int amdgpu_dm_init(struct amdgpu_device *adev) 877 { 878 struct dc_init_data init_data; 879 #ifdef CONFIG_DRM_AMD_DC_HDCP 880 struct dc_callback_init init_params; 881 #endif 882 int r; 883 884 adev->dm.ddev = adev->ddev; 885 adev->dm.adev = adev; 886 887 /* Zero all the fields */ 888 memset(&init_data, 0, sizeof(init_data)); 889 #ifdef CONFIG_DRM_AMD_DC_HDCP 890 memset(&init_params, 0, sizeof(init_params)); 891 #endif 892 893 mutex_init(&adev->dm.dc_lock); 894 mutex_init(&adev->dm.audio_lock); 895 896 if(amdgpu_dm_irq_init(adev)) { 897 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n"); 898 goto error; 899 } 900 901 init_data.asic_id.chip_family = adev->family; 902 903 init_data.asic_id.pci_revision_id = adev->rev_id; 904 init_data.asic_id.hw_internal_rev = adev->external_rev_id; 905 906 init_data.asic_id.vram_width = adev->gmc.vram_width; 907 /* TODO: initialize init_data.asic_id.vram_type here!!!! */ 908 init_data.asic_id.atombios_base_address = 909 adev->mode_info.atom_context->bios; 910 911 init_data.driver = adev; 912 913 adev->dm.cgs_device = amdgpu_cgs_create_device(adev); 914 915 if (!adev->dm.cgs_device) { 916 DRM_ERROR("amdgpu: failed to create cgs device.\n"); 917 goto error; 918 } 919 920 init_data.cgs_device = adev->dm.cgs_device; 921 922 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV; 923 924 switch (adev->asic_type) { 925 case CHIP_CARRIZO: 926 case CHIP_STONEY: 927 case CHIP_RAVEN: 928 case CHIP_RENOIR: 929 init_data.flags.gpu_vm_support = true; 930 break; 931 default: 932 break; 933 } 934 935 if (amdgpu_dc_feature_mask & DC_FBC_MASK) 936 init_data.flags.fbc_support = true; 937 938 if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK) 939 init_data.flags.multi_mon_pp_mclk_switch = true; 940 941 if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK) 942 init_data.flags.disable_fractional_pwm = true; 943 944 init_data.flags.power_down_display_on_boot = true; 945 946 init_data.soc_bounding_box = adev->dm.soc_bounding_box; 947 948 /* Display Core create. */ 949 adev->dm.dc = dc_create(&init_data); 950 951 if (adev->dm.dc) { 952 DRM_INFO("Display Core initialized with v%s!\n", DC_VER); 953 } else { 954 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER); 955 goto error; 956 } 957 958 r = dm_dmub_hw_init(adev); 959 if (r) { 960 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r); 961 goto error; 962 } 963 964 dc_hardware_init(adev->dm.dc); 965 966 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc); 967 if (!adev->dm.freesync_module) { 968 DRM_ERROR( 969 "amdgpu: failed to initialize freesync_module.\n"); 970 } else 971 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n", 972 adev->dm.freesync_module); 973 974 amdgpu_dm_init_color_mod(); 975 976 #ifdef CONFIG_DRM_AMD_DC_HDCP 977 if (adev->asic_type >= CHIP_RAVEN) { 978 adev->dm.hdcp_workqueue = hdcp_create_workqueue(&adev->psp, &init_params.cp_psp, adev->dm.dc); 979 980 if (!adev->dm.hdcp_workqueue) 981 DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n"); 982 else 983 DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue); 984 985 dc_init_callbacks(adev->dm.dc, &init_params); 986 } 987 #endif 988 if (amdgpu_dm_initialize_drm_device(adev)) { 989 DRM_ERROR( 990 "amdgpu: failed to initialize sw for display support.\n"); 991 goto error; 992 } 993 994 /* Update the actual used number of crtc */ 995 adev->mode_info.num_crtc = adev->dm.display_indexes_num; 996 997 /* TODO: Add_display_info? */ 998 999 /* TODO use dynamic cursor width */ 1000 adev->ddev->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size; 1001 adev->ddev->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size; 1002 1003 if (drm_vblank_init(adev->ddev, adev->dm.display_indexes_num)) { 1004 DRM_ERROR( 1005 "amdgpu: failed to initialize sw for display support.\n"); 1006 goto error; 1007 } 1008 1009 #if defined(CONFIG_DEBUG_FS) 1010 if (dtn_debugfs_init(adev)) 1011 DRM_ERROR("amdgpu: failed initialize dtn debugfs support.\n"); 1012 #endif 1013 1014 DRM_DEBUG_DRIVER("KMS initialized.\n"); 1015 1016 return 0; 1017 error: 1018 amdgpu_dm_fini(adev); 1019 1020 return -EINVAL; 1021 } 1022 1023 static void amdgpu_dm_fini(struct amdgpu_device *adev) 1024 { 1025 amdgpu_dm_audio_fini(adev); 1026 1027 amdgpu_dm_destroy_drm_device(&adev->dm); 1028 1029 #ifdef CONFIG_DRM_AMD_DC_HDCP 1030 if (adev->dm.hdcp_workqueue) { 1031 hdcp_destroy(adev->dm.hdcp_workqueue); 1032 adev->dm.hdcp_workqueue = NULL; 1033 } 1034 1035 if (adev->dm.dc) 1036 dc_deinit_callbacks(adev->dm.dc); 1037 #endif 1038 if (adev->dm.dc->ctx->dmub_srv) { 1039 dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv); 1040 adev->dm.dc->ctx->dmub_srv = NULL; 1041 } 1042 1043 if (adev->dm.dmub_bo) 1044 amdgpu_bo_free_kernel(&adev->dm.dmub_bo, 1045 &adev->dm.dmub_bo_gpu_addr, 1046 &adev->dm.dmub_bo_cpu_addr); 1047 1048 /* DC Destroy TODO: Replace destroy DAL */ 1049 if (adev->dm.dc) 1050 dc_destroy(&adev->dm.dc); 1051 /* 1052 * TODO: pageflip, vlank interrupt 1053 * 1054 * amdgpu_dm_irq_fini(adev); 1055 */ 1056 1057 if (adev->dm.cgs_device) { 1058 amdgpu_cgs_destroy_device(adev->dm.cgs_device); 1059 adev->dm.cgs_device = NULL; 1060 } 1061 if (adev->dm.freesync_module) { 1062 mod_freesync_destroy(adev->dm.freesync_module); 1063 adev->dm.freesync_module = NULL; 1064 } 1065 1066 mutex_destroy(&adev->dm.audio_lock); 1067 mutex_destroy(&adev->dm.dc_lock); 1068 1069 return; 1070 } 1071 1072 static int load_dmcu_fw(struct amdgpu_device *adev) 1073 { 1074 const char *fw_name_dmcu = NULL; 1075 int r; 1076 const struct dmcu_firmware_header_v1_0 *hdr; 1077 1078 switch(adev->asic_type) { 1079 case CHIP_BONAIRE: 1080 case CHIP_HAWAII: 1081 case CHIP_KAVERI: 1082 case CHIP_KABINI: 1083 case CHIP_MULLINS: 1084 case CHIP_TONGA: 1085 case CHIP_FIJI: 1086 case CHIP_CARRIZO: 1087 case CHIP_STONEY: 1088 case CHIP_POLARIS11: 1089 case CHIP_POLARIS10: 1090 case CHIP_POLARIS12: 1091 case CHIP_VEGAM: 1092 case CHIP_VEGA10: 1093 case CHIP_VEGA12: 1094 case CHIP_VEGA20: 1095 case CHIP_NAVI10: 1096 case CHIP_NAVI14: 1097 case CHIP_NAVI12: 1098 case CHIP_RENOIR: 1099 return 0; 1100 case CHIP_RAVEN: 1101 if (ASICREV_IS_PICASSO(adev->external_rev_id)) 1102 fw_name_dmcu = FIRMWARE_RAVEN_DMCU; 1103 else if (ASICREV_IS_RAVEN2(adev->external_rev_id)) 1104 fw_name_dmcu = FIRMWARE_RAVEN_DMCU; 1105 else 1106 return 0; 1107 break; 1108 default: 1109 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type); 1110 return -EINVAL; 1111 } 1112 1113 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1114 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n"); 1115 return 0; 1116 } 1117 1118 r = request_firmware_direct(&adev->dm.fw_dmcu, fw_name_dmcu, adev->dev); 1119 if (r == -ENOENT) { 1120 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */ 1121 DRM_DEBUG_KMS("dm: DMCU firmware not found\n"); 1122 adev->dm.fw_dmcu = NULL; 1123 return 0; 1124 } 1125 if (r) { 1126 dev_err(adev->dev, "amdgpu_dm: Can't load firmware \"%s\"\n", 1127 fw_name_dmcu); 1128 return r; 1129 } 1130 1131 r = amdgpu_ucode_validate(adev->dm.fw_dmcu); 1132 if (r) { 1133 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n", 1134 fw_name_dmcu); 1135 release_firmware(adev->dm.fw_dmcu); 1136 adev->dm.fw_dmcu = NULL; 1137 return r; 1138 } 1139 1140 hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data; 1141 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM; 1142 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu; 1143 adev->firmware.fw_size += 1144 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE); 1145 1146 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV; 1147 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu; 1148 adev->firmware.fw_size += 1149 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE); 1150 1151 adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version); 1152 1153 DRM_DEBUG_KMS("PSP loading DMCU firmware\n"); 1154 1155 return 0; 1156 } 1157 1158 static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address) 1159 { 1160 struct amdgpu_device *adev = ctx; 1161 1162 return dm_read_reg(adev->dm.dc->ctx, address); 1163 } 1164 1165 static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address, 1166 uint32_t value) 1167 { 1168 struct amdgpu_device *adev = ctx; 1169 1170 return dm_write_reg(adev->dm.dc->ctx, address, value); 1171 } 1172 1173 static int dm_dmub_sw_init(struct amdgpu_device *adev) 1174 { 1175 struct dmub_srv_create_params create_params; 1176 struct dmub_srv_region_params region_params; 1177 struct dmub_srv_region_info region_info; 1178 struct dmub_srv_fb_params fb_params; 1179 struct dmub_srv_fb_info *fb_info; 1180 struct dmub_srv *dmub_srv; 1181 const struct dmcub_firmware_header_v1_0 *hdr; 1182 const char *fw_name_dmub; 1183 enum dmub_asic dmub_asic; 1184 enum dmub_status status; 1185 int r; 1186 1187 switch (adev->asic_type) { 1188 case CHIP_RENOIR: 1189 dmub_asic = DMUB_ASIC_DCN21; 1190 fw_name_dmub = FIRMWARE_RENOIR_DMUB; 1191 break; 1192 1193 default: 1194 /* ASIC doesn't support DMUB. */ 1195 return 0; 1196 } 1197 1198 r = request_firmware_direct(&adev->dm.dmub_fw, fw_name_dmub, adev->dev); 1199 if (r) { 1200 DRM_ERROR("DMUB firmware loading failed: %d\n", r); 1201 return 0; 1202 } 1203 1204 r = amdgpu_ucode_validate(adev->dm.dmub_fw); 1205 if (r) { 1206 DRM_ERROR("Couldn't validate DMUB firmware: %d\n", r); 1207 return 0; 1208 } 1209 1210 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1211 DRM_WARN("Only PSP firmware loading is supported for DMUB\n"); 1212 return 0; 1213 } 1214 1215 hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data; 1216 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].ucode_id = 1217 AMDGPU_UCODE_ID_DMCUB; 1218 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].fw = adev->dm.dmub_fw; 1219 adev->firmware.fw_size += 1220 ALIGN(le32_to_cpu(hdr->inst_const_bytes), PAGE_SIZE); 1221 1222 adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version); 1223 1224 DRM_INFO("Loading DMUB firmware via PSP: version=0x%08X\n", 1225 adev->dm.dmcub_fw_version); 1226 1227 adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL); 1228 dmub_srv = adev->dm.dmub_srv; 1229 1230 if (!dmub_srv) { 1231 DRM_ERROR("Failed to allocate DMUB service!\n"); 1232 return -ENOMEM; 1233 } 1234 1235 memset(&create_params, 0, sizeof(create_params)); 1236 create_params.user_ctx = adev; 1237 create_params.funcs.reg_read = amdgpu_dm_dmub_reg_read; 1238 create_params.funcs.reg_write = amdgpu_dm_dmub_reg_write; 1239 create_params.asic = dmub_asic; 1240 1241 /* Create the DMUB service. */ 1242 status = dmub_srv_create(dmub_srv, &create_params); 1243 if (status != DMUB_STATUS_OK) { 1244 DRM_ERROR("Error creating DMUB service: %d\n", status); 1245 return -EINVAL; 1246 } 1247 1248 /* Calculate the size of all the regions for the DMUB service. */ 1249 memset(®ion_params, 0, sizeof(region_params)); 1250 1251 region_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes) - 1252 PSP_HEADER_BYTES - PSP_FOOTER_BYTES; 1253 region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes); 1254 region_params.vbios_size = adev->bios_size; 1255 region_params.fw_bss_data = 1256 adev->dm.dmub_fw->data + 1257 le32_to_cpu(hdr->header.ucode_array_offset_bytes) + 1258 le32_to_cpu(hdr->inst_const_bytes); 1259 1260 status = dmub_srv_calc_region_info(dmub_srv, ®ion_params, 1261 ®ion_info); 1262 1263 if (status != DMUB_STATUS_OK) { 1264 DRM_ERROR("Error calculating DMUB region info: %d\n", status); 1265 return -EINVAL; 1266 } 1267 1268 /* 1269 * Allocate a framebuffer based on the total size of all the regions. 1270 * TODO: Move this into GART. 1271 */ 1272 r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE, 1273 AMDGPU_GEM_DOMAIN_VRAM, &adev->dm.dmub_bo, 1274 &adev->dm.dmub_bo_gpu_addr, 1275 &adev->dm.dmub_bo_cpu_addr); 1276 if (r) 1277 return r; 1278 1279 /* Rebase the regions on the framebuffer address. */ 1280 memset(&fb_params, 0, sizeof(fb_params)); 1281 fb_params.cpu_addr = adev->dm.dmub_bo_cpu_addr; 1282 fb_params.gpu_addr = adev->dm.dmub_bo_gpu_addr; 1283 fb_params.region_info = ®ion_info; 1284 1285 adev->dm.dmub_fb_info = 1286 kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL); 1287 fb_info = adev->dm.dmub_fb_info; 1288 1289 if (!fb_info) { 1290 DRM_ERROR( 1291 "Failed to allocate framebuffer info for DMUB service!\n"); 1292 return -ENOMEM; 1293 } 1294 1295 status = dmub_srv_calc_fb_info(dmub_srv, &fb_params, fb_info); 1296 if (status != DMUB_STATUS_OK) { 1297 DRM_ERROR("Error calculating DMUB FB info: %d\n", status); 1298 return -EINVAL; 1299 } 1300 1301 return 0; 1302 } 1303 1304 static int dm_sw_init(void *handle) 1305 { 1306 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1307 int r; 1308 1309 r = dm_dmub_sw_init(adev); 1310 if (r) 1311 return r; 1312 1313 return load_dmcu_fw(adev); 1314 } 1315 1316 static int dm_sw_fini(void *handle) 1317 { 1318 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1319 1320 kfree(adev->dm.dmub_fb_info); 1321 adev->dm.dmub_fb_info = NULL; 1322 1323 if (adev->dm.dmub_srv) { 1324 dmub_srv_destroy(adev->dm.dmub_srv); 1325 adev->dm.dmub_srv = NULL; 1326 } 1327 1328 if (adev->dm.dmub_fw) { 1329 release_firmware(adev->dm.dmub_fw); 1330 adev->dm.dmub_fw = NULL; 1331 } 1332 1333 if(adev->dm.fw_dmcu) { 1334 release_firmware(adev->dm.fw_dmcu); 1335 adev->dm.fw_dmcu = NULL; 1336 } 1337 1338 return 0; 1339 } 1340 1341 static int detect_mst_link_for_all_connectors(struct drm_device *dev) 1342 { 1343 struct amdgpu_dm_connector *aconnector; 1344 struct drm_connector *connector; 1345 struct drm_connector_list_iter iter; 1346 int ret = 0; 1347 1348 drm_connector_list_iter_begin(dev, &iter); 1349 drm_for_each_connector_iter(connector, &iter) { 1350 aconnector = to_amdgpu_dm_connector(connector); 1351 if (aconnector->dc_link->type == dc_connection_mst_branch && 1352 aconnector->mst_mgr.aux) { 1353 DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n", 1354 aconnector, 1355 aconnector->base.base.id); 1356 1357 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true); 1358 if (ret < 0) { 1359 DRM_ERROR("DM_MST: Failed to start MST\n"); 1360 aconnector->dc_link->type = 1361 dc_connection_single; 1362 break; 1363 } 1364 } 1365 } 1366 drm_connector_list_iter_end(&iter); 1367 1368 return ret; 1369 } 1370 1371 static int dm_late_init(void *handle) 1372 { 1373 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1374 1375 struct dmcu_iram_parameters params; 1376 unsigned int linear_lut[16]; 1377 int i; 1378 struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu; 1379 bool ret = false; 1380 1381 for (i = 0; i < 16; i++) 1382 linear_lut[i] = 0xFFFF * i / 15; 1383 1384 params.set = 0; 1385 params.backlight_ramping_start = 0xCCCC; 1386 params.backlight_ramping_reduction = 0xCCCCCCCC; 1387 params.backlight_lut_array_size = 16; 1388 params.backlight_lut_array = linear_lut; 1389 1390 /* Min backlight level after ABM reduction, Don't allow below 1% 1391 * 0xFFFF x 0.01 = 0x28F 1392 */ 1393 params.min_abm_backlight = 0x28F; 1394 1395 /* todo will enable for navi10 */ 1396 if (adev->asic_type <= CHIP_RAVEN) { 1397 ret = dmcu_load_iram(dmcu, params); 1398 1399 if (!ret) 1400 return -EINVAL; 1401 } 1402 1403 return detect_mst_link_for_all_connectors(adev->ddev); 1404 } 1405 1406 static void s3_handle_mst(struct drm_device *dev, bool suspend) 1407 { 1408 struct amdgpu_dm_connector *aconnector; 1409 struct drm_connector *connector; 1410 struct drm_connector_list_iter iter; 1411 struct drm_dp_mst_topology_mgr *mgr; 1412 int ret; 1413 bool need_hotplug = false; 1414 1415 drm_connector_list_iter_begin(dev, &iter); 1416 drm_for_each_connector_iter(connector, &iter) { 1417 aconnector = to_amdgpu_dm_connector(connector); 1418 if (aconnector->dc_link->type != dc_connection_mst_branch || 1419 aconnector->mst_port) 1420 continue; 1421 1422 mgr = &aconnector->mst_mgr; 1423 1424 if (suspend) { 1425 drm_dp_mst_topology_mgr_suspend(mgr); 1426 } else { 1427 ret = drm_dp_mst_topology_mgr_resume(mgr, true); 1428 if (ret < 0) { 1429 drm_dp_mst_topology_mgr_set_mst(mgr, false); 1430 need_hotplug = true; 1431 } 1432 } 1433 } 1434 drm_connector_list_iter_end(&iter); 1435 1436 if (need_hotplug) 1437 drm_kms_helper_hotplug_event(dev); 1438 } 1439 1440 /** 1441 * dm_hw_init() - Initialize DC device 1442 * @handle: The base driver device containing the amdgpu_dm device. 1443 * 1444 * Initialize the &struct amdgpu_display_manager device. This involves calling 1445 * the initializers of each DM component, then populating the struct with them. 1446 * 1447 * Although the function implies hardware initialization, both hardware and 1448 * software are initialized here. Splitting them out to their relevant init 1449 * hooks is a future TODO item. 1450 * 1451 * Some notable things that are initialized here: 1452 * 1453 * - Display Core, both software and hardware 1454 * - DC modules that we need (freesync and color management) 1455 * - DRM software states 1456 * - Interrupt sources and handlers 1457 * - Vblank support 1458 * - Debug FS entries, if enabled 1459 */ 1460 static int dm_hw_init(void *handle) 1461 { 1462 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1463 /* Create DAL display manager */ 1464 amdgpu_dm_init(adev); 1465 amdgpu_dm_hpd_init(adev); 1466 1467 return 0; 1468 } 1469 1470 /** 1471 * dm_hw_fini() - Teardown DC device 1472 * @handle: The base driver device containing the amdgpu_dm device. 1473 * 1474 * Teardown components within &struct amdgpu_display_manager that require 1475 * cleanup. This involves cleaning up the DRM device, DC, and any modules that 1476 * were loaded. Also flush IRQ workqueues and disable them. 1477 */ 1478 static int dm_hw_fini(void *handle) 1479 { 1480 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1481 1482 amdgpu_dm_hpd_fini(adev); 1483 1484 amdgpu_dm_irq_fini(adev); 1485 amdgpu_dm_fini(adev); 1486 return 0; 1487 } 1488 1489 static int dm_suspend(void *handle) 1490 { 1491 struct amdgpu_device *adev = handle; 1492 struct amdgpu_display_manager *dm = &adev->dm; 1493 int ret = 0; 1494 1495 WARN_ON(adev->dm.cached_state); 1496 adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev); 1497 1498 s3_handle_mst(adev->ddev, true); 1499 1500 amdgpu_dm_irq_suspend(adev); 1501 1502 1503 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3); 1504 1505 return ret; 1506 } 1507 1508 static struct amdgpu_dm_connector * 1509 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state, 1510 struct drm_crtc *crtc) 1511 { 1512 uint32_t i; 1513 struct drm_connector_state *new_con_state; 1514 struct drm_connector *connector; 1515 struct drm_crtc *crtc_from_state; 1516 1517 for_each_new_connector_in_state(state, connector, new_con_state, i) { 1518 crtc_from_state = new_con_state->crtc; 1519 1520 if (crtc_from_state == crtc) 1521 return to_amdgpu_dm_connector(connector); 1522 } 1523 1524 return NULL; 1525 } 1526 1527 static void emulated_link_detect(struct dc_link *link) 1528 { 1529 struct dc_sink_init_data sink_init_data = { 0 }; 1530 struct display_sink_capability sink_caps = { 0 }; 1531 enum dc_edid_status edid_status; 1532 struct dc_context *dc_ctx = link->ctx; 1533 struct dc_sink *sink = NULL; 1534 struct dc_sink *prev_sink = NULL; 1535 1536 link->type = dc_connection_none; 1537 prev_sink = link->local_sink; 1538 1539 if (prev_sink != NULL) 1540 dc_sink_retain(prev_sink); 1541 1542 switch (link->connector_signal) { 1543 case SIGNAL_TYPE_HDMI_TYPE_A: { 1544 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 1545 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A; 1546 break; 1547 } 1548 1549 case SIGNAL_TYPE_DVI_SINGLE_LINK: { 1550 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 1551 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 1552 break; 1553 } 1554 1555 case SIGNAL_TYPE_DVI_DUAL_LINK: { 1556 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 1557 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK; 1558 break; 1559 } 1560 1561 case SIGNAL_TYPE_LVDS: { 1562 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 1563 sink_caps.signal = SIGNAL_TYPE_LVDS; 1564 break; 1565 } 1566 1567 case SIGNAL_TYPE_EDP: { 1568 sink_caps.transaction_type = 1569 DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 1570 sink_caps.signal = SIGNAL_TYPE_EDP; 1571 break; 1572 } 1573 1574 case SIGNAL_TYPE_DISPLAY_PORT: { 1575 sink_caps.transaction_type = 1576 DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 1577 sink_caps.signal = SIGNAL_TYPE_VIRTUAL; 1578 break; 1579 } 1580 1581 default: 1582 DC_ERROR("Invalid connector type! signal:%d\n", 1583 link->connector_signal); 1584 return; 1585 } 1586 1587 sink_init_data.link = link; 1588 sink_init_data.sink_signal = sink_caps.signal; 1589 1590 sink = dc_sink_create(&sink_init_data); 1591 if (!sink) { 1592 DC_ERROR("Failed to create sink!\n"); 1593 return; 1594 } 1595 1596 /* dc_sink_create returns a new reference */ 1597 link->local_sink = sink; 1598 1599 edid_status = dm_helpers_read_local_edid( 1600 link->ctx, 1601 link, 1602 sink); 1603 1604 if (edid_status != EDID_OK) 1605 DC_ERROR("Failed to read EDID"); 1606 1607 } 1608 1609 static int dm_resume(void *handle) 1610 { 1611 struct amdgpu_device *adev = handle; 1612 struct drm_device *ddev = adev->ddev; 1613 struct amdgpu_display_manager *dm = &adev->dm; 1614 struct amdgpu_dm_connector *aconnector; 1615 struct drm_connector *connector; 1616 struct drm_connector_list_iter iter; 1617 struct drm_crtc *crtc; 1618 struct drm_crtc_state *new_crtc_state; 1619 struct dm_crtc_state *dm_new_crtc_state; 1620 struct drm_plane *plane; 1621 struct drm_plane_state *new_plane_state; 1622 struct dm_plane_state *dm_new_plane_state; 1623 struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state); 1624 enum dc_connection_type new_connection_type = dc_connection_none; 1625 int i, r; 1626 1627 /* Recreate dc_state - DC invalidates it when setting power state to S3. */ 1628 dc_release_state(dm_state->context); 1629 dm_state->context = dc_create_state(dm->dc); 1630 /* TODO: Remove dc_state->dccg, use dc->dccg directly. */ 1631 dc_resource_state_construct(dm->dc, dm_state->context); 1632 1633 /* Before powering on DC we need to re-initialize DMUB. */ 1634 r = dm_dmub_hw_init(adev); 1635 if (r) 1636 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r); 1637 1638 /* power on hardware */ 1639 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); 1640 1641 /* program HPD filter */ 1642 dc_resume(dm->dc); 1643 1644 /* 1645 * early enable HPD Rx IRQ, should be done before set mode as short 1646 * pulse interrupts are used for MST 1647 */ 1648 amdgpu_dm_irq_resume_early(adev); 1649 1650 /* On resume we need to rewrite the MSTM control bits to enable MST*/ 1651 s3_handle_mst(ddev, false); 1652 1653 /* Do detection*/ 1654 drm_connector_list_iter_begin(ddev, &iter); 1655 drm_for_each_connector_iter(connector, &iter) { 1656 aconnector = to_amdgpu_dm_connector(connector); 1657 1658 /* 1659 * this is the case when traversing through already created 1660 * MST connectors, should be skipped 1661 */ 1662 if (aconnector->mst_port) 1663 continue; 1664 1665 mutex_lock(&aconnector->hpd_lock); 1666 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type)) 1667 DRM_ERROR("KMS: Failed to detect connector\n"); 1668 1669 if (aconnector->base.force && new_connection_type == dc_connection_none) 1670 emulated_link_detect(aconnector->dc_link); 1671 else 1672 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); 1673 1674 if (aconnector->fake_enable && aconnector->dc_link->local_sink) 1675 aconnector->fake_enable = false; 1676 1677 if (aconnector->dc_sink) 1678 dc_sink_release(aconnector->dc_sink); 1679 aconnector->dc_sink = NULL; 1680 amdgpu_dm_update_connector_after_detect(aconnector); 1681 mutex_unlock(&aconnector->hpd_lock); 1682 } 1683 drm_connector_list_iter_end(&iter); 1684 1685 /* Force mode set in atomic commit */ 1686 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) 1687 new_crtc_state->active_changed = true; 1688 1689 /* 1690 * atomic_check is expected to create the dc states. We need to release 1691 * them here, since they were duplicated as part of the suspend 1692 * procedure. 1693 */ 1694 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) { 1695 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 1696 if (dm_new_crtc_state->stream) { 1697 WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1); 1698 dc_stream_release(dm_new_crtc_state->stream); 1699 dm_new_crtc_state->stream = NULL; 1700 } 1701 } 1702 1703 for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) { 1704 dm_new_plane_state = to_dm_plane_state(new_plane_state); 1705 if (dm_new_plane_state->dc_state) { 1706 WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1); 1707 dc_plane_state_release(dm_new_plane_state->dc_state); 1708 dm_new_plane_state->dc_state = NULL; 1709 } 1710 } 1711 1712 drm_atomic_helper_resume(ddev, dm->cached_state); 1713 1714 dm->cached_state = NULL; 1715 1716 amdgpu_dm_irq_resume_late(adev); 1717 1718 return 0; 1719 } 1720 1721 /** 1722 * DOC: DM Lifecycle 1723 * 1724 * DM (and consequently DC) is registered in the amdgpu base driver as a IP 1725 * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to 1726 * the base driver's device list to be initialized and torn down accordingly. 1727 * 1728 * The functions to do so are provided as hooks in &struct amd_ip_funcs. 1729 */ 1730 1731 static const struct amd_ip_funcs amdgpu_dm_funcs = { 1732 .name = "dm", 1733 .early_init = dm_early_init, 1734 .late_init = dm_late_init, 1735 .sw_init = dm_sw_init, 1736 .sw_fini = dm_sw_fini, 1737 .hw_init = dm_hw_init, 1738 .hw_fini = dm_hw_fini, 1739 .suspend = dm_suspend, 1740 .resume = dm_resume, 1741 .is_idle = dm_is_idle, 1742 .wait_for_idle = dm_wait_for_idle, 1743 .check_soft_reset = dm_check_soft_reset, 1744 .soft_reset = dm_soft_reset, 1745 .set_clockgating_state = dm_set_clockgating_state, 1746 .set_powergating_state = dm_set_powergating_state, 1747 }; 1748 1749 const struct amdgpu_ip_block_version dm_ip_block = 1750 { 1751 .type = AMD_IP_BLOCK_TYPE_DCE, 1752 .major = 1, 1753 .minor = 0, 1754 .rev = 0, 1755 .funcs = &amdgpu_dm_funcs, 1756 }; 1757 1758 1759 /** 1760 * DOC: atomic 1761 * 1762 * *WIP* 1763 */ 1764 1765 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = { 1766 .fb_create = amdgpu_display_user_framebuffer_create, 1767 .output_poll_changed = drm_fb_helper_output_poll_changed, 1768 .atomic_check = amdgpu_dm_atomic_check, 1769 .atomic_commit = amdgpu_dm_atomic_commit, 1770 }; 1771 1772 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = { 1773 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail 1774 }; 1775 1776 static void 1777 amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector) 1778 { 1779 struct drm_connector *connector = &aconnector->base; 1780 struct drm_device *dev = connector->dev; 1781 struct dc_sink *sink; 1782 1783 /* MST handled by drm_mst framework */ 1784 if (aconnector->mst_mgr.mst_state == true) 1785 return; 1786 1787 1788 sink = aconnector->dc_link->local_sink; 1789 if (sink) 1790 dc_sink_retain(sink); 1791 1792 /* 1793 * Edid mgmt connector gets first update only in mode_valid hook and then 1794 * the connector sink is set to either fake or physical sink depends on link status. 1795 * Skip if already done during boot. 1796 */ 1797 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED 1798 && aconnector->dc_em_sink) { 1799 1800 /* 1801 * For S3 resume with headless use eml_sink to fake stream 1802 * because on resume connector->sink is set to NULL 1803 */ 1804 mutex_lock(&dev->mode_config.mutex); 1805 1806 if (sink) { 1807 if (aconnector->dc_sink) { 1808 amdgpu_dm_update_freesync_caps(connector, NULL); 1809 /* 1810 * retain and release below are used to 1811 * bump up refcount for sink because the link doesn't point 1812 * to it anymore after disconnect, so on next crtc to connector 1813 * reshuffle by UMD we will get into unwanted dc_sink release 1814 */ 1815 dc_sink_release(aconnector->dc_sink); 1816 } 1817 aconnector->dc_sink = sink; 1818 dc_sink_retain(aconnector->dc_sink); 1819 amdgpu_dm_update_freesync_caps(connector, 1820 aconnector->edid); 1821 } else { 1822 amdgpu_dm_update_freesync_caps(connector, NULL); 1823 if (!aconnector->dc_sink) { 1824 aconnector->dc_sink = aconnector->dc_em_sink; 1825 dc_sink_retain(aconnector->dc_sink); 1826 } 1827 } 1828 1829 mutex_unlock(&dev->mode_config.mutex); 1830 1831 if (sink) 1832 dc_sink_release(sink); 1833 return; 1834 } 1835 1836 /* 1837 * TODO: temporary guard to look for proper fix 1838 * if this sink is MST sink, we should not do anything 1839 */ 1840 if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 1841 dc_sink_release(sink); 1842 return; 1843 } 1844 1845 if (aconnector->dc_sink == sink) { 1846 /* 1847 * We got a DP short pulse (Link Loss, DP CTS, etc...). 1848 * Do nothing!! 1849 */ 1850 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n", 1851 aconnector->connector_id); 1852 if (sink) 1853 dc_sink_release(sink); 1854 return; 1855 } 1856 1857 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n", 1858 aconnector->connector_id, aconnector->dc_sink, sink); 1859 1860 mutex_lock(&dev->mode_config.mutex); 1861 1862 /* 1863 * 1. Update status of the drm connector 1864 * 2. Send an event and let userspace tell us what to do 1865 */ 1866 if (sink) { 1867 /* 1868 * TODO: check if we still need the S3 mode update workaround. 1869 * If yes, put it here. 1870 */ 1871 if (aconnector->dc_sink) 1872 amdgpu_dm_update_freesync_caps(connector, NULL); 1873 1874 aconnector->dc_sink = sink; 1875 dc_sink_retain(aconnector->dc_sink); 1876 if (sink->dc_edid.length == 0) { 1877 aconnector->edid = NULL; 1878 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux); 1879 } else { 1880 aconnector->edid = 1881 (struct edid *) sink->dc_edid.raw_edid; 1882 1883 1884 drm_connector_update_edid_property(connector, 1885 aconnector->edid); 1886 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux, 1887 aconnector->edid); 1888 } 1889 amdgpu_dm_update_freesync_caps(connector, aconnector->edid); 1890 1891 } else { 1892 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux); 1893 amdgpu_dm_update_freesync_caps(connector, NULL); 1894 drm_connector_update_edid_property(connector, NULL); 1895 aconnector->num_modes = 0; 1896 dc_sink_release(aconnector->dc_sink); 1897 aconnector->dc_sink = NULL; 1898 aconnector->edid = NULL; 1899 #ifdef CONFIG_DRM_AMD_DC_HDCP 1900 /* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */ 1901 if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) 1902 connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 1903 #endif 1904 } 1905 1906 mutex_unlock(&dev->mode_config.mutex); 1907 1908 if (sink) 1909 dc_sink_release(sink); 1910 } 1911 1912 static void handle_hpd_irq(void *param) 1913 { 1914 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param; 1915 struct drm_connector *connector = &aconnector->base; 1916 struct drm_device *dev = connector->dev; 1917 enum dc_connection_type new_connection_type = dc_connection_none; 1918 #ifdef CONFIG_DRM_AMD_DC_HDCP 1919 struct amdgpu_device *adev = dev->dev_private; 1920 #endif 1921 1922 /* 1923 * In case of failure or MST no need to update connector status or notify the OS 1924 * since (for MST case) MST does this in its own context. 1925 */ 1926 mutex_lock(&aconnector->hpd_lock); 1927 1928 #ifdef CONFIG_DRM_AMD_DC_HDCP 1929 if (adev->dm.hdcp_workqueue) 1930 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index); 1931 #endif 1932 if (aconnector->fake_enable) 1933 aconnector->fake_enable = false; 1934 1935 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type)) 1936 DRM_ERROR("KMS: Failed to detect connector\n"); 1937 1938 if (aconnector->base.force && new_connection_type == dc_connection_none) { 1939 emulated_link_detect(aconnector->dc_link); 1940 1941 1942 drm_modeset_lock_all(dev); 1943 dm_restore_drm_connector_state(dev, connector); 1944 drm_modeset_unlock_all(dev); 1945 1946 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) 1947 drm_kms_helper_hotplug_event(dev); 1948 1949 } else if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) { 1950 amdgpu_dm_update_connector_after_detect(aconnector); 1951 1952 1953 drm_modeset_lock_all(dev); 1954 dm_restore_drm_connector_state(dev, connector); 1955 drm_modeset_unlock_all(dev); 1956 1957 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) 1958 drm_kms_helper_hotplug_event(dev); 1959 } 1960 mutex_unlock(&aconnector->hpd_lock); 1961 1962 } 1963 1964 static void dm_handle_hpd_rx_irq(struct amdgpu_dm_connector *aconnector) 1965 { 1966 uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 }; 1967 uint8_t dret; 1968 bool new_irq_handled = false; 1969 int dpcd_addr; 1970 int dpcd_bytes_to_read; 1971 1972 const int max_process_count = 30; 1973 int process_count = 0; 1974 1975 const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link); 1976 1977 if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) { 1978 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT; 1979 /* DPCD 0x200 - 0x201 for downstream IRQ */ 1980 dpcd_addr = DP_SINK_COUNT; 1981 } else { 1982 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI; 1983 /* DPCD 0x2002 - 0x2005 for downstream IRQ */ 1984 dpcd_addr = DP_SINK_COUNT_ESI; 1985 } 1986 1987 dret = drm_dp_dpcd_read( 1988 &aconnector->dm_dp_aux.aux, 1989 dpcd_addr, 1990 esi, 1991 dpcd_bytes_to_read); 1992 1993 while (dret == dpcd_bytes_to_read && 1994 process_count < max_process_count) { 1995 uint8_t retry; 1996 dret = 0; 1997 1998 process_count++; 1999 2000 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]); 2001 /* handle HPD short pulse irq */ 2002 if (aconnector->mst_mgr.mst_state) 2003 drm_dp_mst_hpd_irq( 2004 &aconnector->mst_mgr, 2005 esi, 2006 &new_irq_handled); 2007 2008 if (new_irq_handled) { 2009 /* ACK at DPCD to notify down stream */ 2010 const int ack_dpcd_bytes_to_write = 2011 dpcd_bytes_to_read - 1; 2012 2013 for (retry = 0; retry < 3; retry++) { 2014 uint8_t wret; 2015 2016 wret = drm_dp_dpcd_write( 2017 &aconnector->dm_dp_aux.aux, 2018 dpcd_addr + 1, 2019 &esi[1], 2020 ack_dpcd_bytes_to_write); 2021 if (wret == ack_dpcd_bytes_to_write) 2022 break; 2023 } 2024 2025 /* check if there is new irq to be handled */ 2026 dret = drm_dp_dpcd_read( 2027 &aconnector->dm_dp_aux.aux, 2028 dpcd_addr, 2029 esi, 2030 dpcd_bytes_to_read); 2031 2032 new_irq_handled = false; 2033 } else { 2034 break; 2035 } 2036 } 2037 2038 if (process_count == max_process_count) 2039 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n"); 2040 } 2041 2042 static void handle_hpd_rx_irq(void *param) 2043 { 2044 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param; 2045 struct drm_connector *connector = &aconnector->base; 2046 struct drm_device *dev = connector->dev; 2047 struct dc_link *dc_link = aconnector->dc_link; 2048 bool is_mst_root_connector = aconnector->mst_mgr.mst_state; 2049 enum dc_connection_type new_connection_type = dc_connection_none; 2050 #ifdef CONFIG_DRM_AMD_DC_HDCP 2051 union hpd_irq_data hpd_irq_data; 2052 struct amdgpu_device *adev = dev->dev_private; 2053 2054 memset(&hpd_irq_data, 0, sizeof(hpd_irq_data)); 2055 #endif 2056 2057 /* 2058 * TODO:Temporary add mutex to protect hpd interrupt not have a gpio 2059 * conflict, after implement i2c helper, this mutex should be 2060 * retired. 2061 */ 2062 if (dc_link->type != dc_connection_mst_branch) 2063 mutex_lock(&aconnector->hpd_lock); 2064 2065 2066 #ifdef CONFIG_DRM_AMD_DC_HDCP 2067 if (dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data, NULL) && 2068 #else 2069 if (dc_link_handle_hpd_rx_irq(dc_link, NULL, NULL) && 2070 #endif 2071 !is_mst_root_connector) { 2072 /* Downstream Port status changed. */ 2073 if (!dc_link_detect_sink(dc_link, &new_connection_type)) 2074 DRM_ERROR("KMS: Failed to detect connector\n"); 2075 2076 if (aconnector->base.force && new_connection_type == dc_connection_none) { 2077 emulated_link_detect(dc_link); 2078 2079 if (aconnector->fake_enable) 2080 aconnector->fake_enable = false; 2081 2082 amdgpu_dm_update_connector_after_detect(aconnector); 2083 2084 2085 drm_modeset_lock_all(dev); 2086 dm_restore_drm_connector_state(dev, connector); 2087 drm_modeset_unlock_all(dev); 2088 2089 drm_kms_helper_hotplug_event(dev); 2090 } else if (dc_link_detect(dc_link, DETECT_REASON_HPDRX)) { 2091 2092 if (aconnector->fake_enable) 2093 aconnector->fake_enable = false; 2094 2095 amdgpu_dm_update_connector_after_detect(aconnector); 2096 2097 2098 drm_modeset_lock_all(dev); 2099 dm_restore_drm_connector_state(dev, connector); 2100 drm_modeset_unlock_all(dev); 2101 2102 drm_kms_helper_hotplug_event(dev); 2103 } 2104 } 2105 #ifdef CONFIG_DRM_AMD_DC_HDCP 2106 if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ) { 2107 if (adev->dm.hdcp_workqueue) 2108 hdcp_handle_cpirq(adev->dm.hdcp_workqueue, aconnector->base.index); 2109 } 2110 #endif 2111 if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) || 2112 (dc_link->type == dc_connection_mst_branch)) 2113 dm_handle_hpd_rx_irq(aconnector); 2114 2115 if (dc_link->type != dc_connection_mst_branch) { 2116 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux); 2117 mutex_unlock(&aconnector->hpd_lock); 2118 } 2119 } 2120 2121 static void register_hpd_handlers(struct amdgpu_device *adev) 2122 { 2123 struct drm_device *dev = adev->ddev; 2124 struct drm_connector *connector; 2125 struct amdgpu_dm_connector *aconnector; 2126 const struct dc_link *dc_link; 2127 struct dc_interrupt_params int_params = {0}; 2128 2129 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 2130 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 2131 2132 list_for_each_entry(connector, 2133 &dev->mode_config.connector_list, head) { 2134 2135 aconnector = to_amdgpu_dm_connector(connector); 2136 dc_link = aconnector->dc_link; 2137 2138 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) { 2139 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; 2140 int_params.irq_source = dc_link->irq_source_hpd; 2141 2142 amdgpu_dm_irq_register_interrupt(adev, &int_params, 2143 handle_hpd_irq, 2144 (void *) aconnector); 2145 } 2146 2147 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) { 2148 2149 /* Also register for DP short pulse (hpd_rx). */ 2150 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; 2151 int_params.irq_source = dc_link->irq_source_hpd_rx; 2152 2153 amdgpu_dm_irq_register_interrupt(adev, &int_params, 2154 handle_hpd_rx_irq, 2155 (void *) aconnector); 2156 } 2157 } 2158 } 2159 2160 /* Register IRQ sources and initialize IRQ callbacks */ 2161 static int dce110_register_irq_handlers(struct amdgpu_device *adev) 2162 { 2163 struct dc *dc = adev->dm.dc; 2164 struct common_irq_params *c_irq_params; 2165 struct dc_interrupt_params int_params = {0}; 2166 int r; 2167 int i; 2168 unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY; 2169 2170 if (adev->asic_type >= CHIP_VEGA10) 2171 client_id = SOC15_IH_CLIENTID_DCE; 2172 2173 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 2174 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 2175 2176 /* 2177 * Actions of amdgpu_irq_add_id(): 2178 * 1. Register a set() function with base driver. 2179 * Base driver will call set() function to enable/disable an 2180 * interrupt in DC hardware. 2181 * 2. Register amdgpu_dm_irq_handler(). 2182 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts 2183 * coming from DC hardware. 2184 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC 2185 * for acknowledging and handling. */ 2186 2187 /* Use VBLANK interrupt */ 2188 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) { 2189 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq); 2190 if (r) { 2191 DRM_ERROR("Failed to add crtc irq id!\n"); 2192 return r; 2193 } 2194 2195 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 2196 int_params.irq_source = 2197 dc_interrupt_to_irq_source(dc, i, 0); 2198 2199 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; 2200 2201 c_irq_params->adev = adev; 2202 c_irq_params->irq_src = int_params.irq_source; 2203 2204 amdgpu_dm_irq_register_interrupt(adev, &int_params, 2205 dm_crtc_high_irq, c_irq_params); 2206 } 2207 2208 /* Use VUPDATE interrupt */ 2209 for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) { 2210 r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq); 2211 if (r) { 2212 DRM_ERROR("Failed to add vupdate irq id!\n"); 2213 return r; 2214 } 2215 2216 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 2217 int_params.irq_source = 2218 dc_interrupt_to_irq_source(dc, i, 0); 2219 2220 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1]; 2221 2222 c_irq_params->adev = adev; 2223 c_irq_params->irq_src = int_params.irq_source; 2224 2225 amdgpu_dm_irq_register_interrupt(adev, &int_params, 2226 dm_vupdate_high_irq, c_irq_params); 2227 } 2228 2229 /* Use GRPH_PFLIP interrupt */ 2230 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; 2231 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) { 2232 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq); 2233 if (r) { 2234 DRM_ERROR("Failed to add page flip irq id!\n"); 2235 return r; 2236 } 2237 2238 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 2239 int_params.irq_source = 2240 dc_interrupt_to_irq_source(dc, i, 0); 2241 2242 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; 2243 2244 c_irq_params->adev = adev; 2245 c_irq_params->irq_src = int_params.irq_source; 2246 2247 amdgpu_dm_irq_register_interrupt(adev, &int_params, 2248 dm_pflip_high_irq, c_irq_params); 2249 2250 } 2251 2252 /* HPD */ 2253 r = amdgpu_irq_add_id(adev, client_id, 2254 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq); 2255 if (r) { 2256 DRM_ERROR("Failed to add hpd irq id!\n"); 2257 return r; 2258 } 2259 2260 register_hpd_handlers(adev); 2261 2262 return 0; 2263 } 2264 2265 #if defined(CONFIG_DRM_AMD_DC_DCN) 2266 /* Register IRQ sources and initialize IRQ callbacks */ 2267 static int dcn10_register_irq_handlers(struct amdgpu_device *adev) 2268 { 2269 struct dc *dc = adev->dm.dc; 2270 struct common_irq_params *c_irq_params; 2271 struct dc_interrupt_params int_params = {0}; 2272 int r; 2273 int i; 2274 2275 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 2276 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 2277 2278 /* 2279 * Actions of amdgpu_irq_add_id(): 2280 * 1. Register a set() function with base driver. 2281 * Base driver will call set() function to enable/disable an 2282 * interrupt in DC hardware. 2283 * 2. Register amdgpu_dm_irq_handler(). 2284 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts 2285 * coming from DC hardware. 2286 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC 2287 * for acknowledging and handling. 2288 */ 2289 2290 /* Use VSTARTUP interrupt */ 2291 for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP; 2292 i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1; 2293 i++) { 2294 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq); 2295 2296 if (r) { 2297 DRM_ERROR("Failed to add crtc irq id!\n"); 2298 return r; 2299 } 2300 2301 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 2302 int_params.irq_source = 2303 dc_interrupt_to_irq_source(dc, i, 0); 2304 2305 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; 2306 2307 c_irq_params->adev = adev; 2308 c_irq_params->irq_src = int_params.irq_source; 2309 2310 amdgpu_dm_irq_register_interrupt(adev, &int_params, 2311 dm_dcn_crtc_high_irq, c_irq_params); 2312 } 2313 2314 /* Use GRPH_PFLIP interrupt */ 2315 for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT; 2316 i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1; 2317 i++) { 2318 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq); 2319 if (r) { 2320 DRM_ERROR("Failed to add page flip irq id!\n"); 2321 return r; 2322 } 2323 2324 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 2325 int_params.irq_source = 2326 dc_interrupt_to_irq_source(dc, i, 0); 2327 2328 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; 2329 2330 c_irq_params->adev = adev; 2331 c_irq_params->irq_src = int_params.irq_source; 2332 2333 amdgpu_dm_irq_register_interrupt(adev, &int_params, 2334 dm_pflip_high_irq, c_irq_params); 2335 2336 } 2337 2338 /* HPD */ 2339 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT, 2340 &adev->hpd_irq); 2341 if (r) { 2342 DRM_ERROR("Failed to add hpd irq id!\n"); 2343 return r; 2344 } 2345 2346 register_hpd_handlers(adev); 2347 2348 return 0; 2349 } 2350 #endif 2351 2352 /* 2353 * Acquires the lock for the atomic state object and returns 2354 * the new atomic state. 2355 * 2356 * This should only be called during atomic check. 2357 */ 2358 static int dm_atomic_get_state(struct drm_atomic_state *state, 2359 struct dm_atomic_state **dm_state) 2360 { 2361 struct drm_device *dev = state->dev; 2362 struct amdgpu_device *adev = dev->dev_private; 2363 struct amdgpu_display_manager *dm = &adev->dm; 2364 struct drm_private_state *priv_state; 2365 2366 if (*dm_state) 2367 return 0; 2368 2369 priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj); 2370 if (IS_ERR(priv_state)) 2371 return PTR_ERR(priv_state); 2372 2373 *dm_state = to_dm_atomic_state(priv_state); 2374 2375 return 0; 2376 } 2377 2378 struct dm_atomic_state * 2379 dm_atomic_get_new_state(struct drm_atomic_state *state) 2380 { 2381 struct drm_device *dev = state->dev; 2382 struct amdgpu_device *adev = dev->dev_private; 2383 struct amdgpu_display_manager *dm = &adev->dm; 2384 struct drm_private_obj *obj; 2385 struct drm_private_state *new_obj_state; 2386 int i; 2387 2388 for_each_new_private_obj_in_state(state, obj, new_obj_state, i) { 2389 if (obj->funcs == dm->atomic_obj.funcs) 2390 return to_dm_atomic_state(new_obj_state); 2391 } 2392 2393 return NULL; 2394 } 2395 2396 struct dm_atomic_state * 2397 dm_atomic_get_old_state(struct drm_atomic_state *state) 2398 { 2399 struct drm_device *dev = state->dev; 2400 struct amdgpu_device *adev = dev->dev_private; 2401 struct amdgpu_display_manager *dm = &adev->dm; 2402 struct drm_private_obj *obj; 2403 struct drm_private_state *old_obj_state; 2404 int i; 2405 2406 for_each_old_private_obj_in_state(state, obj, old_obj_state, i) { 2407 if (obj->funcs == dm->atomic_obj.funcs) 2408 return to_dm_atomic_state(old_obj_state); 2409 } 2410 2411 return NULL; 2412 } 2413 2414 static struct drm_private_state * 2415 dm_atomic_duplicate_state(struct drm_private_obj *obj) 2416 { 2417 struct dm_atomic_state *old_state, *new_state; 2418 2419 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL); 2420 if (!new_state) 2421 return NULL; 2422 2423 __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base); 2424 2425 old_state = to_dm_atomic_state(obj->state); 2426 2427 if (old_state && old_state->context) 2428 new_state->context = dc_copy_state(old_state->context); 2429 2430 if (!new_state->context) { 2431 kfree(new_state); 2432 return NULL; 2433 } 2434 2435 return &new_state->base; 2436 } 2437 2438 static void dm_atomic_destroy_state(struct drm_private_obj *obj, 2439 struct drm_private_state *state) 2440 { 2441 struct dm_atomic_state *dm_state = to_dm_atomic_state(state); 2442 2443 if (dm_state && dm_state->context) 2444 dc_release_state(dm_state->context); 2445 2446 kfree(dm_state); 2447 } 2448 2449 static struct drm_private_state_funcs dm_atomic_state_funcs = { 2450 .atomic_duplicate_state = dm_atomic_duplicate_state, 2451 .atomic_destroy_state = dm_atomic_destroy_state, 2452 }; 2453 2454 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) 2455 { 2456 struct dm_atomic_state *state; 2457 int r; 2458 2459 adev->mode_info.mode_config_initialized = true; 2460 2461 adev->ddev->mode_config.funcs = &amdgpu_dm_mode_funcs; 2462 adev->ddev->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs; 2463 2464 adev->ddev->mode_config.max_width = 16384; 2465 adev->ddev->mode_config.max_height = 16384; 2466 2467 adev->ddev->mode_config.preferred_depth = 24; 2468 adev->ddev->mode_config.prefer_shadow = 1; 2469 /* indicates support for immediate flip */ 2470 adev->ddev->mode_config.async_page_flip = true; 2471 2472 adev->ddev->mode_config.fb_base = adev->gmc.aper_base; 2473 2474 state = kzalloc(sizeof(*state), GFP_KERNEL); 2475 if (!state) 2476 return -ENOMEM; 2477 2478 state->context = dc_create_state(adev->dm.dc); 2479 if (!state->context) { 2480 kfree(state); 2481 return -ENOMEM; 2482 } 2483 2484 dc_resource_state_copy_construct_current(adev->dm.dc, state->context); 2485 2486 drm_atomic_private_obj_init(adev->ddev, 2487 &adev->dm.atomic_obj, 2488 &state->base, 2489 &dm_atomic_state_funcs); 2490 2491 r = amdgpu_display_modeset_create_props(adev); 2492 if (r) 2493 return r; 2494 2495 r = amdgpu_dm_audio_init(adev); 2496 if (r) 2497 return r; 2498 2499 return 0; 2500 } 2501 2502 #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12 2503 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255 2504 2505 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\ 2506 IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 2507 2508 static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm) 2509 { 2510 #if IS_ENABLED(CONFIG_ACPI) 2511 struct amdgpu_dm_backlight_caps caps; 2512 2513 if (dm->backlight_caps.caps_valid) 2514 return; 2515 2516 amdgpu_acpi_get_backlight_caps(dm->adev, &caps); 2517 if (caps.caps_valid) { 2518 dm->backlight_caps.min_input_signal = caps.min_input_signal; 2519 dm->backlight_caps.max_input_signal = caps.max_input_signal; 2520 dm->backlight_caps.caps_valid = true; 2521 } else { 2522 dm->backlight_caps.min_input_signal = 2523 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT; 2524 dm->backlight_caps.max_input_signal = 2525 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT; 2526 } 2527 #else 2528 dm->backlight_caps.min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT; 2529 dm->backlight_caps.max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT; 2530 #endif 2531 } 2532 2533 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd) 2534 { 2535 struct amdgpu_display_manager *dm = bl_get_data(bd); 2536 struct amdgpu_dm_backlight_caps caps; 2537 uint32_t brightness = bd->props.brightness; 2538 2539 amdgpu_dm_update_backlight_caps(dm); 2540 caps = dm->backlight_caps; 2541 /* 2542 * The brightness input is in the range 0-255 2543 * It needs to be rescaled to be between the 2544 * requested min and max input signal 2545 * 2546 * It also needs to be scaled up by 0x101 to 2547 * match the DC interface which has a range of 2548 * 0 to 0xffff 2549 */ 2550 brightness = 2551 brightness 2552 * 0x101 2553 * (caps.max_input_signal - caps.min_input_signal) 2554 / AMDGPU_MAX_BL_LEVEL 2555 + caps.min_input_signal * 0x101; 2556 2557 if (dc_link_set_backlight_level(dm->backlight_link, 2558 brightness, 0)) 2559 return 0; 2560 else 2561 return 1; 2562 } 2563 2564 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd) 2565 { 2566 struct amdgpu_display_manager *dm = bl_get_data(bd); 2567 int ret = dc_link_get_backlight_level(dm->backlight_link); 2568 2569 if (ret == DC_ERROR_UNEXPECTED) 2570 return bd->props.brightness; 2571 return ret; 2572 } 2573 2574 static const struct backlight_ops amdgpu_dm_backlight_ops = { 2575 .options = BL_CORE_SUSPENDRESUME, 2576 .get_brightness = amdgpu_dm_backlight_get_brightness, 2577 .update_status = amdgpu_dm_backlight_update_status, 2578 }; 2579 2580 static void 2581 amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm) 2582 { 2583 char bl_name[16]; 2584 struct backlight_properties props = { 0 }; 2585 2586 amdgpu_dm_update_backlight_caps(dm); 2587 2588 props.max_brightness = AMDGPU_MAX_BL_LEVEL; 2589 props.brightness = AMDGPU_MAX_BL_LEVEL; 2590 props.type = BACKLIGHT_RAW; 2591 2592 snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d", 2593 dm->adev->ddev->primary->index); 2594 2595 dm->backlight_dev = backlight_device_register(bl_name, 2596 dm->adev->ddev->dev, 2597 dm, 2598 &amdgpu_dm_backlight_ops, 2599 &props); 2600 2601 if (IS_ERR(dm->backlight_dev)) 2602 DRM_ERROR("DM: Backlight registration failed!\n"); 2603 else 2604 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name); 2605 } 2606 2607 #endif 2608 2609 static int initialize_plane(struct amdgpu_display_manager *dm, 2610 struct amdgpu_mode_info *mode_info, int plane_id, 2611 enum drm_plane_type plane_type, 2612 const struct dc_plane_cap *plane_cap) 2613 { 2614 struct drm_plane *plane; 2615 unsigned long possible_crtcs; 2616 int ret = 0; 2617 2618 plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL); 2619 if (!plane) { 2620 DRM_ERROR("KMS: Failed to allocate plane\n"); 2621 return -ENOMEM; 2622 } 2623 plane->type = plane_type; 2624 2625 /* 2626 * HACK: IGT tests expect that the primary plane for a CRTC 2627 * can only have one possible CRTC. Only expose support for 2628 * any CRTC if they're not going to be used as a primary plane 2629 * for a CRTC - like overlay or underlay planes. 2630 */ 2631 possible_crtcs = 1 << plane_id; 2632 if (plane_id >= dm->dc->caps.max_streams) 2633 possible_crtcs = 0xff; 2634 2635 ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap); 2636 2637 if (ret) { 2638 DRM_ERROR("KMS: Failed to initialize plane\n"); 2639 kfree(plane); 2640 return ret; 2641 } 2642 2643 if (mode_info) 2644 mode_info->planes[plane_id] = plane; 2645 2646 return ret; 2647 } 2648 2649 2650 static void register_backlight_device(struct amdgpu_display_manager *dm, 2651 struct dc_link *link) 2652 { 2653 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\ 2654 IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 2655 2656 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) && 2657 link->type != dc_connection_none) { 2658 /* 2659 * Event if registration failed, we should continue with 2660 * DM initialization because not having a backlight control 2661 * is better then a black screen. 2662 */ 2663 amdgpu_dm_register_backlight_device(dm); 2664 2665 if (dm->backlight_dev) 2666 dm->backlight_link = link; 2667 } 2668 #endif 2669 } 2670 2671 2672 /* 2673 * In this architecture, the association 2674 * connector -> encoder -> crtc 2675 * id not really requried. The crtc and connector will hold the 2676 * display_index as an abstraction to use with DAL component 2677 * 2678 * Returns 0 on success 2679 */ 2680 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) 2681 { 2682 struct amdgpu_display_manager *dm = &adev->dm; 2683 int32_t i; 2684 struct amdgpu_dm_connector *aconnector = NULL; 2685 struct amdgpu_encoder *aencoder = NULL; 2686 struct amdgpu_mode_info *mode_info = &adev->mode_info; 2687 uint32_t link_cnt; 2688 int32_t primary_planes; 2689 enum dc_connection_type new_connection_type = dc_connection_none; 2690 const struct dc_plane_cap *plane; 2691 2692 link_cnt = dm->dc->caps.max_links; 2693 if (amdgpu_dm_mode_config_init(dm->adev)) { 2694 DRM_ERROR("DM: Failed to initialize mode config\n"); 2695 return -EINVAL; 2696 } 2697 2698 /* There is one primary plane per CRTC */ 2699 primary_planes = dm->dc->caps.max_streams; 2700 ASSERT(primary_planes <= AMDGPU_MAX_PLANES); 2701 2702 /* 2703 * Initialize primary planes, implicit planes for legacy IOCTLS. 2704 * Order is reversed to match iteration order in atomic check. 2705 */ 2706 for (i = (primary_planes - 1); i >= 0; i--) { 2707 plane = &dm->dc->caps.planes[i]; 2708 2709 if (initialize_plane(dm, mode_info, i, 2710 DRM_PLANE_TYPE_PRIMARY, plane)) { 2711 DRM_ERROR("KMS: Failed to initialize primary plane\n"); 2712 goto fail; 2713 } 2714 } 2715 2716 /* 2717 * Initialize overlay planes, index starting after primary planes. 2718 * These planes have a higher DRM index than the primary planes since 2719 * they should be considered as having a higher z-order. 2720 * Order is reversed to match iteration order in atomic check. 2721 * 2722 * Only support DCN for now, and only expose one so we don't encourage 2723 * userspace to use up all the pipes. 2724 */ 2725 for (i = 0; i < dm->dc->caps.max_planes; ++i) { 2726 struct dc_plane_cap *plane = &dm->dc->caps.planes[i]; 2727 2728 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL) 2729 continue; 2730 2731 if (!plane->blends_with_above || !plane->blends_with_below) 2732 continue; 2733 2734 if (!plane->pixel_format_support.argb8888) 2735 continue; 2736 2737 if (initialize_plane(dm, NULL, primary_planes + i, 2738 DRM_PLANE_TYPE_OVERLAY, plane)) { 2739 DRM_ERROR("KMS: Failed to initialize overlay plane\n"); 2740 goto fail; 2741 } 2742 2743 /* Only create one overlay plane. */ 2744 break; 2745 } 2746 2747 for (i = 0; i < dm->dc->caps.max_streams; i++) 2748 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) { 2749 DRM_ERROR("KMS: Failed to initialize crtc\n"); 2750 goto fail; 2751 } 2752 2753 dm->display_indexes_num = dm->dc->caps.max_streams; 2754 2755 /* loops over all connectors on the board */ 2756 for (i = 0; i < link_cnt; i++) { 2757 struct dc_link *link = NULL; 2758 2759 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) { 2760 DRM_ERROR( 2761 "KMS: Cannot support more than %d display indexes\n", 2762 AMDGPU_DM_MAX_DISPLAY_INDEX); 2763 continue; 2764 } 2765 2766 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL); 2767 if (!aconnector) 2768 goto fail; 2769 2770 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL); 2771 if (!aencoder) 2772 goto fail; 2773 2774 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) { 2775 DRM_ERROR("KMS: Failed to initialize encoder\n"); 2776 goto fail; 2777 } 2778 2779 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) { 2780 DRM_ERROR("KMS: Failed to initialize connector\n"); 2781 goto fail; 2782 } 2783 2784 link = dc_get_link_at_index(dm->dc, i); 2785 2786 if (!dc_link_detect_sink(link, &new_connection_type)) 2787 DRM_ERROR("KMS: Failed to detect connector\n"); 2788 2789 if (aconnector->base.force && new_connection_type == dc_connection_none) { 2790 emulated_link_detect(link); 2791 amdgpu_dm_update_connector_after_detect(aconnector); 2792 2793 } else if (dc_link_detect(link, DETECT_REASON_BOOT)) { 2794 amdgpu_dm_update_connector_after_detect(aconnector); 2795 register_backlight_device(dm, link); 2796 if (amdgpu_dc_feature_mask & DC_PSR_MASK) 2797 amdgpu_dm_set_psr_caps(link); 2798 } 2799 2800 2801 } 2802 2803 /* Software is initialized. Now we can register interrupt handlers. */ 2804 switch (adev->asic_type) { 2805 case CHIP_BONAIRE: 2806 case CHIP_HAWAII: 2807 case CHIP_KAVERI: 2808 case CHIP_KABINI: 2809 case CHIP_MULLINS: 2810 case CHIP_TONGA: 2811 case CHIP_FIJI: 2812 case CHIP_CARRIZO: 2813 case CHIP_STONEY: 2814 case CHIP_POLARIS11: 2815 case CHIP_POLARIS10: 2816 case CHIP_POLARIS12: 2817 case CHIP_VEGAM: 2818 case CHIP_VEGA10: 2819 case CHIP_VEGA12: 2820 case CHIP_VEGA20: 2821 if (dce110_register_irq_handlers(dm->adev)) { 2822 DRM_ERROR("DM: Failed to initialize IRQ\n"); 2823 goto fail; 2824 } 2825 break; 2826 #if defined(CONFIG_DRM_AMD_DC_DCN) 2827 case CHIP_RAVEN: 2828 case CHIP_NAVI12: 2829 case CHIP_NAVI10: 2830 case CHIP_NAVI14: 2831 case CHIP_RENOIR: 2832 if (dcn10_register_irq_handlers(dm->adev)) { 2833 DRM_ERROR("DM: Failed to initialize IRQ\n"); 2834 goto fail; 2835 } 2836 break; 2837 #endif 2838 default: 2839 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type); 2840 goto fail; 2841 } 2842 2843 if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY) 2844 dm->dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true; 2845 2846 return 0; 2847 fail: 2848 kfree(aencoder); 2849 kfree(aconnector); 2850 2851 return -EINVAL; 2852 } 2853 2854 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm) 2855 { 2856 drm_mode_config_cleanup(dm->ddev); 2857 drm_atomic_private_obj_fini(&dm->atomic_obj); 2858 return; 2859 } 2860 2861 /****************************************************************************** 2862 * amdgpu_display_funcs functions 2863 *****************************************************************************/ 2864 2865 /* 2866 * dm_bandwidth_update - program display watermarks 2867 * 2868 * @adev: amdgpu_device pointer 2869 * 2870 * Calculate and program the display watermarks and line buffer allocation. 2871 */ 2872 static void dm_bandwidth_update(struct amdgpu_device *adev) 2873 { 2874 /* TODO: implement later */ 2875 } 2876 2877 static const struct amdgpu_display_funcs dm_display_funcs = { 2878 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */ 2879 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */ 2880 .backlight_set_level = NULL, /* never called for DC */ 2881 .backlight_get_level = NULL, /* never called for DC */ 2882 .hpd_sense = NULL,/* called unconditionally */ 2883 .hpd_set_polarity = NULL, /* called unconditionally */ 2884 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */ 2885 .page_flip_get_scanoutpos = 2886 dm_crtc_get_scanoutpos,/* called unconditionally */ 2887 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */ 2888 .add_connector = NULL, /* VBIOS parsing. DAL does it. */ 2889 }; 2890 2891 #if defined(CONFIG_DEBUG_KERNEL_DC) 2892 2893 static ssize_t s3_debug_store(struct device *device, 2894 struct device_attribute *attr, 2895 const char *buf, 2896 size_t count) 2897 { 2898 int ret; 2899 int s3_state; 2900 struct drm_device *drm_dev = dev_get_drvdata(device); 2901 struct amdgpu_device *adev = drm_dev->dev_private; 2902 2903 ret = kstrtoint(buf, 0, &s3_state); 2904 2905 if (ret == 0) { 2906 if (s3_state) { 2907 dm_resume(adev); 2908 drm_kms_helper_hotplug_event(adev->ddev); 2909 } else 2910 dm_suspend(adev); 2911 } 2912 2913 return ret == 0 ? count : 0; 2914 } 2915 2916 DEVICE_ATTR_WO(s3_debug); 2917 2918 #endif 2919 2920 static int dm_early_init(void *handle) 2921 { 2922 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2923 2924 switch (adev->asic_type) { 2925 case CHIP_BONAIRE: 2926 case CHIP_HAWAII: 2927 adev->mode_info.num_crtc = 6; 2928 adev->mode_info.num_hpd = 6; 2929 adev->mode_info.num_dig = 6; 2930 break; 2931 case CHIP_KAVERI: 2932 adev->mode_info.num_crtc = 4; 2933 adev->mode_info.num_hpd = 6; 2934 adev->mode_info.num_dig = 7; 2935 break; 2936 case CHIP_KABINI: 2937 case CHIP_MULLINS: 2938 adev->mode_info.num_crtc = 2; 2939 adev->mode_info.num_hpd = 6; 2940 adev->mode_info.num_dig = 6; 2941 break; 2942 case CHIP_FIJI: 2943 case CHIP_TONGA: 2944 adev->mode_info.num_crtc = 6; 2945 adev->mode_info.num_hpd = 6; 2946 adev->mode_info.num_dig = 7; 2947 break; 2948 case CHIP_CARRIZO: 2949 adev->mode_info.num_crtc = 3; 2950 adev->mode_info.num_hpd = 6; 2951 adev->mode_info.num_dig = 9; 2952 break; 2953 case CHIP_STONEY: 2954 adev->mode_info.num_crtc = 2; 2955 adev->mode_info.num_hpd = 6; 2956 adev->mode_info.num_dig = 9; 2957 break; 2958 case CHIP_POLARIS11: 2959 case CHIP_POLARIS12: 2960 adev->mode_info.num_crtc = 5; 2961 adev->mode_info.num_hpd = 5; 2962 adev->mode_info.num_dig = 5; 2963 break; 2964 case CHIP_POLARIS10: 2965 case CHIP_VEGAM: 2966 adev->mode_info.num_crtc = 6; 2967 adev->mode_info.num_hpd = 6; 2968 adev->mode_info.num_dig = 6; 2969 break; 2970 case CHIP_VEGA10: 2971 case CHIP_VEGA12: 2972 case CHIP_VEGA20: 2973 adev->mode_info.num_crtc = 6; 2974 adev->mode_info.num_hpd = 6; 2975 adev->mode_info.num_dig = 6; 2976 break; 2977 #if defined(CONFIG_DRM_AMD_DC_DCN) 2978 case CHIP_RAVEN: 2979 adev->mode_info.num_crtc = 4; 2980 adev->mode_info.num_hpd = 4; 2981 adev->mode_info.num_dig = 4; 2982 break; 2983 #endif 2984 case CHIP_NAVI10: 2985 case CHIP_NAVI12: 2986 adev->mode_info.num_crtc = 6; 2987 adev->mode_info.num_hpd = 6; 2988 adev->mode_info.num_dig = 6; 2989 break; 2990 case CHIP_NAVI14: 2991 adev->mode_info.num_crtc = 5; 2992 adev->mode_info.num_hpd = 5; 2993 adev->mode_info.num_dig = 5; 2994 break; 2995 case CHIP_RENOIR: 2996 adev->mode_info.num_crtc = 4; 2997 adev->mode_info.num_hpd = 4; 2998 adev->mode_info.num_dig = 4; 2999 break; 3000 default: 3001 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type); 3002 return -EINVAL; 3003 } 3004 3005 amdgpu_dm_set_irq_funcs(adev); 3006 3007 if (adev->mode_info.funcs == NULL) 3008 adev->mode_info.funcs = &dm_display_funcs; 3009 3010 /* 3011 * Note: Do NOT change adev->audio_endpt_rreg and 3012 * adev->audio_endpt_wreg because they are initialised in 3013 * amdgpu_device_init() 3014 */ 3015 #if defined(CONFIG_DEBUG_KERNEL_DC) 3016 device_create_file( 3017 adev->ddev->dev, 3018 &dev_attr_s3_debug); 3019 #endif 3020 3021 return 0; 3022 } 3023 3024 static bool modeset_required(struct drm_crtc_state *crtc_state, 3025 struct dc_stream_state *new_stream, 3026 struct dc_stream_state *old_stream) 3027 { 3028 if (!drm_atomic_crtc_needs_modeset(crtc_state)) 3029 return false; 3030 3031 if (!crtc_state->enable) 3032 return false; 3033 3034 return crtc_state->active; 3035 } 3036 3037 static bool modereset_required(struct drm_crtc_state *crtc_state) 3038 { 3039 if (!drm_atomic_crtc_needs_modeset(crtc_state)) 3040 return false; 3041 3042 return !crtc_state->enable || !crtc_state->active; 3043 } 3044 3045 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder) 3046 { 3047 drm_encoder_cleanup(encoder); 3048 kfree(encoder); 3049 } 3050 3051 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = { 3052 .destroy = amdgpu_dm_encoder_destroy, 3053 }; 3054 3055 3056 static int fill_dc_scaling_info(const struct drm_plane_state *state, 3057 struct dc_scaling_info *scaling_info) 3058 { 3059 int scale_w, scale_h; 3060 3061 memset(scaling_info, 0, sizeof(*scaling_info)); 3062 3063 /* Source is fixed 16.16 but we ignore mantissa for now... */ 3064 scaling_info->src_rect.x = state->src_x >> 16; 3065 scaling_info->src_rect.y = state->src_y >> 16; 3066 3067 scaling_info->src_rect.width = state->src_w >> 16; 3068 if (scaling_info->src_rect.width == 0) 3069 return -EINVAL; 3070 3071 scaling_info->src_rect.height = state->src_h >> 16; 3072 if (scaling_info->src_rect.height == 0) 3073 return -EINVAL; 3074 3075 scaling_info->dst_rect.x = state->crtc_x; 3076 scaling_info->dst_rect.y = state->crtc_y; 3077 3078 if (state->crtc_w == 0) 3079 return -EINVAL; 3080 3081 scaling_info->dst_rect.width = state->crtc_w; 3082 3083 if (state->crtc_h == 0) 3084 return -EINVAL; 3085 3086 scaling_info->dst_rect.height = state->crtc_h; 3087 3088 /* DRM doesn't specify clipping on destination output. */ 3089 scaling_info->clip_rect = scaling_info->dst_rect; 3090 3091 /* TODO: Validate scaling per-format with DC plane caps */ 3092 scale_w = scaling_info->dst_rect.width * 1000 / 3093 scaling_info->src_rect.width; 3094 3095 if (scale_w < 250 || scale_w > 16000) 3096 return -EINVAL; 3097 3098 scale_h = scaling_info->dst_rect.height * 1000 / 3099 scaling_info->src_rect.height; 3100 3101 if (scale_h < 250 || scale_h > 16000) 3102 return -EINVAL; 3103 3104 /* 3105 * The "scaling_quality" can be ignored for now, quality = 0 has DC 3106 * assume reasonable defaults based on the format. 3107 */ 3108 3109 return 0; 3110 } 3111 3112 static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb, 3113 uint64_t *tiling_flags) 3114 { 3115 struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]); 3116 int r = amdgpu_bo_reserve(rbo, false); 3117 3118 if (unlikely(r)) { 3119 /* Don't show error message when returning -ERESTARTSYS */ 3120 if (r != -ERESTARTSYS) 3121 DRM_ERROR("Unable to reserve buffer: %d\n", r); 3122 return r; 3123 } 3124 3125 if (tiling_flags) 3126 amdgpu_bo_get_tiling_flags(rbo, tiling_flags); 3127 3128 amdgpu_bo_unreserve(rbo); 3129 3130 return r; 3131 } 3132 3133 static inline uint64_t get_dcc_address(uint64_t address, uint64_t tiling_flags) 3134 { 3135 uint32_t offset = AMDGPU_TILING_GET(tiling_flags, DCC_OFFSET_256B); 3136 3137 return offset ? (address + offset * 256) : 0; 3138 } 3139 3140 static int 3141 fill_plane_dcc_attributes(struct amdgpu_device *adev, 3142 const struct amdgpu_framebuffer *afb, 3143 const enum surface_pixel_format format, 3144 const enum dc_rotation_angle rotation, 3145 const struct plane_size *plane_size, 3146 const union dc_tiling_info *tiling_info, 3147 const uint64_t info, 3148 struct dc_plane_dcc_param *dcc, 3149 struct dc_plane_address *address) 3150 { 3151 struct dc *dc = adev->dm.dc; 3152 struct dc_dcc_surface_param input; 3153 struct dc_surface_dcc_cap output; 3154 uint32_t offset = AMDGPU_TILING_GET(info, DCC_OFFSET_256B); 3155 uint32_t i64b = AMDGPU_TILING_GET(info, DCC_INDEPENDENT_64B) != 0; 3156 uint64_t dcc_address; 3157 3158 memset(&input, 0, sizeof(input)); 3159 memset(&output, 0, sizeof(output)); 3160 3161 if (!offset) 3162 return 0; 3163 3164 if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 3165 return 0; 3166 3167 if (!dc->cap_funcs.get_dcc_compression_cap) 3168 return -EINVAL; 3169 3170 input.format = format; 3171 input.surface_size.width = plane_size->surface_size.width; 3172 input.surface_size.height = plane_size->surface_size.height; 3173 input.swizzle_mode = tiling_info->gfx9.swizzle; 3174 3175 if (rotation == ROTATION_ANGLE_0 || rotation == ROTATION_ANGLE_180) 3176 input.scan = SCAN_DIRECTION_HORIZONTAL; 3177 else if (rotation == ROTATION_ANGLE_90 || rotation == ROTATION_ANGLE_270) 3178 input.scan = SCAN_DIRECTION_VERTICAL; 3179 3180 if (!dc->cap_funcs.get_dcc_compression_cap(dc, &input, &output)) 3181 return -EINVAL; 3182 3183 if (!output.capable) 3184 return -EINVAL; 3185 3186 if (i64b == 0 && output.grph.rgb.independent_64b_blks != 0) 3187 return -EINVAL; 3188 3189 dcc->enable = 1; 3190 dcc->meta_pitch = 3191 AMDGPU_TILING_GET(info, DCC_PITCH_MAX) + 1; 3192 dcc->independent_64b_blks = i64b; 3193 3194 dcc_address = get_dcc_address(afb->address, info); 3195 address->grph.meta_addr.low_part = lower_32_bits(dcc_address); 3196 address->grph.meta_addr.high_part = upper_32_bits(dcc_address); 3197 3198 return 0; 3199 } 3200 3201 static int 3202 fill_plane_buffer_attributes(struct amdgpu_device *adev, 3203 const struct amdgpu_framebuffer *afb, 3204 const enum surface_pixel_format format, 3205 const enum dc_rotation_angle rotation, 3206 const uint64_t tiling_flags, 3207 union dc_tiling_info *tiling_info, 3208 struct plane_size *plane_size, 3209 struct dc_plane_dcc_param *dcc, 3210 struct dc_plane_address *address) 3211 { 3212 const struct drm_framebuffer *fb = &afb->base; 3213 int ret; 3214 3215 memset(tiling_info, 0, sizeof(*tiling_info)); 3216 memset(plane_size, 0, sizeof(*plane_size)); 3217 memset(dcc, 0, sizeof(*dcc)); 3218 memset(address, 0, sizeof(*address)); 3219 3220 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { 3221 plane_size->surface_size.x = 0; 3222 plane_size->surface_size.y = 0; 3223 plane_size->surface_size.width = fb->width; 3224 plane_size->surface_size.height = fb->height; 3225 plane_size->surface_pitch = 3226 fb->pitches[0] / fb->format->cpp[0]; 3227 3228 address->type = PLN_ADDR_TYPE_GRAPHICS; 3229 address->grph.addr.low_part = lower_32_bits(afb->address); 3230 address->grph.addr.high_part = upper_32_bits(afb->address); 3231 } else if (format < SURFACE_PIXEL_FORMAT_INVALID) { 3232 uint64_t chroma_addr = afb->address + fb->offsets[1]; 3233 3234 plane_size->surface_size.x = 0; 3235 plane_size->surface_size.y = 0; 3236 plane_size->surface_size.width = fb->width; 3237 plane_size->surface_size.height = fb->height; 3238 plane_size->surface_pitch = 3239 fb->pitches[0] / fb->format->cpp[0]; 3240 3241 plane_size->chroma_size.x = 0; 3242 plane_size->chroma_size.y = 0; 3243 /* TODO: set these based on surface format */ 3244 plane_size->chroma_size.width = fb->width / 2; 3245 plane_size->chroma_size.height = fb->height / 2; 3246 3247 plane_size->chroma_pitch = 3248 fb->pitches[1] / fb->format->cpp[1]; 3249 3250 address->type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE; 3251 address->video_progressive.luma_addr.low_part = 3252 lower_32_bits(afb->address); 3253 address->video_progressive.luma_addr.high_part = 3254 upper_32_bits(afb->address); 3255 address->video_progressive.chroma_addr.low_part = 3256 lower_32_bits(chroma_addr); 3257 address->video_progressive.chroma_addr.high_part = 3258 upper_32_bits(chroma_addr); 3259 } 3260 3261 /* Fill GFX8 params */ 3262 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) { 3263 unsigned int bankw, bankh, mtaspect, tile_split, num_banks; 3264 3265 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); 3266 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); 3267 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); 3268 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); 3269 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); 3270 3271 /* XXX fix me for VI */ 3272 tiling_info->gfx8.num_banks = num_banks; 3273 tiling_info->gfx8.array_mode = 3274 DC_ARRAY_2D_TILED_THIN1; 3275 tiling_info->gfx8.tile_split = tile_split; 3276 tiling_info->gfx8.bank_width = bankw; 3277 tiling_info->gfx8.bank_height = bankh; 3278 tiling_info->gfx8.tile_aspect = mtaspect; 3279 tiling_info->gfx8.tile_mode = 3280 DC_ADDR_SURF_MICRO_TILING_DISPLAY; 3281 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) 3282 == DC_ARRAY_1D_TILED_THIN1) { 3283 tiling_info->gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1; 3284 } 3285 3286 tiling_info->gfx8.pipe_config = 3287 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); 3288 3289 if (adev->asic_type == CHIP_VEGA10 || 3290 adev->asic_type == CHIP_VEGA12 || 3291 adev->asic_type == CHIP_VEGA20 || 3292 adev->asic_type == CHIP_NAVI10 || 3293 adev->asic_type == CHIP_NAVI14 || 3294 adev->asic_type == CHIP_NAVI12 || 3295 adev->asic_type == CHIP_RENOIR || 3296 adev->asic_type == CHIP_RAVEN) { 3297 /* Fill GFX9 params */ 3298 tiling_info->gfx9.num_pipes = 3299 adev->gfx.config.gb_addr_config_fields.num_pipes; 3300 tiling_info->gfx9.num_banks = 3301 adev->gfx.config.gb_addr_config_fields.num_banks; 3302 tiling_info->gfx9.pipe_interleave = 3303 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size; 3304 tiling_info->gfx9.num_shader_engines = 3305 adev->gfx.config.gb_addr_config_fields.num_se; 3306 tiling_info->gfx9.max_compressed_frags = 3307 adev->gfx.config.gb_addr_config_fields.max_compress_frags; 3308 tiling_info->gfx9.num_rb_per_se = 3309 adev->gfx.config.gb_addr_config_fields.num_rb_per_se; 3310 tiling_info->gfx9.swizzle = 3311 AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE); 3312 tiling_info->gfx9.shaderEnable = 1; 3313 3314 ret = fill_plane_dcc_attributes(adev, afb, format, rotation, 3315 plane_size, tiling_info, 3316 tiling_flags, dcc, address); 3317 if (ret) 3318 return ret; 3319 } 3320 3321 return 0; 3322 } 3323 3324 static void 3325 fill_blending_from_plane_state(const struct drm_plane_state *plane_state, 3326 bool *per_pixel_alpha, bool *global_alpha, 3327 int *global_alpha_value) 3328 { 3329 *per_pixel_alpha = false; 3330 *global_alpha = false; 3331 *global_alpha_value = 0xff; 3332 3333 if (plane_state->plane->type != DRM_PLANE_TYPE_OVERLAY) 3334 return; 3335 3336 if (plane_state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) { 3337 static const uint32_t alpha_formats[] = { 3338 DRM_FORMAT_ARGB8888, 3339 DRM_FORMAT_RGBA8888, 3340 DRM_FORMAT_ABGR8888, 3341 }; 3342 uint32_t format = plane_state->fb->format->format; 3343 unsigned int i; 3344 3345 for (i = 0; i < ARRAY_SIZE(alpha_formats); ++i) { 3346 if (format == alpha_formats[i]) { 3347 *per_pixel_alpha = true; 3348 break; 3349 } 3350 } 3351 } 3352 3353 if (plane_state->alpha < 0xffff) { 3354 *global_alpha = true; 3355 *global_alpha_value = plane_state->alpha >> 8; 3356 } 3357 } 3358 3359 static int 3360 fill_plane_color_attributes(const struct drm_plane_state *plane_state, 3361 const enum surface_pixel_format format, 3362 enum dc_color_space *color_space) 3363 { 3364 bool full_range; 3365 3366 *color_space = COLOR_SPACE_SRGB; 3367 3368 /* DRM color properties only affect non-RGB formats. */ 3369 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 3370 return 0; 3371 3372 full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE); 3373 3374 switch (plane_state->color_encoding) { 3375 case DRM_COLOR_YCBCR_BT601: 3376 if (full_range) 3377 *color_space = COLOR_SPACE_YCBCR601; 3378 else 3379 *color_space = COLOR_SPACE_YCBCR601_LIMITED; 3380 break; 3381 3382 case DRM_COLOR_YCBCR_BT709: 3383 if (full_range) 3384 *color_space = COLOR_SPACE_YCBCR709; 3385 else 3386 *color_space = COLOR_SPACE_YCBCR709_LIMITED; 3387 break; 3388 3389 case DRM_COLOR_YCBCR_BT2020: 3390 if (full_range) 3391 *color_space = COLOR_SPACE_2020_YCBCR; 3392 else 3393 return -EINVAL; 3394 break; 3395 3396 default: 3397 return -EINVAL; 3398 } 3399 3400 return 0; 3401 } 3402 3403 static int 3404 fill_dc_plane_info_and_addr(struct amdgpu_device *adev, 3405 const struct drm_plane_state *plane_state, 3406 const uint64_t tiling_flags, 3407 struct dc_plane_info *plane_info, 3408 struct dc_plane_address *address) 3409 { 3410 const struct drm_framebuffer *fb = plane_state->fb; 3411 const struct amdgpu_framebuffer *afb = 3412 to_amdgpu_framebuffer(plane_state->fb); 3413 struct drm_format_name_buf format_name; 3414 int ret; 3415 3416 memset(plane_info, 0, sizeof(*plane_info)); 3417 3418 switch (fb->format->format) { 3419 case DRM_FORMAT_C8: 3420 plane_info->format = 3421 SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS; 3422 break; 3423 case DRM_FORMAT_RGB565: 3424 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565; 3425 break; 3426 case DRM_FORMAT_XRGB8888: 3427 case DRM_FORMAT_ARGB8888: 3428 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888; 3429 break; 3430 case DRM_FORMAT_XRGB2101010: 3431 case DRM_FORMAT_ARGB2101010: 3432 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010; 3433 break; 3434 case DRM_FORMAT_XBGR2101010: 3435 case DRM_FORMAT_ABGR2101010: 3436 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010; 3437 break; 3438 case DRM_FORMAT_XBGR8888: 3439 case DRM_FORMAT_ABGR8888: 3440 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888; 3441 break; 3442 case DRM_FORMAT_NV21: 3443 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr; 3444 break; 3445 case DRM_FORMAT_NV12: 3446 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb; 3447 break; 3448 default: 3449 DRM_ERROR( 3450 "Unsupported screen format %s\n", 3451 drm_get_format_name(fb->format->format, &format_name)); 3452 return -EINVAL; 3453 } 3454 3455 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) { 3456 case DRM_MODE_ROTATE_0: 3457 plane_info->rotation = ROTATION_ANGLE_0; 3458 break; 3459 case DRM_MODE_ROTATE_90: 3460 plane_info->rotation = ROTATION_ANGLE_90; 3461 break; 3462 case DRM_MODE_ROTATE_180: 3463 plane_info->rotation = ROTATION_ANGLE_180; 3464 break; 3465 case DRM_MODE_ROTATE_270: 3466 plane_info->rotation = ROTATION_ANGLE_270; 3467 break; 3468 default: 3469 plane_info->rotation = ROTATION_ANGLE_0; 3470 break; 3471 } 3472 3473 plane_info->visible = true; 3474 plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE; 3475 3476 plane_info->layer_index = 0; 3477 3478 ret = fill_plane_color_attributes(plane_state, plane_info->format, 3479 &plane_info->color_space); 3480 if (ret) 3481 return ret; 3482 3483 ret = fill_plane_buffer_attributes(adev, afb, plane_info->format, 3484 plane_info->rotation, tiling_flags, 3485 &plane_info->tiling_info, 3486 &plane_info->plane_size, 3487 &plane_info->dcc, address); 3488 if (ret) 3489 return ret; 3490 3491 fill_blending_from_plane_state( 3492 plane_state, &plane_info->per_pixel_alpha, 3493 &plane_info->global_alpha, &plane_info->global_alpha_value); 3494 3495 return 0; 3496 } 3497 3498 static int fill_dc_plane_attributes(struct amdgpu_device *adev, 3499 struct dc_plane_state *dc_plane_state, 3500 struct drm_plane_state *plane_state, 3501 struct drm_crtc_state *crtc_state) 3502 { 3503 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); 3504 const struct amdgpu_framebuffer *amdgpu_fb = 3505 to_amdgpu_framebuffer(plane_state->fb); 3506 struct dc_scaling_info scaling_info; 3507 struct dc_plane_info plane_info; 3508 uint64_t tiling_flags; 3509 int ret; 3510 3511 ret = fill_dc_scaling_info(plane_state, &scaling_info); 3512 if (ret) 3513 return ret; 3514 3515 dc_plane_state->src_rect = scaling_info.src_rect; 3516 dc_plane_state->dst_rect = scaling_info.dst_rect; 3517 dc_plane_state->clip_rect = scaling_info.clip_rect; 3518 dc_plane_state->scaling_quality = scaling_info.scaling_quality; 3519 3520 ret = get_fb_info(amdgpu_fb, &tiling_flags); 3521 if (ret) 3522 return ret; 3523 3524 ret = fill_dc_plane_info_and_addr(adev, plane_state, tiling_flags, 3525 &plane_info, 3526 &dc_plane_state->address); 3527 if (ret) 3528 return ret; 3529 3530 dc_plane_state->format = plane_info.format; 3531 dc_plane_state->color_space = plane_info.color_space; 3532 dc_plane_state->format = plane_info.format; 3533 dc_plane_state->plane_size = plane_info.plane_size; 3534 dc_plane_state->rotation = plane_info.rotation; 3535 dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror; 3536 dc_plane_state->stereo_format = plane_info.stereo_format; 3537 dc_plane_state->tiling_info = plane_info.tiling_info; 3538 dc_plane_state->visible = plane_info.visible; 3539 dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha; 3540 dc_plane_state->global_alpha = plane_info.global_alpha; 3541 dc_plane_state->global_alpha_value = plane_info.global_alpha_value; 3542 dc_plane_state->dcc = plane_info.dcc; 3543 dc_plane_state->layer_index = plane_info.layer_index; // Always returns 0 3544 3545 /* 3546 * Always set input transfer function, since plane state is refreshed 3547 * every time. 3548 */ 3549 ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state); 3550 if (ret) 3551 return ret; 3552 3553 return 0; 3554 } 3555 3556 static void update_stream_scaling_settings(const struct drm_display_mode *mode, 3557 const struct dm_connector_state *dm_state, 3558 struct dc_stream_state *stream) 3559 { 3560 enum amdgpu_rmx_type rmx_type; 3561 3562 struct rect src = { 0 }; /* viewport in composition space*/ 3563 struct rect dst = { 0 }; /* stream addressable area */ 3564 3565 /* no mode. nothing to be done */ 3566 if (!mode) 3567 return; 3568 3569 /* Full screen scaling by default */ 3570 src.width = mode->hdisplay; 3571 src.height = mode->vdisplay; 3572 dst.width = stream->timing.h_addressable; 3573 dst.height = stream->timing.v_addressable; 3574 3575 if (dm_state) { 3576 rmx_type = dm_state->scaling; 3577 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) { 3578 if (src.width * dst.height < 3579 src.height * dst.width) { 3580 /* height needs less upscaling/more downscaling */ 3581 dst.width = src.width * 3582 dst.height / src.height; 3583 } else { 3584 /* width needs less upscaling/more downscaling */ 3585 dst.height = src.height * 3586 dst.width / src.width; 3587 } 3588 } else if (rmx_type == RMX_CENTER) { 3589 dst = src; 3590 } 3591 3592 dst.x = (stream->timing.h_addressable - dst.width) / 2; 3593 dst.y = (stream->timing.v_addressable - dst.height) / 2; 3594 3595 if (dm_state->underscan_enable) { 3596 dst.x += dm_state->underscan_hborder / 2; 3597 dst.y += dm_state->underscan_vborder / 2; 3598 dst.width -= dm_state->underscan_hborder; 3599 dst.height -= dm_state->underscan_vborder; 3600 } 3601 } 3602 3603 stream->src = src; 3604 stream->dst = dst; 3605 3606 DRM_DEBUG_DRIVER("Destination Rectangle x:%d y:%d width:%d height:%d\n", 3607 dst.x, dst.y, dst.width, dst.height); 3608 3609 } 3610 3611 static enum dc_color_depth 3612 convert_color_depth_from_display_info(const struct drm_connector *connector, 3613 const struct drm_connector_state *state, 3614 bool is_y420) 3615 { 3616 uint8_t bpc; 3617 3618 if (is_y420) { 3619 bpc = 8; 3620 3621 /* Cap display bpc based on HDMI 2.0 HF-VSDB */ 3622 if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48) 3623 bpc = 16; 3624 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36) 3625 bpc = 12; 3626 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30) 3627 bpc = 10; 3628 } else { 3629 bpc = (uint8_t)connector->display_info.bpc; 3630 /* Assume 8 bpc by default if no bpc is specified. */ 3631 bpc = bpc ? bpc : 8; 3632 } 3633 3634 if (!state) 3635 state = connector->state; 3636 3637 if (state) { 3638 /* 3639 * Cap display bpc based on the user requested value. 3640 * 3641 * The value for state->max_bpc may not correctly updated 3642 * depending on when the connector gets added to the state 3643 * or if this was called outside of atomic check, so it 3644 * can't be used directly. 3645 */ 3646 bpc = min(bpc, state->max_requested_bpc); 3647 3648 /* Round down to the nearest even number. */ 3649 bpc = bpc - (bpc & 1); 3650 } 3651 3652 switch (bpc) { 3653 case 0: 3654 /* 3655 * Temporary Work around, DRM doesn't parse color depth for 3656 * EDID revision before 1.4 3657 * TODO: Fix edid parsing 3658 */ 3659 return COLOR_DEPTH_888; 3660 case 6: 3661 return COLOR_DEPTH_666; 3662 case 8: 3663 return COLOR_DEPTH_888; 3664 case 10: 3665 return COLOR_DEPTH_101010; 3666 case 12: 3667 return COLOR_DEPTH_121212; 3668 case 14: 3669 return COLOR_DEPTH_141414; 3670 case 16: 3671 return COLOR_DEPTH_161616; 3672 default: 3673 return COLOR_DEPTH_UNDEFINED; 3674 } 3675 } 3676 3677 static enum dc_aspect_ratio 3678 get_aspect_ratio(const struct drm_display_mode *mode_in) 3679 { 3680 /* 1-1 mapping, since both enums follow the HDMI spec. */ 3681 return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio; 3682 } 3683 3684 static enum dc_color_space 3685 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing) 3686 { 3687 enum dc_color_space color_space = COLOR_SPACE_SRGB; 3688 3689 switch (dc_crtc_timing->pixel_encoding) { 3690 case PIXEL_ENCODING_YCBCR422: 3691 case PIXEL_ENCODING_YCBCR444: 3692 case PIXEL_ENCODING_YCBCR420: 3693 { 3694 /* 3695 * 27030khz is the separation point between HDTV and SDTV 3696 * according to HDMI spec, we use YCbCr709 and YCbCr601 3697 * respectively 3698 */ 3699 if (dc_crtc_timing->pix_clk_100hz > 270300) { 3700 if (dc_crtc_timing->flags.Y_ONLY) 3701 color_space = 3702 COLOR_SPACE_YCBCR709_LIMITED; 3703 else 3704 color_space = COLOR_SPACE_YCBCR709; 3705 } else { 3706 if (dc_crtc_timing->flags.Y_ONLY) 3707 color_space = 3708 COLOR_SPACE_YCBCR601_LIMITED; 3709 else 3710 color_space = COLOR_SPACE_YCBCR601; 3711 } 3712 3713 } 3714 break; 3715 case PIXEL_ENCODING_RGB: 3716 color_space = COLOR_SPACE_SRGB; 3717 break; 3718 3719 default: 3720 WARN_ON(1); 3721 break; 3722 } 3723 3724 return color_space; 3725 } 3726 3727 static bool adjust_colour_depth_from_display_info( 3728 struct dc_crtc_timing *timing_out, 3729 const struct drm_display_info *info) 3730 { 3731 enum dc_color_depth depth = timing_out->display_color_depth; 3732 int normalized_clk; 3733 do { 3734 normalized_clk = timing_out->pix_clk_100hz / 10; 3735 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */ 3736 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420) 3737 normalized_clk /= 2; 3738 /* Adjusting pix clock following on HDMI spec based on colour depth */ 3739 switch (depth) { 3740 case COLOR_DEPTH_888: 3741 break; 3742 case COLOR_DEPTH_101010: 3743 normalized_clk = (normalized_clk * 30) / 24; 3744 break; 3745 case COLOR_DEPTH_121212: 3746 normalized_clk = (normalized_clk * 36) / 24; 3747 break; 3748 case COLOR_DEPTH_161616: 3749 normalized_clk = (normalized_clk * 48) / 24; 3750 break; 3751 default: 3752 /* The above depths are the only ones valid for HDMI. */ 3753 return false; 3754 } 3755 if (normalized_clk <= info->max_tmds_clock) { 3756 timing_out->display_color_depth = depth; 3757 return true; 3758 } 3759 } while (--depth > COLOR_DEPTH_666); 3760 return false; 3761 } 3762 3763 static void fill_stream_properties_from_drm_display_mode( 3764 struct dc_stream_state *stream, 3765 const struct drm_display_mode *mode_in, 3766 const struct drm_connector *connector, 3767 const struct drm_connector_state *connector_state, 3768 const struct dc_stream_state *old_stream) 3769 { 3770 struct dc_crtc_timing *timing_out = &stream->timing; 3771 const struct drm_display_info *info = &connector->display_info; 3772 const struct amdgpu_dm_connector *aconnector = const_container_of(connector, struct amdgpu_dm_connector, base); 3773 struct hdmi_vendor_infoframe hv_frame; 3774 struct hdmi_avi_infoframe avi_frame; 3775 3776 memset(&hv_frame, 0, sizeof(hv_frame)); 3777 memset(&avi_frame, 0, sizeof(avi_frame)); 3778 3779 timing_out->h_border_left = 0; 3780 timing_out->h_border_right = 0; 3781 timing_out->v_border_top = 0; 3782 timing_out->v_border_bottom = 0; 3783 /* TODO: un-hardcode */ 3784 if (drm_mode_is_420_only(info, mode_in) 3785 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) 3786 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; 3787 else if (drm_mode_is_420_also(info, mode_in) 3788 && aconnector->force_yuv420_output) 3789 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; 3790 else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444) 3791 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) 3792 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444; 3793 else 3794 timing_out->pixel_encoding = PIXEL_ENCODING_RGB; 3795 3796 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE; 3797 timing_out->display_color_depth = convert_color_depth_from_display_info( 3798 connector, connector_state, 3799 (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)); 3800 timing_out->scan_type = SCANNING_TYPE_NODATA; 3801 timing_out->hdmi_vic = 0; 3802 3803 if(old_stream) { 3804 timing_out->vic = old_stream->timing.vic; 3805 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY; 3806 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY; 3807 } else { 3808 timing_out->vic = drm_match_cea_mode(mode_in); 3809 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC) 3810 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1; 3811 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC) 3812 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1; 3813 } 3814 3815 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) { 3816 drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, __UNCONST(connector), mode_in); 3817 timing_out->vic = avi_frame.video_code; 3818 drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, __UNCONST(connector), mode_in); 3819 timing_out->hdmi_vic = hv_frame.vic; 3820 } 3821 3822 timing_out->h_addressable = mode_in->crtc_hdisplay; 3823 timing_out->h_total = mode_in->crtc_htotal; 3824 timing_out->h_sync_width = 3825 mode_in->crtc_hsync_end - mode_in->crtc_hsync_start; 3826 timing_out->h_front_porch = 3827 mode_in->crtc_hsync_start - mode_in->crtc_hdisplay; 3828 timing_out->v_total = mode_in->crtc_vtotal; 3829 timing_out->v_addressable = mode_in->crtc_vdisplay; 3830 timing_out->v_front_porch = 3831 mode_in->crtc_vsync_start - mode_in->crtc_vdisplay; 3832 timing_out->v_sync_width = 3833 mode_in->crtc_vsync_end - mode_in->crtc_vsync_start; 3834 timing_out->pix_clk_100hz = mode_in->crtc_clock * 10; 3835 timing_out->aspect_ratio = get_aspect_ratio(mode_in); 3836 3837 stream->output_color_space = get_output_color_space(timing_out); 3838 3839 stream->out_transfer_func->type = TF_TYPE_PREDEFINED; 3840 stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB; 3841 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) { 3842 if (!adjust_colour_depth_from_display_info(timing_out, info) && 3843 drm_mode_is_420_also(info, mode_in) && 3844 timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) { 3845 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; 3846 adjust_colour_depth_from_display_info(timing_out, info); 3847 } 3848 } 3849 } 3850 3851 static void fill_audio_info(struct audio_info *audio_info, 3852 const struct drm_connector *drm_connector, 3853 const struct dc_sink *dc_sink) 3854 { 3855 int i = 0; 3856 int cea_revision = 0; 3857 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps; 3858 3859 audio_info->manufacture_id = edid_caps->manufacturer_id; 3860 audio_info->product_id = edid_caps->product_id; 3861 3862 cea_revision = drm_connector->display_info.cea_rev; 3863 3864 strscpy(audio_info->display_name, 3865 edid_caps->display_name, 3866 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS); 3867 3868 if (cea_revision >= 3) { 3869 audio_info->mode_count = edid_caps->audio_mode_count; 3870 3871 for (i = 0; i < audio_info->mode_count; ++i) { 3872 audio_info->modes[i].format_code = 3873 (enum audio_format_code) 3874 (edid_caps->audio_modes[i].format_code); 3875 audio_info->modes[i].channel_count = 3876 edid_caps->audio_modes[i].channel_count; 3877 audio_info->modes[i].sample_rates.all = 3878 edid_caps->audio_modes[i].sample_rate; 3879 audio_info->modes[i].sample_size = 3880 edid_caps->audio_modes[i].sample_size; 3881 } 3882 } 3883 3884 audio_info->flags.all = edid_caps->speaker_flags; 3885 3886 /* TODO: We only check for the progressive mode, check for interlace mode too */ 3887 if (drm_connector->latency_present[0]) { 3888 audio_info->video_latency = drm_connector->video_latency[0]; 3889 audio_info->audio_latency = drm_connector->audio_latency[0]; 3890 } 3891 3892 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */ 3893 3894 } 3895 3896 static void 3897 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode, 3898 struct drm_display_mode *dst_mode) 3899 { 3900 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay; 3901 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay; 3902 dst_mode->crtc_clock = src_mode->crtc_clock; 3903 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start; 3904 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end; 3905 dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start; 3906 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end; 3907 dst_mode->crtc_htotal = src_mode->crtc_htotal; 3908 dst_mode->crtc_hskew = src_mode->crtc_hskew; 3909 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start; 3910 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end; 3911 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start; 3912 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end; 3913 dst_mode->crtc_vtotal = src_mode->crtc_vtotal; 3914 } 3915 3916 static void 3917 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode, 3918 const struct drm_display_mode *native_mode, 3919 bool scale_enabled) 3920 { 3921 if (scale_enabled) { 3922 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode); 3923 } else if (native_mode->clock == drm_mode->clock && 3924 native_mode->htotal == drm_mode->htotal && 3925 native_mode->vtotal == drm_mode->vtotal) { 3926 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode); 3927 } else { 3928 /* no scaling nor amdgpu inserted, no need to patch */ 3929 } 3930 } 3931 3932 static struct dc_sink * 3933 create_fake_sink(struct amdgpu_dm_connector *aconnector) 3934 { 3935 struct dc_sink_init_data sink_init_data = { 0 }; 3936 struct dc_sink *sink = NULL; 3937 sink_init_data.link = aconnector->dc_link; 3938 sink_init_data.sink_signal = aconnector->dc_link->connector_signal; 3939 3940 sink = dc_sink_create(&sink_init_data); 3941 if (!sink) { 3942 DRM_ERROR("Failed to create sink!\n"); 3943 return NULL; 3944 } 3945 sink->sink_signal = SIGNAL_TYPE_VIRTUAL; 3946 3947 return sink; 3948 } 3949 3950 static void set_multisync_trigger_params( 3951 struct dc_stream_state *stream) 3952 { 3953 if (stream->triggered_crtc_reset.enabled) { 3954 stream->triggered_crtc_reset.event = CRTC_EVENT_VSYNC_RISING; 3955 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_LINE; 3956 } 3957 } 3958 3959 static void set_master_stream(struct dc_stream_state *stream_set[], 3960 int stream_count) 3961 { 3962 int j, highest_rfr = 0, master_stream = 0; 3963 3964 for (j = 0; j < stream_count; j++) { 3965 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) { 3966 int refresh_rate = 0; 3967 3968 refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/ 3969 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total); 3970 if (refresh_rate > highest_rfr) { 3971 highest_rfr = refresh_rate; 3972 master_stream = j; 3973 } 3974 } 3975 } 3976 for (j = 0; j < stream_count; j++) { 3977 if (stream_set[j]) 3978 stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream]; 3979 } 3980 } 3981 3982 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context) 3983 { 3984 int i = 0; 3985 3986 if (context->stream_count < 2) 3987 return; 3988 for (i = 0; i < context->stream_count ; i++) { 3989 if (!context->streams[i]) 3990 continue; 3991 /* 3992 * TODO: add a function to read AMD VSDB bits and set 3993 * crtc_sync_master.multi_sync_enabled flag 3994 * For now it's set to false 3995 */ 3996 set_multisync_trigger_params(context->streams[i]); 3997 } 3998 set_master_stream(context->streams, context->stream_count); 3999 } 4000 4001 static struct dc_stream_state * 4002 create_stream_for_sink(struct amdgpu_dm_connector *aconnector, 4003 const struct drm_display_mode *drm_mode, 4004 const struct dm_connector_state *dm_state, 4005 const struct dc_stream_state *old_stream) 4006 { 4007 struct drm_display_mode *preferred_mode = NULL; 4008 struct drm_connector *drm_connector; 4009 const struct drm_connector_state *con_state = 4010 dm_state ? &dm_state->base : NULL; 4011 struct dc_stream_state *stream = NULL; 4012 struct drm_display_mode mode = *drm_mode; 4013 bool native_mode_found = false; 4014 bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false; 4015 int mode_refresh; 4016 int preferred_refresh = 0; 4017 #if defined(CONFIG_DRM_AMD_DC_DCN) 4018 struct dsc_dec_dpcd_caps dsc_caps; 4019 #endif 4020 uint32_t link_bandwidth_kbps; 4021 4022 struct dc_sink *sink = NULL; 4023 if (aconnector == NULL) { 4024 DRM_ERROR("aconnector is NULL!\n"); 4025 return stream; 4026 } 4027 4028 drm_connector = &aconnector->base; 4029 4030 if (!aconnector->dc_sink) { 4031 sink = create_fake_sink(aconnector); 4032 if (!sink) 4033 return stream; 4034 } else { 4035 sink = aconnector->dc_sink; 4036 dc_sink_retain(sink); 4037 } 4038 4039 stream = dc_create_stream_for_sink(sink); 4040 4041 if (stream == NULL) { 4042 DRM_ERROR("Failed to create stream for sink!\n"); 4043 goto finish; 4044 } 4045 4046 stream->dm_stream_context = aconnector; 4047 4048 stream->timing.flags.LTE_340MCSC_SCRAMBLE = 4049 drm_connector->display_info.hdmi.scdc.scrambling.low_rates; 4050 4051 list_for_each_entry(preferred_mode, &aconnector->base.modes, head) { 4052 /* Search for preferred mode */ 4053 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) { 4054 native_mode_found = true; 4055 break; 4056 } 4057 } 4058 if (!native_mode_found) 4059 preferred_mode = list_first_entry_or_null( 4060 &aconnector->base.modes, 4061 struct drm_display_mode, 4062 head); 4063 4064 mode_refresh = drm_mode_vrefresh(&mode); 4065 4066 if (preferred_mode == NULL) { 4067 /* 4068 * This may not be an error, the use case is when we have no 4069 * usermode calls to reset and set mode upon hotplug. In this 4070 * case, we call set mode ourselves to restore the previous mode 4071 * and the modelist may not be filled in in time. 4072 */ 4073 DRM_DEBUG_DRIVER("No preferred mode found\n"); 4074 } else { 4075 decide_crtc_timing_for_drm_display_mode( 4076 &mode, preferred_mode, 4077 dm_state ? (dm_state->scaling != RMX_OFF) : false); 4078 preferred_refresh = drm_mode_vrefresh(preferred_mode); 4079 } 4080 4081 if (!dm_state) 4082 drm_mode_set_crtcinfo(&mode, 0); 4083 4084 /* 4085 * If scaling is enabled and refresh rate didn't change 4086 * we copy the vic and polarities of the old timings 4087 */ 4088 if (!scale || mode_refresh != preferred_refresh) 4089 fill_stream_properties_from_drm_display_mode(stream, 4090 &mode, &aconnector->base, con_state, NULL); 4091 else 4092 fill_stream_properties_from_drm_display_mode(stream, 4093 &mode, &aconnector->base, con_state, old_stream); 4094 4095 stream->timing.flags.DSC = 0; 4096 4097 if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) { 4098 #if defined(CONFIG_DRM_AMD_DC_DCN) 4099 dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc, 4100 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw, 4101 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_ext_caps.raw, 4102 &dsc_caps); 4103 #endif 4104 link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link, 4105 dc_link_get_link_cap(aconnector->dc_link)); 4106 4107 #if defined(CONFIG_DRM_AMD_DC_DCN) 4108 if (dsc_caps.is_dsc_supported) 4109 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0], 4110 &dsc_caps, 4111 aconnector->dc_link->ctx->dc->debug.dsc_min_slice_height_override, 4112 link_bandwidth_kbps, 4113 &stream->timing, 4114 &stream->timing.dsc_cfg)) 4115 stream->timing.flags.DSC = 1; 4116 #endif 4117 } 4118 4119 update_stream_scaling_settings(&mode, dm_state, stream); 4120 4121 fill_audio_info( 4122 &stream->audio_info, 4123 drm_connector, 4124 sink); 4125 4126 update_stream_signal(stream, sink); 4127 4128 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) 4129 mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket, false, false); 4130 if (stream->link->psr_feature_enabled) { 4131 struct dc *core_dc = stream->link->ctx->dc; 4132 4133 if (dc_is_dmcu_initialized(core_dc)) { 4134 struct dmcu *dmcu = core_dc->res_pool->dmcu; 4135 4136 stream->psr_version = dmcu->dmcu_version.psr_version; 4137 mod_build_vsc_infopacket(stream, 4138 &stream->vsc_infopacket, 4139 &stream->use_vsc_sdp_for_colorimetry); 4140 } 4141 } 4142 finish: 4143 dc_sink_release(sink); 4144 4145 return stream; 4146 } 4147 4148 static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc) 4149 { 4150 drm_crtc_cleanup(crtc); 4151 kfree(crtc); 4152 } 4153 4154 static void dm_crtc_destroy_state(struct drm_crtc *crtc, 4155 struct drm_crtc_state *state) 4156 { 4157 struct dm_crtc_state *cur = to_dm_crtc_state(state); 4158 4159 /* TODO Destroy dc_stream objects are stream object is flattened */ 4160 if (cur->stream) 4161 dc_stream_release(cur->stream); 4162 4163 4164 __drm_atomic_helper_crtc_destroy_state(state); 4165 4166 4167 kfree(state); 4168 } 4169 4170 static void dm_crtc_reset_state(struct drm_crtc *crtc) 4171 { 4172 struct dm_crtc_state *state; 4173 4174 if (crtc->state) 4175 dm_crtc_destroy_state(crtc, crtc->state); 4176 4177 state = kzalloc(sizeof(*state), GFP_KERNEL); 4178 if (WARN_ON(!state)) 4179 return; 4180 4181 crtc->state = &state->base; 4182 crtc->state->crtc = crtc; 4183 4184 } 4185 4186 static struct drm_crtc_state * 4187 dm_crtc_duplicate_state(struct drm_crtc *crtc) 4188 { 4189 struct dm_crtc_state *state, *cur; 4190 4191 cur = to_dm_crtc_state(crtc->state); 4192 4193 if (WARN_ON(!crtc->state)) 4194 return NULL; 4195 4196 state = kzalloc(sizeof(*state), GFP_KERNEL); 4197 if (!state) 4198 return NULL; 4199 4200 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base); 4201 4202 if (cur->stream) { 4203 state->stream = cur->stream; 4204 dc_stream_retain(state->stream); 4205 } 4206 4207 state->active_planes = cur->active_planes; 4208 state->interrupts_enabled = cur->interrupts_enabled; 4209 state->vrr_params = cur->vrr_params; 4210 state->vrr_infopacket = cur->vrr_infopacket; 4211 state->abm_level = cur->abm_level; 4212 state->vrr_supported = cur->vrr_supported; 4213 state->freesync_config = cur->freesync_config; 4214 state->crc_src = cur->crc_src; 4215 state->cm_has_degamma = cur->cm_has_degamma; 4216 state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb; 4217 4218 /* TODO Duplicate dc_stream after objects are stream object is flattened */ 4219 4220 return &state->base; 4221 } 4222 4223 static inline int dm_set_vupdate_irq(struct drm_crtc *crtc, bool enable) 4224 { 4225 enum dc_irq_source irq_source; 4226 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 4227 struct amdgpu_device *adev = crtc->dev->dev_private; 4228 int rc; 4229 4230 /* Do not set vupdate for DCN hardware */ 4231 if (adev->family > AMDGPU_FAMILY_AI) 4232 return 0; 4233 4234 irq_source = IRQ_TYPE_VUPDATE + acrtc->otg_inst; 4235 4236 rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY; 4237 4238 DRM_DEBUG_DRIVER("crtc %d - vupdate irq %sabling: r=%d\n", 4239 acrtc->crtc_id, enable ? "en" : "dis", rc); 4240 return rc; 4241 } 4242 4243 static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable) 4244 { 4245 enum dc_irq_source irq_source; 4246 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 4247 struct amdgpu_device *adev = crtc->dev->dev_private; 4248 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state); 4249 int rc = 0; 4250 4251 if (enable) { 4252 /* vblank irq on -> Only need vupdate irq in vrr mode */ 4253 if (amdgpu_dm_vrr_active(acrtc_state)) 4254 rc = dm_set_vupdate_irq(crtc, true); 4255 } else { 4256 /* vblank irq off -> vupdate irq off */ 4257 rc = dm_set_vupdate_irq(crtc, false); 4258 } 4259 4260 if (rc) 4261 return rc; 4262 4263 irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst; 4264 return dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY; 4265 } 4266 4267 static int dm_enable_vblank(struct drm_crtc *crtc) 4268 { 4269 return dm_set_vblank(crtc, true); 4270 } 4271 4272 static void dm_disable_vblank(struct drm_crtc *crtc) 4273 { 4274 dm_set_vblank(crtc, false); 4275 } 4276 4277 /* Implemented only the options currently availible for the driver */ 4278 static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = { 4279 .reset = dm_crtc_reset_state, 4280 .destroy = amdgpu_dm_crtc_destroy, 4281 .gamma_set = drm_atomic_helper_legacy_gamma_set, 4282 .set_config = drm_atomic_helper_set_config, 4283 .page_flip = drm_atomic_helper_page_flip, 4284 .atomic_duplicate_state = dm_crtc_duplicate_state, 4285 .atomic_destroy_state = dm_crtc_destroy_state, 4286 .set_crc_source = amdgpu_dm_crtc_set_crc_source, 4287 .verify_crc_source = amdgpu_dm_crtc_verify_crc_source, 4288 .get_crc_sources = amdgpu_dm_crtc_get_crc_sources, 4289 .enable_vblank = dm_enable_vblank, 4290 .disable_vblank = dm_disable_vblank, 4291 }; 4292 4293 static enum drm_connector_status 4294 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force) 4295 { 4296 bool connected; 4297 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 4298 4299 /* 4300 * Notes: 4301 * 1. This interface is NOT called in context of HPD irq. 4302 * 2. This interface *is called* in context of user-mode ioctl. Which 4303 * makes it a bad place for *any* MST-related activity. 4304 */ 4305 4306 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED && 4307 !aconnector->fake_enable) 4308 connected = (aconnector->dc_sink != NULL); 4309 else 4310 connected = (aconnector->base.force == DRM_FORCE_ON); 4311 4312 return (connected ? connector_status_connected : 4313 connector_status_disconnected); 4314 } 4315 4316 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, 4317 struct drm_connector_state *connector_state, 4318 struct drm_property *property, 4319 uint64_t val) 4320 { 4321 struct drm_device *dev = connector->dev; 4322 struct amdgpu_device *adev = dev->dev_private; 4323 struct dm_connector_state *dm_old_state = 4324 to_dm_connector_state(connector->state); 4325 struct dm_connector_state *dm_new_state = 4326 to_dm_connector_state(connector_state); 4327 4328 int ret = -EINVAL; 4329 4330 if (property == dev->mode_config.scaling_mode_property) { 4331 enum amdgpu_rmx_type rmx_type; 4332 4333 switch (val) { 4334 case DRM_MODE_SCALE_CENTER: 4335 rmx_type = RMX_CENTER; 4336 break; 4337 case DRM_MODE_SCALE_ASPECT: 4338 rmx_type = RMX_ASPECT; 4339 break; 4340 case DRM_MODE_SCALE_FULLSCREEN: 4341 rmx_type = RMX_FULL; 4342 break; 4343 case DRM_MODE_SCALE_NONE: 4344 default: 4345 rmx_type = RMX_OFF; 4346 break; 4347 } 4348 4349 if (dm_old_state->scaling == rmx_type) 4350 return 0; 4351 4352 dm_new_state->scaling = rmx_type; 4353 ret = 0; 4354 } else if (property == adev->mode_info.underscan_hborder_property) { 4355 dm_new_state->underscan_hborder = val; 4356 ret = 0; 4357 } else if (property == adev->mode_info.underscan_vborder_property) { 4358 dm_new_state->underscan_vborder = val; 4359 ret = 0; 4360 } else if (property == adev->mode_info.underscan_property) { 4361 dm_new_state->underscan_enable = val; 4362 ret = 0; 4363 } else if (property == adev->mode_info.abm_level_property) { 4364 dm_new_state->abm_level = val; 4365 ret = 0; 4366 } 4367 4368 return ret; 4369 } 4370 4371 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, 4372 const struct drm_connector_state *state, 4373 struct drm_property *property, 4374 uint64_t *val) 4375 { 4376 struct drm_device *dev = connector->dev; 4377 struct amdgpu_device *adev = dev->dev_private; 4378 const struct dm_connector_state *dm_state = 4379 const_container_of(state, struct dm_connector_state, base); 4380 int ret = -EINVAL; 4381 4382 if (property == dev->mode_config.scaling_mode_property) { 4383 switch (dm_state->scaling) { 4384 case RMX_CENTER: 4385 *val = DRM_MODE_SCALE_CENTER; 4386 break; 4387 case RMX_ASPECT: 4388 *val = DRM_MODE_SCALE_ASPECT; 4389 break; 4390 case RMX_FULL: 4391 *val = DRM_MODE_SCALE_FULLSCREEN; 4392 break; 4393 case RMX_OFF: 4394 default: 4395 *val = DRM_MODE_SCALE_NONE; 4396 break; 4397 } 4398 ret = 0; 4399 } else if (property == adev->mode_info.underscan_hborder_property) { 4400 *val = dm_state->underscan_hborder; 4401 ret = 0; 4402 } else if (property == adev->mode_info.underscan_vborder_property) { 4403 *val = dm_state->underscan_vborder; 4404 ret = 0; 4405 } else if (property == adev->mode_info.underscan_property) { 4406 *val = dm_state->underscan_enable; 4407 ret = 0; 4408 } else if (property == adev->mode_info.abm_level_property) { 4409 *val = dm_state->abm_level; 4410 ret = 0; 4411 } 4412 4413 return ret; 4414 } 4415 4416 static void amdgpu_dm_connector_unregister(struct drm_connector *connector) 4417 { 4418 struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector); 4419 4420 drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux); 4421 } 4422 4423 static void amdgpu_dm_connector_destroy(struct drm_connector *connector) 4424 { 4425 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 4426 const struct dc_link *link = aconnector->dc_link; 4427 struct amdgpu_device *adev = connector->dev->dev_private; 4428 struct amdgpu_display_manager *dm = &adev->dm; 4429 4430 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\ 4431 IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 4432 4433 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) && 4434 link->type != dc_connection_none && 4435 dm->backlight_dev) { 4436 backlight_device_unregister(dm->backlight_dev); 4437 dm->backlight_dev = NULL; 4438 } 4439 #else 4440 __USE(dm); 4441 __USE(link); 4442 #endif 4443 4444 if (aconnector->dc_em_sink) 4445 dc_sink_release(aconnector->dc_em_sink); 4446 aconnector->dc_em_sink = NULL; 4447 if (aconnector->dc_sink) 4448 dc_sink_release(aconnector->dc_sink); 4449 aconnector->dc_sink = NULL; 4450 4451 drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux); 4452 drm_connector_unregister(connector); 4453 drm_connector_cleanup(connector); 4454 if (aconnector->i2c) { 4455 i2c_del_adapter(&aconnector->i2c->base); 4456 kfree(aconnector->i2c); 4457 } 4458 mutex_destroy(&aconnector->hpd_lock); 4459 4460 kfree(connector); 4461 } 4462 4463 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector) 4464 { 4465 struct dm_connector_state *state = 4466 to_dm_connector_state(connector->state); 4467 4468 if (connector->state) 4469 __drm_atomic_helper_connector_destroy_state(connector->state); 4470 4471 kfree(state); 4472 4473 state = kzalloc(sizeof(*state), GFP_KERNEL); 4474 4475 if (state) { 4476 state->scaling = RMX_OFF; 4477 state->underscan_enable = false; 4478 state->underscan_hborder = 0; 4479 state->underscan_vborder = 0; 4480 state->base.max_requested_bpc = 8; 4481 state->vcpi_slots = 0; 4482 state->pbn = 0; 4483 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 4484 state->abm_level = amdgpu_dm_abm_level; 4485 4486 __drm_atomic_helper_connector_reset(connector, &state->base); 4487 } 4488 } 4489 4490 struct drm_connector_state * 4491 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector) 4492 { 4493 struct dm_connector_state *state = 4494 to_dm_connector_state(connector->state); 4495 4496 struct dm_connector_state *new_state = 4497 kmemdup(state, sizeof(*state), GFP_KERNEL); 4498 4499 if (!new_state) 4500 return NULL; 4501 4502 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base); 4503 4504 new_state->freesync_capable = state->freesync_capable; 4505 new_state->abm_level = state->abm_level; 4506 new_state->scaling = state->scaling; 4507 new_state->underscan_enable = state->underscan_enable; 4508 new_state->underscan_hborder = state->underscan_hborder; 4509 new_state->underscan_vborder = state->underscan_vborder; 4510 new_state->vcpi_slots = state->vcpi_slots; 4511 new_state->pbn = state->pbn; 4512 return &new_state->base; 4513 } 4514 4515 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = { 4516 .reset = amdgpu_dm_connector_funcs_reset, 4517 .detect = amdgpu_dm_connector_detect, 4518 .fill_modes = drm_helper_probe_single_connector_modes, 4519 .destroy = amdgpu_dm_connector_destroy, 4520 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state, 4521 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 4522 .atomic_set_property = amdgpu_dm_connector_atomic_set_property, 4523 .atomic_get_property = amdgpu_dm_connector_atomic_get_property, 4524 .early_unregister = amdgpu_dm_connector_unregister 4525 }; 4526 4527 static int get_modes(struct drm_connector *connector) 4528 { 4529 return amdgpu_dm_connector_get_modes(connector); 4530 } 4531 4532 static void create_eml_sink(struct amdgpu_dm_connector *aconnector) 4533 { 4534 struct dc_sink_init_data init_params = { 4535 .link = aconnector->dc_link, 4536 .sink_signal = SIGNAL_TYPE_VIRTUAL 4537 }; 4538 struct edid *edid; 4539 4540 if (!aconnector->base.edid_blob_ptr) { 4541 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n", 4542 aconnector->base.name); 4543 4544 aconnector->base.force = DRM_FORCE_OFF; 4545 aconnector->base.override_edid = false; 4546 return; 4547 } 4548 4549 edid = (struct edid *) aconnector->base.edid_blob_ptr->data; 4550 4551 aconnector->edid = edid; 4552 4553 aconnector->dc_em_sink = dc_link_add_remote_sink( 4554 aconnector->dc_link, 4555 (uint8_t *)edid, 4556 (edid->extensions + 1) * EDID_LENGTH, 4557 &init_params); 4558 4559 if (aconnector->base.force == DRM_FORCE_ON) { 4560 aconnector->dc_sink = aconnector->dc_link->local_sink ? 4561 aconnector->dc_link->local_sink : 4562 aconnector->dc_em_sink; 4563 dc_sink_retain(aconnector->dc_sink); 4564 } 4565 } 4566 4567 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector) 4568 { 4569 struct dc_link *link = (struct dc_link *)aconnector->dc_link; 4570 4571 /* 4572 * In case of headless boot with force on for DP managed connector 4573 * Those settings have to be != 0 to get initial modeset 4574 */ 4575 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) { 4576 link->verified_link_cap.lane_count = LANE_COUNT_FOUR; 4577 link->verified_link_cap.link_rate = LINK_RATE_HIGH2; 4578 } 4579 4580 4581 aconnector->base.override_edid = true; 4582 create_eml_sink(aconnector); 4583 } 4584 4585 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, 4586 struct drm_display_mode *mode) 4587 { 4588 int result = MODE_ERROR; 4589 struct dc_sink *dc_sink; 4590 struct amdgpu_device *adev = connector->dev->dev_private; 4591 /* TODO: Unhardcode stream count */ 4592 struct dc_stream_state *stream; 4593 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 4594 enum dc_status dc_result = DC_OK; 4595 4596 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) || 4597 (mode->flags & DRM_MODE_FLAG_DBLSCAN)) 4598 return result; 4599 4600 /* 4601 * Only run this the first time mode_valid is called to initilialize 4602 * EDID mgmt 4603 */ 4604 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED && 4605 !aconnector->dc_em_sink) 4606 handle_edid_mgmt(aconnector); 4607 4608 dc_sink = to_amdgpu_dm_connector(connector)->dc_sink; 4609 4610 if (dc_sink == NULL) { 4611 DRM_ERROR("dc_sink is NULL!\n"); 4612 goto fail; 4613 } 4614 4615 stream = create_stream_for_sink(aconnector, mode, NULL, NULL); 4616 if (stream == NULL) { 4617 DRM_ERROR("Failed to create stream for sink!\n"); 4618 goto fail; 4619 } 4620 4621 dc_result = dc_validate_stream(adev->dm.dc, stream); 4622 4623 if (dc_result == DC_OK) 4624 result = MODE_OK; 4625 else 4626 DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d\n", 4627 mode->hdisplay, 4628 mode->vdisplay, 4629 mode->clock, 4630 dc_result); 4631 4632 dc_stream_release(stream); 4633 4634 fail: 4635 /* TODO: error handling*/ 4636 return result; 4637 } 4638 4639 static int fill_hdr_info_packet(const struct drm_connector_state *state, 4640 struct dc_info_packet *out) 4641 { 4642 struct hdmi_drm_infoframe frame; 4643 unsigned char buf[30]; /* 26 + 4 */ 4644 ssize_t len; 4645 int ret, i; 4646 4647 memset(out, 0, sizeof(*out)); 4648 4649 if (!state->hdr_output_metadata) 4650 return 0; 4651 4652 ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state); 4653 if (ret) 4654 return ret; 4655 4656 len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf)); 4657 if (len < 0) 4658 return (int)len; 4659 4660 /* Static metadata is a fixed 26 bytes + 4 byte header. */ 4661 if (len != 30) 4662 return -EINVAL; 4663 4664 /* Prepare the infopacket for DC. */ 4665 switch (state->connector->connector_type) { 4666 case DRM_MODE_CONNECTOR_HDMIA: 4667 out->hb0 = 0x87; /* type */ 4668 out->hb1 = 0x01; /* version */ 4669 out->hb2 = 0x1A; /* length */ 4670 out->sb[0] = buf[3]; /* checksum */ 4671 i = 1; 4672 break; 4673 4674 case DRM_MODE_CONNECTOR_DisplayPort: 4675 case DRM_MODE_CONNECTOR_eDP: 4676 out->hb0 = 0x00; /* sdp id, zero */ 4677 out->hb1 = 0x87; /* type */ 4678 out->hb2 = 0x1D; /* payload len - 1 */ 4679 out->hb3 = (0x13 << 2); /* sdp version */ 4680 out->sb[0] = 0x01; /* version */ 4681 out->sb[1] = 0x1A; /* length */ 4682 i = 2; 4683 break; 4684 4685 default: 4686 return -EINVAL; 4687 } 4688 4689 memcpy(&out->sb[i], &buf[4], 26); 4690 out->valid = true; 4691 4692 print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb, 4693 sizeof(out->sb), false); 4694 4695 return 0; 4696 } 4697 4698 static bool 4699 is_hdr_metadata_different(const struct drm_connector_state *old_state, 4700 const struct drm_connector_state *new_state) 4701 { 4702 struct drm_property_blob *old_blob = old_state->hdr_output_metadata; 4703 struct drm_property_blob *new_blob = new_state->hdr_output_metadata; 4704 4705 if (old_blob != new_blob) { 4706 if (old_blob && new_blob && 4707 old_blob->length == new_blob->length) 4708 return memcmp(old_blob->data, new_blob->data, 4709 old_blob->length); 4710 4711 return true; 4712 } 4713 4714 return false; 4715 } 4716 4717 static int 4718 amdgpu_dm_connector_atomic_check(struct drm_connector *conn, 4719 struct drm_atomic_state *state) 4720 { 4721 struct drm_connector_state *new_con_state = 4722 drm_atomic_get_new_connector_state(state, conn); 4723 struct drm_connector_state *old_con_state = 4724 drm_atomic_get_old_connector_state(state, conn); 4725 struct drm_crtc *crtc = new_con_state->crtc; 4726 struct drm_crtc_state *new_crtc_state; 4727 int ret; 4728 4729 if (!crtc) 4730 return 0; 4731 4732 if (is_hdr_metadata_different(old_con_state, new_con_state)) { 4733 struct dc_info_packet hdr_infopacket; 4734 4735 ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket); 4736 if (ret) 4737 return ret; 4738 4739 new_crtc_state = drm_atomic_get_crtc_state(state, crtc); 4740 if (IS_ERR(new_crtc_state)) 4741 return PTR_ERR(new_crtc_state); 4742 4743 /* 4744 * DC considers the stream backends changed if the 4745 * static metadata changes. Forcing the modeset also 4746 * gives a simple way for userspace to switch from 4747 * 8bpc to 10bpc when setting the metadata to enter 4748 * or exit HDR. 4749 * 4750 * Changing the static metadata after it's been 4751 * set is permissible, however. So only force a 4752 * modeset if we're entering or exiting HDR. 4753 */ 4754 new_crtc_state->mode_changed = 4755 !old_con_state->hdr_output_metadata || 4756 !new_con_state->hdr_output_metadata; 4757 } 4758 4759 return 0; 4760 } 4761 4762 static const struct drm_connector_helper_funcs 4763 amdgpu_dm_connector_helper_funcs = { 4764 /* 4765 * If hotplugging a second bigger display in FB Con mode, bigger resolution 4766 * modes will be filtered by drm_mode_validate_size(), and those modes 4767 * are missing after user start lightdm. So we need to renew modes list. 4768 * in get_modes call back, not just return the modes count 4769 */ 4770 .get_modes = get_modes, 4771 .mode_valid = amdgpu_dm_connector_mode_valid, 4772 .atomic_check = amdgpu_dm_connector_atomic_check, 4773 }; 4774 4775 static void dm_crtc_helper_disable(struct drm_crtc *crtc) 4776 { 4777 } 4778 4779 static bool does_crtc_have_active_cursor(struct drm_crtc_state *new_crtc_state) 4780 { 4781 struct drm_device *dev = new_crtc_state->crtc->dev; 4782 struct drm_plane *plane; 4783 4784 drm_for_each_plane_mask(plane, dev, new_crtc_state->plane_mask) { 4785 if (plane->type == DRM_PLANE_TYPE_CURSOR) 4786 return true; 4787 } 4788 4789 return false; 4790 } 4791 4792 static int count_crtc_active_planes(struct drm_crtc_state *new_crtc_state) 4793 { 4794 struct drm_atomic_state *state = new_crtc_state->state; 4795 struct drm_plane *plane; 4796 int num_active = 0; 4797 4798 drm_for_each_plane_mask(plane, state->dev, new_crtc_state->plane_mask) { 4799 struct drm_plane_state *new_plane_state; 4800 4801 /* Cursor planes are "fake". */ 4802 if (plane->type == DRM_PLANE_TYPE_CURSOR) 4803 continue; 4804 4805 new_plane_state = drm_atomic_get_new_plane_state(state, plane); 4806 4807 if (!new_plane_state) { 4808 /* 4809 * The plane is enable on the CRTC and hasn't changed 4810 * state. This means that it previously passed 4811 * validation and is therefore enabled. 4812 */ 4813 num_active += 1; 4814 continue; 4815 } 4816 4817 /* We need a framebuffer to be considered enabled. */ 4818 num_active += (new_plane_state->fb != NULL); 4819 } 4820 4821 return num_active; 4822 } 4823 4824 /* 4825 * Sets whether interrupts should be enabled on a specific CRTC. 4826 * We require that the stream be enabled and that there exist active 4827 * DC planes on the stream. 4828 */ 4829 static void 4830 dm_update_crtc_interrupt_state(struct drm_crtc *crtc, 4831 struct drm_crtc_state *new_crtc_state) 4832 { 4833 struct dm_crtc_state *dm_new_crtc_state = 4834 to_dm_crtc_state(new_crtc_state); 4835 4836 dm_new_crtc_state->active_planes = 0; 4837 dm_new_crtc_state->interrupts_enabled = false; 4838 4839 if (!dm_new_crtc_state->stream) 4840 return; 4841 4842 dm_new_crtc_state->active_planes = 4843 count_crtc_active_planes(new_crtc_state); 4844 4845 dm_new_crtc_state->interrupts_enabled = 4846 dm_new_crtc_state->active_planes > 0; 4847 } 4848 4849 static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc, 4850 struct drm_crtc_state *state) 4851 { 4852 struct amdgpu_device *adev = crtc->dev->dev_private; 4853 struct dc *dc = adev->dm.dc; 4854 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(state); 4855 int ret = -EINVAL; 4856 4857 /* 4858 * Update interrupt state for the CRTC. This needs to happen whenever 4859 * the CRTC has changed or whenever any of its planes have changed. 4860 * Atomic check satisfies both of these requirements since the CRTC 4861 * is added to the state by DRM during drm_atomic_helper_check_planes. 4862 */ 4863 dm_update_crtc_interrupt_state(crtc, state); 4864 4865 if (unlikely(!dm_crtc_state->stream && 4866 modeset_required(state, NULL, dm_crtc_state->stream))) { 4867 WARN_ON(1); 4868 return ret; 4869 } 4870 4871 /* In some use cases, like reset, no stream is attached */ 4872 if (!dm_crtc_state->stream) 4873 return 0; 4874 4875 /* 4876 * We want at least one hardware plane enabled to use 4877 * the stream with a cursor enabled. 4878 */ 4879 if (state->enable && state->active && 4880 does_crtc_have_active_cursor(state) && 4881 dm_crtc_state->active_planes == 0) 4882 return -EINVAL; 4883 4884 if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK) 4885 return 0; 4886 4887 return ret; 4888 } 4889 4890 static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc, 4891 const struct drm_display_mode *mode, 4892 struct drm_display_mode *adjusted_mode) 4893 { 4894 return true; 4895 } 4896 4897 static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = { 4898 .disable = dm_crtc_helper_disable, 4899 .atomic_check = dm_crtc_helper_atomic_check, 4900 .mode_fixup = dm_crtc_helper_mode_fixup 4901 }; 4902 4903 static void dm_encoder_helper_disable(struct drm_encoder *encoder) 4904 { 4905 4906 } 4907 4908 static int convert_dc_color_depth_into_bpc (enum dc_color_depth display_color_depth) 4909 { 4910 switch (display_color_depth) { 4911 case COLOR_DEPTH_666: 4912 return 6; 4913 case COLOR_DEPTH_888: 4914 return 8; 4915 case COLOR_DEPTH_101010: 4916 return 10; 4917 case COLOR_DEPTH_121212: 4918 return 12; 4919 case COLOR_DEPTH_141414: 4920 return 14; 4921 case COLOR_DEPTH_161616: 4922 return 16; 4923 default: 4924 break; 4925 } 4926 return 0; 4927 } 4928 4929 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, 4930 struct drm_crtc_state *crtc_state, 4931 struct drm_connector_state *conn_state) 4932 { 4933 struct drm_atomic_state *state = crtc_state->state; 4934 struct drm_connector *connector = conn_state->connector; 4935 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 4936 struct dm_connector_state *dm_new_connector_state = to_dm_connector_state(conn_state); 4937 const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; 4938 struct drm_dp_mst_topology_mgr *mst_mgr; 4939 struct drm_dp_mst_port *mst_port; 4940 enum dc_color_depth color_depth; 4941 int clock, bpp = 0; 4942 bool is_y420 = false; 4943 4944 if (!aconnector->port || !aconnector->dc_sink) 4945 return 0; 4946 4947 mst_port = aconnector->port; 4948 mst_mgr = &aconnector->mst_port->mst_mgr; 4949 4950 if (!crtc_state->connectors_changed && !crtc_state->mode_changed) 4951 return 0; 4952 4953 if (!state->duplicated) { 4954 is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) && 4955 aconnector->force_yuv420_output; 4956 color_depth = convert_color_depth_from_display_info(connector, conn_state, 4957 is_y420); 4958 bpp = convert_dc_color_depth_into_bpc(color_depth) * 3; 4959 clock = adjusted_mode->clock; 4960 dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false); 4961 } 4962 dm_new_connector_state->vcpi_slots = drm_dp_atomic_find_vcpi_slots(state, 4963 mst_mgr, 4964 mst_port, 4965 dm_new_connector_state->pbn, 4966 0); 4967 if (dm_new_connector_state->vcpi_slots < 0) { 4968 DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots); 4969 return dm_new_connector_state->vcpi_slots; 4970 } 4971 return 0; 4972 } 4973 4974 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = { 4975 .disable = dm_encoder_helper_disable, 4976 .atomic_check = dm_encoder_helper_atomic_check 4977 }; 4978 4979 #if defined(CONFIG_DRM_AMD_DC_DCN) 4980 static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state, 4981 struct dc_state *dc_state) 4982 { 4983 struct dc_stream_state *stream = NULL; 4984 struct drm_connector *connector; 4985 struct drm_connector_state *new_con_state, *old_con_state __unused; 4986 struct amdgpu_dm_connector *aconnector; 4987 struct dm_connector_state *dm_conn_state; 4988 int i, j, clock, bpp; 4989 int vcpi, pbn_div, pbn = 0; 4990 4991 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 4992 4993 aconnector = to_amdgpu_dm_connector(connector); 4994 4995 if (!aconnector->port) 4996 continue; 4997 4998 if (!new_con_state || !new_con_state->crtc) 4999 continue; 5000 5001 dm_conn_state = to_dm_connector_state(new_con_state); 5002 5003 for (j = 0; j < dc_state->stream_count; j++) { 5004 stream = dc_state->streams[j]; 5005 if (!stream) 5006 continue; 5007 5008 if ((struct amdgpu_dm_connector*)stream->dm_stream_context == aconnector) 5009 break; 5010 5011 stream = NULL; 5012 } 5013 5014 if (!stream) 5015 continue; 5016 5017 if (stream->timing.flags.DSC != 1) { 5018 drm_dp_mst_atomic_enable_dsc(state, 5019 aconnector->port, 5020 dm_conn_state->pbn, 5021 0, 5022 false); 5023 continue; 5024 } 5025 5026 pbn_div = dm_mst_get_pbn_divider(stream->link); 5027 bpp = stream->timing.dsc_cfg.bits_per_pixel; 5028 clock = stream->timing.pix_clk_100hz / 10; 5029 pbn = drm_dp_calc_pbn_mode(clock, bpp, true); 5030 vcpi = drm_dp_mst_atomic_enable_dsc(state, 5031 aconnector->port, 5032 pbn, pbn_div, 5033 true); 5034 if (vcpi < 0) 5035 return vcpi; 5036 5037 dm_conn_state->pbn = pbn; 5038 dm_conn_state->vcpi_slots = vcpi; 5039 } 5040 return 0; 5041 } 5042 #endif 5043 5044 static void dm_drm_plane_reset(struct drm_plane *plane) 5045 { 5046 struct dm_plane_state *amdgpu_state = NULL; 5047 5048 if (plane->state) 5049 plane->funcs->atomic_destroy_state(plane, plane->state); 5050 5051 amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL); 5052 WARN_ON(amdgpu_state == NULL); 5053 5054 if (amdgpu_state) 5055 __drm_atomic_helper_plane_reset(plane, &amdgpu_state->base); 5056 } 5057 5058 static struct drm_plane_state * 5059 dm_drm_plane_duplicate_state(struct drm_plane *plane) 5060 { 5061 struct dm_plane_state *dm_plane_state, *old_dm_plane_state; 5062 5063 old_dm_plane_state = to_dm_plane_state(plane->state); 5064 dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL); 5065 if (!dm_plane_state) 5066 return NULL; 5067 5068 __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base); 5069 5070 if (old_dm_plane_state->dc_state) { 5071 dm_plane_state->dc_state = old_dm_plane_state->dc_state; 5072 dc_plane_state_retain(dm_plane_state->dc_state); 5073 } 5074 5075 return &dm_plane_state->base; 5076 } 5077 5078 void dm_drm_plane_destroy_state(struct drm_plane *plane, 5079 struct drm_plane_state *state) 5080 { 5081 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state); 5082 5083 if (dm_plane_state->dc_state) 5084 dc_plane_state_release(dm_plane_state->dc_state); 5085 5086 drm_atomic_helper_plane_destroy_state(plane, state); 5087 } 5088 5089 static const struct drm_plane_funcs dm_plane_funcs = { 5090 .update_plane = drm_atomic_helper_update_plane, 5091 .disable_plane = drm_atomic_helper_disable_plane, 5092 .destroy = drm_primary_helper_destroy, 5093 .reset = dm_drm_plane_reset, 5094 .atomic_duplicate_state = dm_drm_plane_duplicate_state, 5095 .atomic_destroy_state = dm_drm_plane_destroy_state, 5096 }; 5097 5098 static int dm_plane_helper_prepare_fb(struct drm_plane *plane, 5099 struct drm_plane_state *new_state) 5100 { 5101 struct amdgpu_framebuffer *afb; 5102 struct drm_gem_object *obj; 5103 struct amdgpu_device *adev; 5104 struct amdgpu_bo *rbo; 5105 struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old; 5106 struct list_head list; 5107 struct ttm_validate_buffer tv; 5108 struct ww_acquire_ctx ticket; 5109 uint64_t tiling_flags; 5110 uint32_t domain; 5111 int r; 5112 5113 dm_plane_state_old = to_dm_plane_state(plane->state); 5114 dm_plane_state_new = to_dm_plane_state(new_state); 5115 5116 if (!new_state->fb) { 5117 DRM_DEBUG_DRIVER("No FB bound\n"); 5118 return 0; 5119 } 5120 5121 afb = to_amdgpu_framebuffer(new_state->fb); 5122 obj = new_state->fb->obj[0]; 5123 rbo = gem_to_amdgpu_bo(obj); 5124 adev = amdgpu_ttm_adev(rbo->tbo.bdev); 5125 INIT_LIST_HEAD(&list); 5126 5127 tv.bo = &rbo->tbo; 5128 tv.num_shared = 1; 5129 list_add(&tv.head, &list); 5130 5131 r = ttm_eu_reserve_buffers(&ticket, &list, false, NULL); 5132 if (r) { 5133 dev_err(adev->dev, "fail to reserve bo (%d)\n", r); 5134 return r; 5135 } 5136 5137 if (plane->type != DRM_PLANE_TYPE_CURSOR) 5138 domain = amdgpu_display_supported_domains(adev, rbo->flags); 5139 else 5140 domain = AMDGPU_GEM_DOMAIN_VRAM; 5141 5142 r = amdgpu_bo_pin(rbo, domain); 5143 if (unlikely(r != 0)) { 5144 if (r != -ERESTARTSYS) 5145 DRM_ERROR("Failed to pin framebuffer with error %d\n", r); 5146 ttm_eu_backoff_reservation(&ticket, &list); 5147 return r; 5148 } 5149 5150 r = amdgpu_ttm_alloc_gart(&rbo->tbo); 5151 if (unlikely(r != 0)) { 5152 amdgpu_bo_unpin(rbo); 5153 ttm_eu_backoff_reservation(&ticket, &list); 5154 DRM_ERROR("%p bind failed\n", rbo); 5155 return r; 5156 } 5157 5158 amdgpu_bo_get_tiling_flags(rbo, &tiling_flags); 5159 5160 ttm_eu_backoff_reservation(&ticket, &list); 5161 5162 afb->address = amdgpu_bo_gpu_offset(rbo); 5163 5164 amdgpu_bo_ref(rbo); 5165 5166 if (dm_plane_state_new->dc_state && 5167 dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) { 5168 struct dc_plane_state *plane_state = dm_plane_state_new->dc_state; 5169 5170 fill_plane_buffer_attributes( 5171 adev, afb, plane_state->format, plane_state->rotation, 5172 tiling_flags, &plane_state->tiling_info, 5173 &plane_state->plane_size, &plane_state->dcc, 5174 &plane_state->address); 5175 } 5176 5177 return 0; 5178 } 5179 5180 static void dm_plane_helper_cleanup_fb(struct drm_plane *plane, 5181 struct drm_plane_state *old_state) 5182 { 5183 struct amdgpu_bo *rbo; 5184 int r; 5185 5186 if (!old_state->fb) 5187 return; 5188 5189 rbo = gem_to_amdgpu_bo(old_state->fb->obj[0]); 5190 r = amdgpu_bo_reserve(rbo, false); 5191 if (unlikely(r)) { 5192 DRM_ERROR("failed to reserve rbo before unpin\n"); 5193 return; 5194 } 5195 5196 amdgpu_bo_unpin(rbo); 5197 amdgpu_bo_unreserve(rbo); 5198 amdgpu_bo_unref(&rbo); 5199 } 5200 5201 static int dm_plane_atomic_check(struct drm_plane *plane, 5202 struct drm_plane_state *state) 5203 { 5204 struct amdgpu_device *adev = plane->dev->dev_private; 5205 struct dc *dc = adev->dm.dc; 5206 struct dm_plane_state *dm_plane_state; 5207 struct dc_scaling_info scaling_info; 5208 int ret; 5209 5210 dm_plane_state = to_dm_plane_state(state); 5211 5212 if (!dm_plane_state->dc_state) 5213 return 0; 5214 5215 ret = fill_dc_scaling_info(state, &scaling_info); 5216 if (ret) 5217 return ret; 5218 5219 if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK) 5220 return 0; 5221 5222 return -EINVAL; 5223 } 5224 5225 static int dm_plane_atomic_async_check(struct drm_plane *plane, 5226 struct drm_plane_state *new_plane_state) 5227 { 5228 /* Only support async updates on cursor planes. */ 5229 if (plane->type != DRM_PLANE_TYPE_CURSOR) 5230 return -EINVAL; 5231 5232 return 0; 5233 } 5234 5235 static void dm_plane_atomic_async_update(struct drm_plane *plane, 5236 struct drm_plane_state *new_state) 5237 { 5238 struct drm_plane_state *old_state = 5239 drm_atomic_get_old_plane_state(new_state->state, plane); 5240 5241 swap(plane->state->fb, new_state->fb); 5242 5243 plane->state->src_x = new_state->src_x; 5244 plane->state->src_y = new_state->src_y; 5245 plane->state->src_w = new_state->src_w; 5246 plane->state->src_h = new_state->src_h; 5247 plane->state->crtc_x = new_state->crtc_x; 5248 plane->state->crtc_y = new_state->crtc_y; 5249 plane->state->crtc_w = new_state->crtc_w; 5250 plane->state->crtc_h = new_state->crtc_h; 5251 5252 handle_cursor_update(plane, old_state); 5253 } 5254 5255 static const struct drm_plane_helper_funcs dm_plane_helper_funcs = { 5256 .prepare_fb = dm_plane_helper_prepare_fb, 5257 .cleanup_fb = dm_plane_helper_cleanup_fb, 5258 .atomic_check = dm_plane_atomic_check, 5259 .atomic_async_check = dm_plane_atomic_async_check, 5260 .atomic_async_update = dm_plane_atomic_async_update 5261 }; 5262 5263 /* 5264 * TODO: these are currently initialized to rgb formats only. 5265 * For future use cases we should either initialize them dynamically based on 5266 * plane capabilities, or initialize this array to all formats, so internal drm 5267 * check will succeed, and let DC implement proper check 5268 */ 5269 static const uint32_t rgb_formats[] = { 5270 DRM_FORMAT_XRGB8888, 5271 DRM_FORMAT_ARGB8888, 5272 DRM_FORMAT_RGBA8888, 5273 DRM_FORMAT_XRGB2101010, 5274 DRM_FORMAT_XBGR2101010, 5275 DRM_FORMAT_ARGB2101010, 5276 DRM_FORMAT_ABGR2101010, 5277 DRM_FORMAT_XBGR8888, 5278 DRM_FORMAT_ABGR8888, 5279 DRM_FORMAT_RGB565, 5280 }; 5281 5282 static const uint32_t overlay_formats[] = { 5283 DRM_FORMAT_XRGB8888, 5284 DRM_FORMAT_ARGB8888, 5285 DRM_FORMAT_RGBA8888, 5286 DRM_FORMAT_XBGR8888, 5287 DRM_FORMAT_ABGR8888, 5288 DRM_FORMAT_RGB565 5289 }; 5290 5291 static const u32 cursor_formats[] = { 5292 DRM_FORMAT_ARGB8888 5293 }; 5294 5295 static int get_plane_formats(const struct drm_plane *plane, 5296 const struct dc_plane_cap *plane_cap, 5297 uint32_t *formats, int max_formats) 5298 { 5299 int i, num_formats = 0; 5300 5301 /* 5302 * TODO: Query support for each group of formats directly from 5303 * DC plane caps. This will require adding more formats to the 5304 * caps list. 5305 */ 5306 5307 switch (plane->type) { 5308 case DRM_PLANE_TYPE_PRIMARY: 5309 for (i = 0; i < ARRAY_SIZE(rgb_formats); ++i) { 5310 if (num_formats >= max_formats) 5311 break; 5312 5313 formats[num_formats++] = rgb_formats[i]; 5314 } 5315 5316 if (plane_cap && plane_cap->pixel_format_support.nv12) 5317 formats[num_formats++] = DRM_FORMAT_NV12; 5318 break; 5319 5320 case DRM_PLANE_TYPE_OVERLAY: 5321 for (i = 0; i < ARRAY_SIZE(overlay_formats); ++i) { 5322 if (num_formats >= max_formats) 5323 break; 5324 5325 formats[num_formats++] = overlay_formats[i]; 5326 } 5327 break; 5328 5329 case DRM_PLANE_TYPE_CURSOR: 5330 for (i = 0; i < ARRAY_SIZE(cursor_formats); ++i) { 5331 if (num_formats >= max_formats) 5332 break; 5333 5334 formats[num_formats++] = cursor_formats[i]; 5335 } 5336 break; 5337 } 5338 5339 return num_formats; 5340 } 5341 5342 static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, 5343 struct drm_plane *plane, 5344 unsigned long possible_crtcs, 5345 const struct dc_plane_cap *plane_cap) 5346 { 5347 uint32_t formats[32]; 5348 int num_formats; 5349 int res = -EPERM; 5350 5351 num_formats = get_plane_formats(plane, plane_cap, formats, 5352 ARRAY_SIZE(formats)); 5353 5354 res = drm_universal_plane_init(dm->adev->ddev, plane, possible_crtcs, 5355 &dm_plane_funcs, formats, num_formats, 5356 NULL, plane->type, NULL); 5357 if (res) 5358 return res; 5359 5360 if (plane->type == DRM_PLANE_TYPE_OVERLAY && 5361 plane_cap && plane_cap->per_pixel_alpha) { 5362 unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) | 5363 BIT(DRM_MODE_BLEND_PREMULTI); 5364 5365 drm_plane_create_alpha_property(plane); 5366 drm_plane_create_blend_mode_property(plane, blend_caps); 5367 } 5368 5369 if (plane->type == DRM_PLANE_TYPE_PRIMARY && 5370 plane_cap && plane_cap->pixel_format_support.nv12) { 5371 /* This only affects YUV formats. */ 5372 drm_plane_create_color_properties( 5373 plane, 5374 BIT(DRM_COLOR_YCBCR_BT601) | 5375 BIT(DRM_COLOR_YCBCR_BT709), 5376 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | 5377 BIT(DRM_COLOR_YCBCR_FULL_RANGE), 5378 DRM_COLOR_YCBCR_BT709, DRM_COLOR_YCBCR_LIMITED_RANGE); 5379 } 5380 5381 drm_plane_helper_add(plane, &dm_plane_helper_funcs); 5382 5383 /* Create (reset) the plane state */ 5384 if (plane->funcs->reset) 5385 plane->funcs->reset(plane); 5386 5387 return 0; 5388 } 5389 5390 static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, 5391 struct drm_plane *plane, 5392 uint32_t crtc_index) 5393 { 5394 struct amdgpu_crtc *acrtc = NULL; 5395 struct drm_plane *cursor_plane; 5396 5397 int res = -ENOMEM; 5398 5399 cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL); 5400 if (!cursor_plane) 5401 goto fail; 5402 5403 cursor_plane->type = DRM_PLANE_TYPE_CURSOR; 5404 res = amdgpu_dm_plane_init(dm, cursor_plane, 0, NULL); 5405 5406 acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL); 5407 if (!acrtc) 5408 goto fail; 5409 5410 res = drm_crtc_init_with_planes( 5411 dm->ddev, 5412 &acrtc->base, 5413 plane, 5414 cursor_plane, 5415 &amdgpu_dm_crtc_funcs, NULL); 5416 5417 if (res) 5418 goto fail; 5419 5420 drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs); 5421 5422 /* Create (reset) the plane state */ 5423 if (acrtc->base.funcs->reset) 5424 acrtc->base.funcs->reset(&acrtc->base); 5425 5426 acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size; 5427 acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size; 5428 5429 acrtc->crtc_id = crtc_index; 5430 acrtc->base.enabled = false; 5431 acrtc->otg_inst = -1; 5432 5433 dm->adev->mode_info.crtcs[crtc_index] = acrtc; 5434 drm_crtc_enable_color_mgmt(&acrtc->base, MAX_COLOR_LUT_ENTRIES, 5435 true, MAX_COLOR_LUT_ENTRIES); 5436 drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES); 5437 5438 return 0; 5439 5440 fail: 5441 kfree(acrtc); 5442 kfree(cursor_plane); 5443 return res; 5444 } 5445 5446 5447 static int to_drm_connector_type(enum signal_type st) 5448 { 5449 switch (st) { 5450 case SIGNAL_TYPE_HDMI_TYPE_A: 5451 return DRM_MODE_CONNECTOR_HDMIA; 5452 case SIGNAL_TYPE_EDP: 5453 return DRM_MODE_CONNECTOR_eDP; 5454 case SIGNAL_TYPE_LVDS: 5455 return DRM_MODE_CONNECTOR_LVDS; 5456 case SIGNAL_TYPE_RGB: 5457 return DRM_MODE_CONNECTOR_VGA; 5458 case SIGNAL_TYPE_DISPLAY_PORT: 5459 case SIGNAL_TYPE_DISPLAY_PORT_MST: 5460 return DRM_MODE_CONNECTOR_DisplayPort; 5461 case SIGNAL_TYPE_DVI_DUAL_LINK: 5462 case SIGNAL_TYPE_DVI_SINGLE_LINK: 5463 return DRM_MODE_CONNECTOR_DVID; 5464 case SIGNAL_TYPE_VIRTUAL: 5465 return DRM_MODE_CONNECTOR_VIRTUAL; 5466 5467 default: 5468 return DRM_MODE_CONNECTOR_Unknown; 5469 } 5470 } 5471 5472 static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector) 5473 { 5474 struct drm_encoder *encoder; 5475 5476 /* There is only one encoder per connector */ 5477 drm_connector_for_each_possible_encoder(connector, encoder) 5478 return encoder; 5479 5480 return NULL; 5481 } 5482 5483 static void amdgpu_dm_get_native_mode(struct drm_connector *connector) 5484 { 5485 struct drm_encoder *encoder; 5486 struct amdgpu_encoder *amdgpu_encoder; 5487 5488 encoder = amdgpu_dm_connector_to_encoder(connector); 5489 5490 if (encoder == NULL) 5491 return; 5492 5493 amdgpu_encoder = to_amdgpu_encoder(encoder); 5494 5495 amdgpu_encoder->native_mode.clock = 0; 5496 5497 if (!list_empty(&connector->probed_modes)) { 5498 struct drm_display_mode *preferred_mode = NULL; 5499 5500 list_for_each_entry(preferred_mode, 5501 &connector->probed_modes, 5502 head) { 5503 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) 5504 amdgpu_encoder->native_mode = *preferred_mode; 5505 5506 break; 5507 } 5508 5509 } 5510 } 5511 5512 static struct drm_display_mode * 5513 amdgpu_dm_create_common_mode(struct drm_encoder *encoder, 5514 char *name, 5515 int hdisplay, int vdisplay) 5516 { 5517 struct drm_device *dev = encoder->dev; 5518 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 5519 struct drm_display_mode *mode = NULL; 5520 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 5521 5522 mode = drm_mode_duplicate(dev, native_mode); 5523 5524 if (mode == NULL) 5525 return NULL; 5526 5527 mode->hdisplay = hdisplay; 5528 mode->vdisplay = vdisplay; 5529 mode->type &= ~DRM_MODE_TYPE_PREFERRED; 5530 strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN); 5531 5532 return mode; 5533 5534 } 5535 5536 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder, 5537 struct drm_connector *connector) 5538 { 5539 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 5540 struct drm_display_mode *mode = NULL; 5541 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 5542 struct amdgpu_dm_connector *amdgpu_dm_connector = 5543 to_amdgpu_dm_connector(connector); 5544 int i; 5545 int n; 5546 struct mode_size { 5547 char name[DRM_DISPLAY_MODE_LEN]; 5548 int w; 5549 int h; 5550 } common_modes[] = { 5551 { "640x480", 640, 480}, 5552 { "800x600", 800, 600}, 5553 { "1024x768", 1024, 768}, 5554 { "1280x720", 1280, 720}, 5555 { "1280x800", 1280, 800}, 5556 {"1280x1024", 1280, 1024}, 5557 { "1440x900", 1440, 900}, 5558 {"1680x1050", 1680, 1050}, 5559 {"1600x1200", 1600, 1200}, 5560 {"1920x1080", 1920, 1080}, 5561 {"1920x1200", 1920, 1200} 5562 }; 5563 5564 n = ARRAY_SIZE(common_modes); 5565 5566 for (i = 0; i < n; i++) { 5567 struct drm_display_mode *curmode = NULL; 5568 bool mode_existed = false; 5569 5570 if (common_modes[i].w > native_mode->hdisplay || 5571 common_modes[i].h > native_mode->vdisplay || 5572 (common_modes[i].w == native_mode->hdisplay && 5573 common_modes[i].h == native_mode->vdisplay)) 5574 continue; 5575 5576 list_for_each_entry(curmode, &connector->probed_modes, head) { 5577 if (common_modes[i].w == curmode->hdisplay && 5578 common_modes[i].h == curmode->vdisplay) { 5579 mode_existed = true; 5580 break; 5581 } 5582 } 5583 5584 if (mode_existed) 5585 continue; 5586 5587 mode = amdgpu_dm_create_common_mode(encoder, 5588 common_modes[i].name, common_modes[i].w, 5589 common_modes[i].h); 5590 drm_mode_probed_add(connector, mode); 5591 amdgpu_dm_connector->num_modes++; 5592 } 5593 } 5594 5595 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector, 5596 struct edid *edid) 5597 { 5598 struct amdgpu_dm_connector *amdgpu_dm_connector = 5599 to_amdgpu_dm_connector(connector); 5600 5601 if (edid) { 5602 /* empty probed_modes */ 5603 INIT_LIST_HEAD(&connector->probed_modes); 5604 amdgpu_dm_connector->num_modes = 5605 drm_add_edid_modes(connector, edid); 5606 5607 /* sorting the probed modes before calling function 5608 * amdgpu_dm_get_native_mode() since EDID can have 5609 * more than one preferred mode. The modes that are 5610 * later in the probed mode list could be of higher 5611 * and preferred resolution. For example, 3840x2160 5612 * resolution in base EDID preferred timing and 4096x2160 5613 * preferred resolution in DID extension block later. 5614 */ 5615 drm_mode_sort(&connector->probed_modes); 5616 amdgpu_dm_get_native_mode(connector); 5617 } else { 5618 amdgpu_dm_connector->num_modes = 0; 5619 } 5620 } 5621 5622 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector) 5623 { 5624 struct amdgpu_dm_connector *amdgpu_dm_connector = 5625 to_amdgpu_dm_connector(connector); 5626 struct drm_encoder *encoder; 5627 struct edid *edid = amdgpu_dm_connector->edid; 5628 5629 encoder = amdgpu_dm_connector_to_encoder(connector); 5630 5631 if (!edid || !drm_edid_is_valid(edid)) { 5632 amdgpu_dm_connector->num_modes = 5633 drm_add_modes_noedid(connector, 640, 480); 5634 } else { 5635 amdgpu_dm_connector_ddc_get_modes(connector, edid); 5636 amdgpu_dm_connector_add_common_modes(encoder, connector); 5637 } 5638 amdgpu_dm_fbc_init(connector); 5639 5640 return amdgpu_dm_connector->num_modes; 5641 } 5642 5643 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, 5644 struct amdgpu_dm_connector *aconnector, 5645 int connector_type, 5646 struct dc_link *link, 5647 int link_index) 5648 { 5649 struct amdgpu_device *adev = dm->ddev->dev_private; 5650 5651 /* 5652 * Some of the properties below require access to state, like bpc. 5653 * Allocate some default initial connector state with our reset helper. 5654 */ 5655 if (aconnector->base.funcs->reset) 5656 aconnector->base.funcs->reset(&aconnector->base); 5657 5658 aconnector->connector_id = link_index; 5659 aconnector->dc_link = link; 5660 aconnector->base.interlace_allowed = false; 5661 aconnector->base.doublescan_allowed = false; 5662 aconnector->base.stereo_allowed = false; 5663 aconnector->base.dpms = DRM_MODE_DPMS_OFF; 5664 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */ 5665 aconnector->audio_inst = -1; 5666 mutex_init(&aconnector->hpd_lock); 5667 5668 /* 5669 * configure support HPD hot plug connector_>polled default value is 0 5670 * which means HPD hot plug not supported 5671 */ 5672 switch (connector_type) { 5673 case DRM_MODE_CONNECTOR_HDMIA: 5674 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 5675 aconnector->base.ycbcr_420_allowed = 5676 link->link_enc->features.hdmi_ycbcr420_supported ? true : false; 5677 break; 5678 case DRM_MODE_CONNECTOR_DisplayPort: 5679 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 5680 aconnector->base.ycbcr_420_allowed = 5681 link->link_enc->features.dp_ycbcr420_supported ? true : false; 5682 break; 5683 case DRM_MODE_CONNECTOR_DVID: 5684 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 5685 break; 5686 default: 5687 break; 5688 } 5689 5690 drm_object_attach_property(&aconnector->base.base, 5691 dm->ddev->mode_config.scaling_mode_property, 5692 DRM_MODE_SCALE_NONE); 5693 5694 drm_object_attach_property(&aconnector->base.base, 5695 adev->mode_info.underscan_property, 5696 UNDERSCAN_OFF); 5697 drm_object_attach_property(&aconnector->base.base, 5698 adev->mode_info.underscan_hborder_property, 5699 0); 5700 drm_object_attach_property(&aconnector->base.base, 5701 adev->mode_info.underscan_vborder_property, 5702 0); 5703 5704 drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16); 5705 5706 /* This defaults to the max in the range, but we want 8bpc for non-edp. */ 5707 aconnector->base.state->max_bpc = (connector_type == DRM_MODE_CONNECTOR_eDP) ? 16 : 8; 5708 aconnector->base.state->max_requested_bpc = aconnector->base.state->max_bpc; 5709 5710 if (connector_type == DRM_MODE_CONNECTOR_eDP && 5711 dc_is_dmcu_initialized(adev->dm.dc)) { 5712 drm_object_attach_property(&aconnector->base.base, 5713 adev->mode_info.abm_level_property, 0); 5714 } 5715 5716 if (connector_type == DRM_MODE_CONNECTOR_HDMIA || 5717 connector_type == DRM_MODE_CONNECTOR_DisplayPort || 5718 connector_type == DRM_MODE_CONNECTOR_eDP) { 5719 drm_object_attach_property( 5720 &aconnector->base.base, 5721 dm->ddev->mode_config.hdr_output_metadata_property, 0); 5722 5723 drm_connector_attach_vrr_capable_property( 5724 &aconnector->base); 5725 #ifdef CONFIG_DRM_AMD_DC_HDCP 5726 if (adev->dm.hdcp_workqueue) 5727 drm_connector_attach_content_protection_property(&aconnector->base, true); 5728 #endif 5729 } 5730 } 5731 5732 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap, 5733 struct i2c_msg *msgs, int num) 5734 { 5735 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap); 5736 struct ddc_service *ddc_service = i2c->ddc_service; 5737 struct i2c_command cmd; 5738 int i; 5739 int result = -EIO; 5740 5741 cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL); 5742 5743 if (!cmd.payloads) 5744 return result; 5745 5746 cmd.number_of_payloads = num; 5747 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT; 5748 cmd.speed = 100; 5749 5750 for (i = 0; i < num; i++) { 5751 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD); 5752 cmd.payloads[i].address = msgs[i].addr; 5753 cmd.payloads[i].length = msgs[i].len; 5754 cmd.payloads[i].data = msgs[i].buf; 5755 } 5756 5757 if (dc_submit_i2c( 5758 ddc_service->ctx->dc, 5759 ddc_service->ddc_pin->hw_info.ddc_channel, 5760 &cmd)) 5761 result = num; 5762 5763 kfree(cmd.payloads); 5764 return result; 5765 } 5766 5767 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap) 5768 { 5769 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 5770 } 5771 5772 static const struct i2c_algorithm amdgpu_dm_i2c_algo = { 5773 .master_xfer = amdgpu_dm_i2c_xfer, 5774 .functionality = amdgpu_dm_i2c_func, 5775 }; 5776 5777 static struct amdgpu_i2c_adapter * 5778 create_i2c(struct ddc_service *ddc_service, 5779 int link_index, 5780 int *res) 5781 { 5782 struct amdgpu_device *adev = ddc_service->ctx->driver_context; 5783 struct amdgpu_i2c_adapter *i2c; 5784 5785 i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL); 5786 if (!i2c) 5787 return NULL; 5788 i2c->base.owner = THIS_MODULE; 5789 i2c->base.class = I2C_CLASS_DDC; 5790 i2c->base.dev.parent = pci_dev_dev(adev->pdev); 5791 i2c->base.algo = &amdgpu_dm_i2c_algo; 5792 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index); 5793 i2c_set_adapdata(&i2c->base, i2c); 5794 i2c->ddc_service = ddc_service; 5795 i2c->ddc_service->ddc_pin->hw_info.ddc_channel = link_index; 5796 5797 return i2c; 5798 } 5799 5800 5801 /* 5802 * Note: this function assumes that dc_link_detect() was called for the 5803 * dc_link which will be represented by this aconnector. 5804 */ 5805 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, 5806 struct amdgpu_dm_connector *aconnector, 5807 uint32_t link_index, 5808 struct amdgpu_encoder *aencoder) 5809 { 5810 int res = 0; 5811 int connector_type; 5812 struct dc *dc = dm->dc; 5813 struct dc_link *link = dc_get_link_at_index(dc, link_index); 5814 struct amdgpu_i2c_adapter *i2c; 5815 5816 link->priv = aconnector; 5817 5818 DRM_DEBUG_DRIVER("%s()\n", __func__); 5819 5820 i2c = create_i2c(link->ddc, link->link_index, &res); 5821 if (!i2c) { 5822 DRM_ERROR("Failed to create i2c adapter data\n"); 5823 return -ENOMEM; 5824 } 5825 5826 aconnector->i2c = i2c; 5827 res = i2c_add_adapter(&i2c->base); 5828 5829 if (res) { 5830 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index); 5831 goto out_free; 5832 } 5833 5834 connector_type = to_drm_connector_type(link->connector_signal); 5835 5836 res = drm_connector_init_with_ddc( 5837 dm->ddev, 5838 &aconnector->base, 5839 &amdgpu_dm_connector_funcs, 5840 connector_type, 5841 &i2c->base); 5842 5843 if (res) { 5844 DRM_ERROR("connector_init failed\n"); 5845 aconnector->connector_id = -1; 5846 goto out_free; 5847 } 5848 5849 drm_connector_helper_add( 5850 &aconnector->base, 5851 &amdgpu_dm_connector_helper_funcs); 5852 5853 amdgpu_dm_connector_init_helper( 5854 dm, 5855 aconnector, 5856 connector_type, 5857 link, 5858 link_index); 5859 5860 drm_connector_attach_encoder( 5861 &aconnector->base, &aencoder->base); 5862 5863 drm_connector_register(&aconnector->base); 5864 #if defined(CONFIG_DEBUG_FS) 5865 connector_debugfs_init(aconnector); 5866 aconnector->debugfs_dpcd_address = 0; 5867 aconnector->debugfs_dpcd_size = 0; 5868 #endif 5869 5870 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort 5871 || connector_type == DRM_MODE_CONNECTOR_eDP) 5872 amdgpu_dm_initialize_dp_connector(dm, aconnector); 5873 5874 out_free: 5875 if (res) { 5876 kfree(i2c); 5877 aconnector->i2c = NULL; 5878 } 5879 return res; 5880 } 5881 5882 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev) 5883 { 5884 switch (adev->mode_info.num_crtc) { 5885 case 1: 5886 return 0x1; 5887 case 2: 5888 return 0x3; 5889 case 3: 5890 return 0x7; 5891 case 4: 5892 return 0xf; 5893 case 5: 5894 return 0x1f; 5895 case 6: 5896 default: 5897 return 0x3f; 5898 } 5899 } 5900 5901 static int amdgpu_dm_encoder_init(struct drm_device *dev, 5902 struct amdgpu_encoder *aencoder, 5903 uint32_t link_index) 5904 { 5905 struct amdgpu_device *adev = dev->dev_private; 5906 5907 int res = drm_encoder_init(dev, 5908 &aencoder->base, 5909 &amdgpu_dm_encoder_funcs, 5910 DRM_MODE_ENCODER_TMDS, 5911 NULL); 5912 5913 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev); 5914 5915 if (!res) 5916 aencoder->encoder_id = link_index; 5917 else 5918 aencoder->encoder_id = -1; 5919 5920 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs); 5921 5922 return res; 5923 } 5924 5925 static void manage_dm_interrupts(struct amdgpu_device *adev, 5926 struct amdgpu_crtc *acrtc, 5927 bool enable) 5928 { 5929 /* 5930 * this is not correct translation but will work as soon as VBLANK 5931 * constant is the same as PFLIP 5932 */ 5933 int irq_type = 5934 amdgpu_display_crtc_idx_to_irq_type( 5935 adev, 5936 acrtc->crtc_id); 5937 5938 if (enable) { 5939 drm_crtc_vblank_on(&acrtc->base); 5940 amdgpu_irq_get( 5941 adev, 5942 &adev->pageflip_irq, 5943 irq_type); 5944 } else { 5945 5946 amdgpu_irq_put( 5947 adev, 5948 &adev->pageflip_irq, 5949 irq_type); 5950 drm_crtc_vblank_off(&acrtc->base); 5951 } 5952 } 5953 5954 static bool 5955 is_scaling_state_different(const struct dm_connector_state *dm_state, 5956 const struct dm_connector_state *old_dm_state) 5957 { 5958 if (dm_state->scaling != old_dm_state->scaling) 5959 return true; 5960 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) { 5961 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0) 5962 return true; 5963 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) { 5964 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0) 5965 return true; 5966 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder || 5967 dm_state->underscan_vborder != old_dm_state->underscan_vborder) 5968 return true; 5969 return false; 5970 } 5971 5972 #ifdef CONFIG_DRM_AMD_DC_HDCP 5973 static bool is_content_protection_different(struct drm_connector_state *state, 5974 const struct drm_connector_state *old_state, 5975 const struct drm_connector *connector, struct hdcp_workqueue *hdcp_w) 5976 { 5977 const struct amdgpu_dm_connector *aconnector = const_container_of(connector, struct amdgpu_dm_connector, base); 5978 5979 if (old_state->hdcp_content_type != state->hdcp_content_type && 5980 state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { 5981 state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 5982 return true; 5983 } 5984 5985 /* CP is being re enabled, ignore this */ 5986 if (old_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED && 5987 state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) { 5988 state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED; 5989 return false; 5990 } 5991 5992 /* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED */ 5993 if (old_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED && 5994 state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) 5995 state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 5996 5997 /* Check if something is connected/enabled, otherwise we start hdcp but nothing is connected/enabled 5998 * hot-plug, headless s3, dpms 5999 */ 6000 if (state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED && connector->dpms == DRM_MODE_DPMS_ON && 6001 aconnector->dc_sink != NULL) 6002 return true; 6003 6004 if (old_state->content_protection == state->content_protection) 6005 return false; 6006 6007 if (state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED) 6008 return true; 6009 6010 return false; 6011 } 6012 6013 #endif 6014 static void remove_stream(struct amdgpu_device *adev, 6015 struct amdgpu_crtc *acrtc, 6016 struct dc_stream_state *stream) 6017 { 6018 /* this is the update mode case */ 6019 6020 acrtc->otg_inst = -1; 6021 acrtc->enabled = false; 6022 } 6023 6024 static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc, 6025 struct dc_cursor_position *position) 6026 { 6027 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 6028 int x, y; 6029 int xorigin = 0, yorigin = 0; 6030 6031 position->enable = false; 6032 position->x = 0; 6033 position->y = 0; 6034 6035 if (!crtc || !plane->state->fb) 6036 return 0; 6037 6038 if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) || 6039 (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) { 6040 DRM_ERROR("%s: bad cursor width or height %d x %d\n", 6041 __func__, 6042 plane->state->crtc_w, 6043 plane->state->crtc_h); 6044 return -EINVAL; 6045 } 6046 6047 x = plane->state->crtc_x; 6048 y = plane->state->crtc_y; 6049 6050 if (x <= -amdgpu_crtc->max_cursor_width || 6051 y <= -amdgpu_crtc->max_cursor_height) 6052 return 0; 6053 6054 if (crtc->primary->state) { 6055 /* avivo cursor are offset into the total surface */ 6056 x += crtc->primary->state->src_x >> 16; 6057 y += crtc->primary->state->src_y >> 16; 6058 } 6059 6060 if (x < 0) { 6061 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); 6062 x = 0; 6063 } 6064 if (y < 0) { 6065 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); 6066 y = 0; 6067 } 6068 position->enable = true; 6069 position->x = x; 6070 position->y = y; 6071 position->x_hotspot = xorigin; 6072 position->y_hotspot = yorigin; 6073 6074 return 0; 6075 } 6076 6077 static void handle_cursor_update(struct drm_plane *plane, 6078 struct drm_plane_state *old_plane_state) 6079 { 6080 struct amdgpu_device *adev = plane->dev->dev_private; 6081 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb); 6082 struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc; 6083 struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL; 6084 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 6085 uint64_t address = afb ? afb->address : 0; 6086 struct dc_cursor_position position; 6087 struct dc_cursor_attributes attributes; 6088 int ret; 6089 6090 if (!plane->state->fb && !old_plane_state->fb) 6091 return; 6092 6093 DRM_DEBUG_DRIVER("%s: crtc_id=%d with size %d to %d\n", 6094 __func__, 6095 amdgpu_crtc->crtc_id, 6096 plane->state->crtc_w, 6097 plane->state->crtc_h); 6098 6099 ret = get_cursor_position(plane, crtc, &position); 6100 if (ret) 6101 return; 6102 6103 if (!position.enable) { 6104 /* turn off cursor */ 6105 if (crtc_state && crtc_state->stream) { 6106 mutex_lock(&adev->dm.dc_lock); 6107 dc_stream_set_cursor_position(crtc_state->stream, 6108 &position); 6109 mutex_unlock(&adev->dm.dc_lock); 6110 } 6111 return; 6112 } 6113 6114 amdgpu_crtc->cursor_width = plane->state->crtc_w; 6115 amdgpu_crtc->cursor_height = plane->state->crtc_h; 6116 6117 memset(&attributes, 0, sizeof(attributes)); 6118 attributes.address.high_part = upper_32_bits(address); 6119 attributes.address.low_part = lower_32_bits(address); 6120 attributes.width = plane->state->crtc_w; 6121 attributes.height = plane->state->crtc_h; 6122 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA; 6123 attributes.rotation_angle = 0; 6124 attributes.attribute_flags.value = 0; 6125 6126 attributes.pitch = attributes.width; 6127 6128 if (crtc_state->stream) { 6129 mutex_lock(&adev->dm.dc_lock); 6130 if (!dc_stream_set_cursor_attributes(crtc_state->stream, 6131 &attributes)) 6132 DRM_ERROR("DC failed to set cursor attributes\n"); 6133 6134 if (!dc_stream_set_cursor_position(crtc_state->stream, 6135 &position)) 6136 DRM_ERROR("DC failed to set cursor position\n"); 6137 mutex_unlock(&adev->dm.dc_lock); 6138 } 6139 } 6140 6141 static void prepare_flip_isr(struct amdgpu_crtc *acrtc) 6142 { 6143 6144 assert_spin_locked(&acrtc->base.dev->event_lock); 6145 WARN_ON(acrtc->event); 6146 6147 acrtc->event = acrtc->base.state->event; 6148 6149 /* Set the flip status */ 6150 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED; 6151 6152 /* Mark this event as consumed */ 6153 acrtc->base.state->event = NULL; 6154 6155 DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n", 6156 acrtc->crtc_id); 6157 } 6158 6159 static void update_freesync_state_on_stream( 6160 struct amdgpu_display_manager *dm, 6161 struct dm_crtc_state *new_crtc_state, 6162 struct dc_stream_state *new_stream, 6163 struct dc_plane_state *surface, 6164 u32 flip_timestamp_in_us) 6165 { 6166 struct mod_vrr_params vrr_params; 6167 struct dc_info_packet vrr_infopacket = {0}; 6168 struct amdgpu_device *adev = dm->adev; 6169 unsigned long flags; 6170 6171 if (!new_stream) 6172 return; 6173 6174 /* 6175 * TODO: Determine why min/max totals and vrefresh can be 0 here. 6176 * For now it's sufficient to just guard against these conditions. 6177 */ 6178 6179 if (!new_stream->timing.h_total || !new_stream->timing.v_total) 6180 return; 6181 6182 spin_lock_irqsave(&adev->ddev->event_lock, flags); 6183 vrr_params = new_crtc_state->vrr_params; 6184 6185 if (surface) { 6186 mod_freesync_handle_preflip( 6187 dm->freesync_module, 6188 surface, 6189 new_stream, 6190 flip_timestamp_in_us, 6191 &vrr_params); 6192 6193 if (adev->family < AMDGPU_FAMILY_AI && 6194 amdgpu_dm_vrr_active(new_crtc_state)) { 6195 mod_freesync_handle_v_update(dm->freesync_module, 6196 new_stream, &vrr_params); 6197 6198 /* Need to call this before the frame ends. */ 6199 dc_stream_adjust_vmin_vmax(dm->dc, 6200 new_crtc_state->stream, 6201 &vrr_params.adjust); 6202 } 6203 } 6204 6205 mod_freesync_build_vrr_infopacket( 6206 dm->freesync_module, 6207 new_stream, 6208 &vrr_params, 6209 PACKET_TYPE_VRR, 6210 TRANSFER_FUNC_UNKNOWN, 6211 &vrr_infopacket); 6212 6213 new_crtc_state->freesync_timing_changed |= 6214 (memcmp(&new_crtc_state->vrr_params.adjust, 6215 &vrr_params.adjust, 6216 sizeof(vrr_params.adjust)) != 0); 6217 6218 new_crtc_state->freesync_vrr_info_changed |= 6219 (memcmp(&new_crtc_state->vrr_infopacket, 6220 &vrr_infopacket, 6221 sizeof(vrr_infopacket)) != 0); 6222 6223 new_crtc_state->vrr_params = vrr_params; 6224 new_crtc_state->vrr_infopacket = vrr_infopacket; 6225 6226 new_stream->adjust = new_crtc_state->vrr_params.adjust; 6227 new_stream->vrr_infopacket = vrr_infopacket; 6228 6229 if (new_crtc_state->freesync_vrr_info_changed) 6230 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d", 6231 new_crtc_state->base.crtc->base.id, 6232 (int)new_crtc_state->base.vrr_enabled, 6233 (int)vrr_params.state); 6234 6235 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 6236 } 6237 6238 static void pre_update_freesync_state_on_stream( 6239 struct amdgpu_display_manager *dm, 6240 struct dm_crtc_state *new_crtc_state) 6241 { 6242 struct dc_stream_state *new_stream = new_crtc_state->stream; 6243 struct mod_vrr_params vrr_params; 6244 struct mod_freesync_config config = new_crtc_state->freesync_config; 6245 struct amdgpu_device *adev = dm->adev; 6246 unsigned long flags; 6247 6248 if (!new_stream) 6249 return; 6250 6251 /* 6252 * TODO: Determine why min/max totals and vrefresh can be 0 here. 6253 * For now it's sufficient to just guard against these conditions. 6254 */ 6255 if (!new_stream->timing.h_total || !new_stream->timing.v_total) 6256 return; 6257 6258 spin_lock_irqsave(&adev->ddev->event_lock, flags); 6259 vrr_params = new_crtc_state->vrr_params; 6260 6261 if (new_crtc_state->vrr_supported && 6262 config.min_refresh_in_uhz && 6263 config.max_refresh_in_uhz) { 6264 config.state = new_crtc_state->base.vrr_enabled ? 6265 VRR_STATE_ACTIVE_VARIABLE : 6266 VRR_STATE_INACTIVE; 6267 } else { 6268 config.state = VRR_STATE_UNSUPPORTED; 6269 } 6270 6271 mod_freesync_build_vrr_params(dm->freesync_module, 6272 new_stream, 6273 &config, &vrr_params); 6274 6275 new_crtc_state->freesync_timing_changed |= 6276 (memcmp(&new_crtc_state->vrr_params.adjust, 6277 &vrr_params.adjust, 6278 sizeof(vrr_params.adjust)) != 0); 6279 6280 new_crtc_state->vrr_params = vrr_params; 6281 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 6282 } 6283 6284 static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state, 6285 struct dm_crtc_state *new_state) 6286 { 6287 bool old_vrr_active = amdgpu_dm_vrr_active(old_state); 6288 bool new_vrr_active = amdgpu_dm_vrr_active(new_state); 6289 6290 if (!old_vrr_active && new_vrr_active) { 6291 /* Transition VRR inactive -> active: 6292 * While VRR is active, we must not disable vblank irq, as a 6293 * reenable after disable would compute bogus vblank/pflip 6294 * timestamps if it likely happened inside display front-porch. 6295 * 6296 * We also need vupdate irq for the actual core vblank handling 6297 * at end of vblank. 6298 */ 6299 dm_set_vupdate_irq(new_state->base.crtc, true); 6300 drm_crtc_vblank_get(new_state->base.crtc); 6301 DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n", 6302 __func__, new_state->base.crtc->base.id); 6303 } else if (old_vrr_active && !new_vrr_active) { 6304 /* Transition VRR active -> inactive: 6305 * Allow vblank irq disable again for fixed refresh rate. 6306 */ 6307 dm_set_vupdate_irq(new_state->base.crtc, false); 6308 drm_crtc_vblank_put(new_state->base.crtc); 6309 DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n", 6310 __func__, new_state->base.crtc->base.id); 6311 } 6312 } 6313 6314 static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state) 6315 { 6316 struct drm_plane *plane; 6317 struct drm_plane_state *old_plane_state, *new_plane_state __unused; 6318 int i; 6319 6320 /* 6321 * TODO: Make this per-stream so we don't issue redundant updates for 6322 * commits with multiple streams. 6323 */ 6324 for_each_oldnew_plane_in_state(state, plane, old_plane_state, 6325 new_plane_state, i) 6326 if (plane->type == DRM_PLANE_TYPE_CURSOR) 6327 handle_cursor_update(plane, old_plane_state); 6328 } 6329 6330 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, 6331 struct dc_state *dc_state, 6332 struct drm_device *dev, 6333 struct amdgpu_display_manager *dm, 6334 struct drm_crtc *pcrtc, 6335 bool wait_for_vblank) 6336 { 6337 uint32_t i; 6338 uint64_t timestamp_ns; 6339 struct drm_plane *plane; 6340 struct drm_plane_state *old_plane_state, *new_plane_state; 6341 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc); 6342 struct drm_crtc_state *new_pcrtc_state = 6343 drm_atomic_get_new_crtc_state(state, pcrtc); 6344 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state); 6345 struct dm_crtc_state *dm_old_crtc_state = 6346 to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc)); 6347 int planes_count = 0, vpos, hpos; 6348 long r; 6349 unsigned long flags; 6350 struct amdgpu_bo *abo; 6351 uint64_t tiling_flags; 6352 uint32_t target_vblank, last_flip_vblank; 6353 bool vrr_active = amdgpu_dm_vrr_active(acrtc_state); 6354 bool pflip_present = false; 6355 bool swizzle = true; 6356 struct { 6357 struct dc_surface_update surface_updates[MAX_SURFACES]; 6358 struct dc_plane_info plane_infos[MAX_SURFACES]; 6359 struct dc_scaling_info scaling_infos[MAX_SURFACES]; 6360 struct dc_flip_addrs flip_addrs[MAX_SURFACES]; 6361 struct dc_stream_update stream_update; 6362 } *bundle; 6363 6364 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL); 6365 6366 if (!bundle) { 6367 dm_error("Failed to allocate update bundle\n"); 6368 goto cleanup; 6369 } 6370 6371 /* 6372 * Disable the cursor first if we're disabling all the planes. 6373 * It'll remain on the screen after the planes are re-enabled 6374 * if we don't. 6375 */ 6376 if (acrtc_state->active_planes == 0) 6377 amdgpu_dm_commit_cursors(state); 6378 6379 /* update planes when needed */ 6380 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { 6381 struct drm_crtc *crtc = new_plane_state->crtc; 6382 struct drm_crtc_state *new_crtc_state; 6383 struct drm_framebuffer *fb = new_plane_state->fb; 6384 bool plane_needs_flip; 6385 struct dc_plane_state *dc_plane; 6386 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state); 6387 6388 /* Cursor plane is handled after stream updates */ 6389 if (plane->type == DRM_PLANE_TYPE_CURSOR) 6390 continue; 6391 6392 if (!fb || !crtc || pcrtc != crtc) 6393 continue; 6394 6395 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 6396 if (!new_crtc_state->active) 6397 continue; 6398 6399 dc_plane = dm_new_plane_state->dc_state; 6400 6401 if (dc_plane && !dc_plane->tiling_info.gfx9.swizzle) 6402 swizzle = false; 6403 6404 bundle->surface_updates[planes_count].surface = dc_plane; 6405 if (new_pcrtc_state->color_mgmt_changed) { 6406 bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction; 6407 bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func; 6408 } 6409 6410 fill_dc_scaling_info(new_plane_state, 6411 &bundle->scaling_infos[planes_count]); 6412 6413 bundle->surface_updates[planes_count].scaling_info = 6414 &bundle->scaling_infos[planes_count]; 6415 6416 plane_needs_flip = old_plane_state->fb && new_plane_state->fb; 6417 6418 pflip_present = pflip_present || plane_needs_flip; 6419 6420 if (!plane_needs_flip) { 6421 planes_count += 1; 6422 continue; 6423 } 6424 6425 abo = gem_to_amdgpu_bo(fb->obj[0]); 6426 6427 /* 6428 * Wait for all fences on this FB. Do limited wait to avoid 6429 * deadlock during GPU reset when this fence will not signal 6430 * but we hold reservation lock for the BO. 6431 */ 6432 r = dma_resv_wait_timeout_rcu(abo->tbo.base.resv, true, 6433 false, 6434 msecs_to_jiffies(5000)); 6435 if (unlikely(r <= 0)) 6436 DRM_ERROR("Waiting for fences timed out!"); 6437 6438 /* 6439 * TODO This might fail and hence better not used, wait 6440 * explicitly on fences instead 6441 * and in general should be called for 6442 * blocking commit to as per framework helpers 6443 */ 6444 r = amdgpu_bo_reserve(abo, true); 6445 if (unlikely(r != 0)) 6446 DRM_ERROR("failed to reserve buffer before flip\n"); 6447 6448 amdgpu_bo_get_tiling_flags(abo, &tiling_flags); 6449 6450 amdgpu_bo_unreserve(abo); 6451 6452 fill_dc_plane_info_and_addr( 6453 dm->adev, new_plane_state, tiling_flags, 6454 &bundle->plane_infos[planes_count], 6455 &bundle->flip_addrs[planes_count].address); 6456 6457 bundle->surface_updates[planes_count].plane_info = 6458 &bundle->plane_infos[planes_count]; 6459 6460 /* 6461 * Only allow immediate flips for fast updates that don't 6462 * change FB pitch, DCC state, rotation or mirroing. 6463 */ 6464 bundle->flip_addrs[planes_count].flip_immediate = 6465 crtc->state->async_flip && 6466 acrtc_state->update_type == UPDATE_TYPE_FAST; 6467 6468 timestamp_ns = ktime_get_ns(); 6469 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000); 6470 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count]; 6471 bundle->surface_updates[planes_count].surface = dc_plane; 6472 6473 if (!bundle->surface_updates[planes_count].surface) { 6474 DRM_ERROR("No surface for CRTC: id=%d\n", 6475 acrtc_attach->crtc_id); 6476 continue; 6477 } 6478 6479 if (plane == pcrtc->primary) 6480 update_freesync_state_on_stream( 6481 dm, 6482 acrtc_state, 6483 acrtc_state->stream, 6484 dc_plane, 6485 bundle->flip_addrs[planes_count].flip_timestamp_in_us); 6486 6487 DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x\n", 6488 __func__, 6489 bundle->flip_addrs[planes_count].address.grph.addr.high_part, 6490 bundle->flip_addrs[planes_count].address.grph.addr.low_part); 6491 6492 planes_count += 1; 6493 6494 } 6495 6496 if (pflip_present) { 6497 if (!vrr_active) { 6498 /* Use old throttling in non-vrr fixed refresh rate mode 6499 * to keep flip scheduling based on target vblank counts 6500 * working in a backwards compatible way, e.g., for 6501 * clients using the GLX_OML_sync_control extension or 6502 * DRI3/Present extension with defined target_msc. 6503 */ 6504 last_flip_vblank = amdgpu_get_vblank_counter_kms(dm->ddev, acrtc_attach->crtc_id); 6505 } 6506 else { 6507 /* For variable refresh rate mode only: 6508 * Get vblank of last completed flip to avoid > 1 vrr 6509 * flips per video frame by use of throttling, but allow 6510 * flip programming anywhere in the possibly large 6511 * variable vrr vblank interval for fine-grained flip 6512 * timing control and more opportunity to avoid stutter 6513 * on late submission of flips. 6514 */ 6515 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 6516 last_flip_vblank = acrtc_attach->last_flip_vblank; 6517 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 6518 } 6519 6520 target_vblank = last_flip_vblank + wait_for_vblank; 6521 6522 /* 6523 * Wait until we're out of the vertical blank period before the one 6524 * targeted by the flip 6525 */ 6526 while ((acrtc_attach->enabled && 6527 (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id, 6528 0, &vpos, &hpos, NULL, 6529 NULL, &pcrtc->hwmode) 6530 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) == 6531 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) && 6532 (int)(target_vblank - 6533 amdgpu_get_vblank_counter_kms(dm->ddev, acrtc_attach->crtc_id)) > 0)) { 6534 usleep_range(1000, 1100); 6535 } 6536 6537 if (acrtc_attach->base.state->event) { 6538 drm_crtc_vblank_get(pcrtc); 6539 6540 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 6541 6542 WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE); 6543 prepare_flip_isr(acrtc_attach); 6544 6545 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 6546 } 6547 6548 if (acrtc_state->stream) { 6549 if (acrtc_state->freesync_vrr_info_changed) 6550 bundle->stream_update.vrr_infopacket = 6551 &acrtc_state->stream->vrr_infopacket; 6552 } 6553 } 6554 6555 /* Update the planes if changed or disable if we don't have any. */ 6556 if ((planes_count || acrtc_state->active_planes == 0) && 6557 acrtc_state->stream) { 6558 bundle->stream_update.stream = acrtc_state->stream; 6559 if (new_pcrtc_state->mode_changed) { 6560 bundle->stream_update.src = acrtc_state->stream->src; 6561 bundle->stream_update.dst = acrtc_state->stream->dst; 6562 } 6563 6564 if (new_pcrtc_state->color_mgmt_changed) { 6565 /* 6566 * TODO: This isn't fully correct since we've actually 6567 * already modified the stream in place. 6568 */ 6569 bundle->stream_update.gamut_remap = 6570 &acrtc_state->stream->gamut_remap_matrix; 6571 bundle->stream_update.output_csc_transform = 6572 &acrtc_state->stream->csc_color_matrix; 6573 bundle->stream_update.out_transfer_func = 6574 acrtc_state->stream->out_transfer_func; 6575 } 6576 6577 acrtc_state->stream->abm_level = acrtc_state->abm_level; 6578 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level) 6579 bundle->stream_update.abm_level = &acrtc_state->abm_level; 6580 6581 /* 6582 * If FreeSync state on the stream has changed then we need to 6583 * re-adjust the min/max bounds now that DC doesn't handle this 6584 * as part of commit. 6585 */ 6586 if (amdgpu_dm_vrr_active(dm_old_crtc_state) != 6587 amdgpu_dm_vrr_active(acrtc_state)) { 6588 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 6589 dc_stream_adjust_vmin_vmax( 6590 dm->dc, acrtc_state->stream, 6591 &acrtc_state->vrr_params.adjust); 6592 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 6593 } 6594 mutex_lock(&dm->dc_lock); 6595 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) && 6596 acrtc_state->stream->link->psr_allow_active) 6597 amdgpu_dm_psr_disable(acrtc_state->stream); 6598 6599 dc_commit_updates_for_stream(dm->dc, 6600 bundle->surface_updates, 6601 planes_count, 6602 acrtc_state->stream, 6603 &bundle->stream_update, 6604 dc_state); 6605 6606 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) && 6607 acrtc_state->stream->psr_version && 6608 !acrtc_state->stream->link->psr_feature_enabled) 6609 amdgpu_dm_link_setup_psr(acrtc_state->stream); 6610 else if ((acrtc_state->update_type == UPDATE_TYPE_FAST) && 6611 acrtc_state->stream->link->psr_feature_enabled && 6612 !acrtc_state->stream->link->psr_allow_active && 6613 swizzle) { 6614 amdgpu_dm_psr_enable(acrtc_state->stream); 6615 } 6616 6617 mutex_unlock(&dm->dc_lock); 6618 } 6619 6620 /* 6621 * Update cursor state *after* programming all the planes. 6622 * This avoids redundant programming in the case where we're going 6623 * to be disabling a single plane - those pipes are being disabled. 6624 */ 6625 if (acrtc_state->active_planes) 6626 amdgpu_dm_commit_cursors(state); 6627 6628 cleanup: 6629 kfree(bundle); 6630 } 6631 6632 static void amdgpu_dm_commit_audio(struct drm_device *dev, 6633 struct drm_atomic_state *state) 6634 { 6635 struct amdgpu_device *adev = dev->dev_private; 6636 struct amdgpu_dm_connector *aconnector; 6637 struct drm_connector *connector; 6638 struct drm_connector_state *old_con_state, *new_con_state; 6639 struct drm_crtc_state *new_crtc_state; 6640 struct dm_crtc_state *new_dm_crtc_state; 6641 const struct dc_stream_status *status; 6642 int i, inst; 6643 6644 /* Notify device removals. */ 6645 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 6646 if (old_con_state->crtc != new_con_state->crtc) { 6647 /* CRTC changes require notification. */ 6648 goto notify; 6649 } 6650 6651 if (!new_con_state->crtc) 6652 continue; 6653 6654 new_crtc_state = drm_atomic_get_new_crtc_state( 6655 state, new_con_state->crtc); 6656 6657 if (!new_crtc_state) 6658 continue; 6659 6660 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 6661 continue; 6662 6663 notify: 6664 aconnector = to_amdgpu_dm_connector(connector); 6665 6666 mutex_lock(&adev->dm.audio_lock); 6667 inst = aconnector->audio_inst; 6668 aconnector->audio_inst = -1; 6669 mutex_unlock(&adev->dm.audio_lock); 6670 6671 amdgpu_dm_audio_eld_notify(adev, inst); 6672 } 6673 6674 /* Notify audio device additions. */ 6675 for_each_new_connector_in_state(state, connector, new_con_state, i) { 6676 if (!new_con_state->crtc) 6677 continue; 6678 6679 new_crtc_state = drm_atomic_get_new_crtc_state( 6680 state, new_con_state->crtc); 6681 6682 if (!new_crtc_state) 6683 continue; 6684 6685 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 6686 continue; 6687 6688 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state); 6689 if (!new_dm_crtc_state->stream) 6690 continue; 6691 6692 status = dc_stream_get_status(new_dm_crtc_state->stream); 6693 if (!status) 6694 continue; 6695 6696 aconnector = to_amdgpu_dm_connector(connector); 6697 6698 mutex_lock(&adev->dm.audio_lock); 6699 inst = status->audio_inst; 6700 aconnector->audio_inst = inst; 6701 mutex_unlock(&adev->dm.audio_lock); 6702 6703 amdgpu_dm_audio_eld_notify(adev, inst); 6704 } 6705 } 6706 6707 /* 6708 * Enable interrupts on CRTCs that are newly active, undergone 6709 * a modeset, or have active planes again. 6710 * 6711 * Done in two passes, based on the for_modeset flag: 6712 * Pass 1: For CRTCs going through modeset 6713 * Pass 2: For CRTCs going from 0 to n active planes 6714 * 6715 * Interrupts can only be enabled after the planes are programmed, 6716 * so this requires a two-pass approach since we don't want to 6717 * just defer the interrupts until after commit planes every time. 6718 */ 6719 static void amdgpu_dm_enable_crtc_interrupts(struct drm_device *dev, 6720 struct drm_atomic_state *state, 6721 bool for_modeset) 6722 { 6723 struct amdgpu_device *adev = dev->dev_private; 6724 struct drm_crtc *crtc; 6725 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 6726 int i; 6727 #ifdef CONFIG_DEBUG_FS 6728 enum amdgpu_dm_pipe_crc_source source; 6729 #endif 6730 6731 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, 6732 new_crtc_state, i) { 6733 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 6734 struct dm_crtc_state *dm_new_crtc_state = 6735 to_dm_crtc_state(new_crtc_state); 6736 struct dm_crtc_state *dm_old_crtc_state = 6737 to_dm_crtc_state(old_crtc_state); 6738 bool modeset = drm_atomic_crtc_needs_modeset(new_crtc_state); 6739 bool run_pass; 6740 6741 run_pass = (for_modeset && modeset) || 6742 (!for_modeset && !modeset && 6743 !dm_old_crtc_state->interrupts_enabled); 6744 6745 if (!run_pass) 6746 continue; 6747 6748 if (!dm_new_crtc_state->interrupts_enabled) 6749 continue; 6750 6751 manage_dm_interrupts(adev, acrtc, true); 6752 6753 #ifdef CONFIG_DEBUG_FS 6754 /* The stream has changed so CRC capture needs to re-enabled. */ 6755 source = dm_new_crtc_state->crc_src; 6756 if (amdgpu_dm_is_valid_crc_source(source)) { 6757 amdgpu_dm_crtc_configure_crc_source( 6758 crtc, dm_new_crtc_state, 6759 dm_new_crtc_state->crc_src); 6760 } 6761 #endif 6762 } 6763 } 6764 6765 /* 6766 * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC 6767 * @crtc_state: the DRM CRTC state 6768 * @stream_state: the DC stream state. 6769 * 6770 * Copy the mirrored transient state flags from DRM, to DC. It is used to bring 6771 * a dc_stream_state's flags in sync with a drm_crtc_state's flags. 6772 */ 6773 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state, 6774 struct dc_stream_state *stream_state) 6775 { 6776 stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state); 6777 } 6778 6779 static int amdgpu_dm_atomic_commit(struct drm_device *dev, 6780 struct drm_atomic_state *state, 6781 bool nonblock) 6782 { 6783 struct drm_crtc *crtc; 6784 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 6785 struct amdgpu_device *adev = dev->dev_private; 6786 int i; 6787 6788 /* 6789 * We evade vblank and pflip interrupts on CRTCs that are undergoing 6790 * a modeset, being disabled, or have no active planes. 6791 * 6792 * It's done in atomic commit rather than commit tail for now since 6793 * some of these interrupt handlers access the current CRTC state and 6794 * potentially the stream pointer itself. 6795 * 6796 * Since the atomic state is swapped within atomic commit and not within 6797 * commit tail this would leave to new state (that hasn't been committed yet) 6798 * being accesssed from within the handlers. 6799 * 6800 * TODO: Fix this so we can do this in commit tail and not have to block 6801 * in atomic check. 6802 */ 6803 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 6804 struct dm_crtc_state *dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 6805 struct dm_crtc_state *dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 6806 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 6807 6808 if (dm_old_crtc_state->interrupts_enabled && 6809 (!dm_new_crtc_state->interrupts_enabled || 6810 drm_atomic_crtc_needs_modeset(new_crtc_state))) 6811 manage_dm_interrupts(adev, acrtc, false); 6812 } 6813 /* 6814 * Add check here for SoC's that support hardware cursor plane, to 6815 * unset legacy_cursor_update 6816 */ 6817 6818 return drm_atomic_helper_commit(dev, state, nonblock); 6819 6820 /*TODO Handle EINTR, reenable IRQ*/ 6821 } 6822 6823 /** 6824 * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation. 6825 * @state: The atomic state to commit 6826 * 6827 * This will tell DC to commit the constructed DC state from atomic_check, 6828 * programming the hardware. Any failures here implies a hardware failure, since 6829 * atomic check should have filtered anything non-kosher. 6830 */ 6831 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) 6832 { 6833 struct drm_device *dev = state->dev; 6834 struct amdgpu_device *adev = dev->dev_private; 6835 struct amdgpu_display_manager *dm = &adev->dm; 6836 struct dm_atomic_state *dm_state; 6837 struct dc_state *dc_state = NULL, *dc_state_temp = NULL; 6838 uint32_t i, j; 6839 struct drm_crtc *crtc; 6840 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 6841 unsigned long flags; 6842 bool wait_for_vblank = true; 6843 struct drm_connector *connector; 6844 struct drm_connector_state *old_con_state, *new_con_state; 6845 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 6846 int crtc_disable_count = 0; 6847 6848 drm_atomic_helper_update_legacy_modeset_state(dev, state); 6849 6850 dm_state = dm_atomic_get_new_state(state); 6851 if (dm_state && dm_state->context) { 6852 dc_state = dm_state->context; 6853 } else { 6854 /* No state changes, retain current state. */ 6855 dc_state_temp = dc_create_state(dm->dc); 6856 ASSERT(dc_state_temp); 6857 dc_state = dc_state_temp; 6858 dc_resource_state_copy_construct_current(dm->dc, dc_state); 6859 } 6860 6861 /* update changed items */ 6862 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 6863 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 6864 6865 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 6866 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 6867 6868 DRM_DEBUG_DRIVER( 6869 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, " 6870 "planes_changed:%d, mode_changed:%d,active_changed:%d," 6871 "connectors_changed:%d\n", 6872 acrtc->crtc_id, 6873 new_crtc_state->enable, 6874 new_crtc_state->active, 6875 new_crtc_state->planes_changed, 6876 new_crtc_state->mode_changed, 6877 new_crtc_state->active_changed, 6878 new_crtc_state->connectors_changed); 6879 6880 /* Copy all transient state flags into dc state */ 6881 if (dm_new_crtc_state->stream) { 6882 amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base, 6883 dm_new_crtc_state->stream); 6884 } 6885 6886 /* handles headless hotplug case, updating new_state and 6887 * aconnector as needed 6888 */ 6889 6890 if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) { 6891 6892 DRM_DEBUG_DRIVER("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc); 6893 6894 if (!dm_new_crtc_state->stream) { 6895 /* 6896 * this could happen because of issues with 6897 * userspace notifications delivery. 6898 * In this case userspace tries to set mode on 6899 * display which is disconnected in fact. 6900 * dc_sink is NULL in this case on aconnector. 6901 * We expect reset mode will come soon. 6902 * 6903 * This can also happen when unplug is done 6904 * during resume sequence ended 6905 * 6906 * In this case, we want to pretend we still 6907 * have a sink to keep the pipe running so that 6908 * hw state is consistent with the sw state 6909 */ 6910 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n", 6911 __func__, acrtc->base.base.id); 6912 continue; 6913 } 6914 6915 if (dm_old_crtc_state->stream) 6916 remove_stream(adev, acrtc, dm_old_crtc_state->stream); 6917 6918 pm_runtime_get_noresume(dev->dev); 6919 6920 acrtc->enabled = true; 6921 acrtc->hw_mode = new_crtc_state->mode; 6922 crtc->hwmode = new_crtc_state->mode; 6923 } else if (modereset_required(new_crtc_state)) { 6924 DRM_DEBUG_DRIVER("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc); 6925 /* i.e. reset mode */ 6926 if (dm_old_crtc_state->stream) { 6927 if (dm_old_crtc_state->stream->link->psr_allow_active) 6928 amdgpu_dm_psr_disable(dm_old_crtc_state->stream); 6929 6930 remove_stream(adev, acrtc, dm_old_crtc_state->stream); 6931 } 6932 } 6933 } /* for_each_crtc_in_state() */ 6934 6935 if (dc_state) { 6936 dm_enable_per_frame_crtc_master_sync(dc_state); 6937 mutex_lock(&dm->dc_lock); 6938 WARN_ON(!dc_commit_state(dm->dc, dc_state)); 6939 mutex_unlock(&dm->dc_lock); 6940 } 6941 6942 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 6943 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 6944 6945 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 6946 6947 if (dm_new_crtc_state->stream != NULL) { 6948 const struct dc_stream_status *status = 6949 dc_stream_get_status(dm_new_crtc_state->stream); 6950 6951 if (!status) 6952 status = dc_stream_get_status_from_state(dc_state, 6953 dm_new_crtc_state->stream); 6954 6955 if (!status) 6956 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc); 6957 else 6958 acrtc->otg_inst = status->primary_otg_inst; 6959 } 6960 } 6961 #ifdef CONFIG_DRM_AMD_DC_HDCP 6962 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 6963 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 6964 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 6965 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 6966 6967 new_crtc_state = NULL; 6968 6969 if (acrtc) 6970 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 6971 6972 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 6973 6974 if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL && 6975 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) { 6976 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index); 6977 new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 6978 continue; 6979 } 6980 6981 if (is_content_protection_different(new_con_state, old_con_state, connector, adev->dm.hdcp_workqueue)) 6982 hdcp_update_display( 6983 adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector, 6984 new_con_state->hdcp_content_type, 6985 new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED ? true 6986 : false); 6987 } 6988 #endif 6989 6990 /* Handle connector state changes */ 6991 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 6992 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 6993 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 6994 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 6995 struct dc_surface_update dummy_updates[MAX_SURFACES]; 6996 struct dc_stream_update stream_update; 6997 struct dc_info_packet hdr_packet; 6998 struct dc_stream_status *status = NULL; 6999 bool abm_changed, hdr_changed, scaling_changed; 7000 7001 memset(&dummy_updates, 0, sizeof(dummy_updates)); 7002 memset(&stream_update, 0, sizeof(stream_update)); 7003 7004 if (acrtc) { 7005 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 7006 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); 7007 } 7008 7009 /* Skip any modesets/resets */ 7010 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state)) 7011 continue; 7012 7013 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 7014 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 7015 7016 scaling_changed = is_scaling_state_different(dm_new_con_state, 7017 dm_old_con_state); 7018 7019 abm_changed = dm_new_crtc_state->abm_level != 7020 dm_old_crtc_state->abm_level; 7021 7022 hdr_changed = 7023 is_hdr_metadata_different(old_con_state, new_con_state); 7024 7025 if (!scaling_changed && !abm_changed && !hdr_changed) 7026 continue; 7027 7028 stream_update.stream = dm_new_crtc_state->stream; 7029 if (scaling_changed) { 7030 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode, 7031 dm_new_con_state, dm_new_crtc_state->stream); 7032 7033 stream_update.src = dm_new_crtc_state->stream->src; 7034 stream_update.dst = dm_new_crtc_state->stream->dst; 7035 } 7036 7037 if (abm_changed) { 7038 dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level; 7039 7040 stream_update.abm_level = &dm_new_crtc_state->abm_level; 7041 } 7042 7043 if (hdr_changed) { 7044 fill_hdr_info_packet(new_con_state, &hdr_packet); 7045 stream_update.hdr_static_metadata = &hdr_packet; 7046 } 7047 7048 status = dc_stream_get_status(dm_new_crtc_state->stream); 7049 WARN_ON(!status); 7050 WARN_ON(!status->plane_count); 7051 7052 /* 7053 * TODO: DC refuses to perform stream updates without a dc_surface_update. 7054 * Here we create an empty update on each plane. 7055 * To fix this, DC should permit updating only stream properties. 7056 */ 7057 for (j = 0; j < status->plane_count; j++) 7058 dummy_updates[j].surface = status->plane_states[0]; 7059 7060 7061 mutex_lock(&dm->dc_lock); 7062 dc_commit_updates_for_stream(dm->dc, 7063 dummy_updates, 7064 status->plane_count, 7065 dm_new_crtc_state->stream, 7066 &stream_update, 7067 dc_state); 7068 mutex_unlock(&dm->dc_lock); 7069 } 7070 7071 /* Count number of newly disabled CRTCs for dropping PM refs later. */ 7072 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, 7073 new_crtc_state, i) { 7074 if (old_crtc_state->active && !new_crtc_state->active) 7075 crtc_disable_count++; 7076 7077 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 7078 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 7079 7080 /* Update freesync active state. */ 7081 pre_update_freesync_state_on_stream(dm, dm_new_crtc_state); 7082 7083 /* Handle vrr on->off / off->on transitions */ 7084 amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, 7085 dm_new_crtc_state); 7086 } 7087 7088 /* Enable interrupts for CRTCs going through a modeset. */ 7089 amdgpu_dm_enable_crtc_interrupts(dev, state, true); 7090 7091 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) 7092 if (new_crtc_state->async_flip) 7093 wait_for_vblank = false; 7094 7095 /* update planes when needed per crtc*/ 7096 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) { 7097 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 7098 7099 if (dm_new_crtc_state->stream) 7100 amdgpu_dm_commit_planes(state, dc_state, dev, 7101 dm, crtc, wait_for_vblank); 7102 } 7103 7104 /* Enable interrupts for CRTCs going from 0 to n active planes. */ 7105 amdgpu_dm_enable_crtc_interrupts(dev, state, false); 7106 7107 /* Update audio instances for each connector. */ 7108 amdgpu_dm_commit_audio(dev, state); 7109 7110 /* 7111 * send vblank event on all events not handled in flip and 7112 * mark consumed event for drm_atomic_helper_commit_hw_done 7113 */ 7114 spin_lock_irqsave(&adev->ddev->event_lock, flags); 7115 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 7116 7117 if (new_crtc_state->event) 7118 drm_send_event_locked(dev, &new_crtc_state->event->base); 7119 7120 new_crtc_state->event = NULL; 7121 } 7122 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 7123 7124 /* Signal HW programming completion */ 7125 drm_atomic_helper_commit_hw_done(state); 7126 7127 if (wait_for_vblank) 7128 drm_atomic_helper_wait_for_flip_done(dev, state); 7129 7130 drm_atomic_helper_cleanup_planes(dev, state); 7131 7132 /* 7133 * Finally, drop a runtime PM reference for each newly disabled CRTC, 7134 * so we can put the GPU into runtime suspend if we're not driving any 7135 * displays anymore 7136 */ 7137 for (i = 0; i < crtc_disable_count; i++) 7138 pm_runtime_put_autosuspend(dev->dev); 7139 pm_runtime_mark_last_busy(dev->dev); 7140 7141 if (dc_state_temp) 7142 dc_release_state(dc_state_temp); 7143 } 7144 7145 7146 static int dm_force_atomic_commit(struct drm_connector *connector) 7147 { 7148 int ret = 0; 7149 struct drm_device *ddev = connector->dev; 7150 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev); 7151 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); 7152 struct drm_plane *plane = disconnected_acrtc->base.primary; 7153 struct drm_connector_state *conn_state; 7154 struct drm_crtc_state *crtc_state; 7155 struct drm_plane_state *plane_state; 7156 7157 if (!state) 7158 return -ENOMEM; 7159 7160 state->acquire_ctx = ddev->mode_config.acquire_ctx; 7161 7162 /* Construct an atomic state to restore previous display setting */ 7163 7164 /* 7165 * Attach connectors to drm_atomic_state 7166 */ 7167 conn_state = drm_atomic_get_connector_state(state, connector); 7168 7169 ret = PTR_ERR_OR_ZERO(conn_state); 7170 if (ret) 7171 goto err; 7172 7173 /* Attach crtc to drm_atomic_state*/ 7174 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base); 7175 7176 ret = PTR_ERR_OR_ZERO(crtc_state); 7177 if (ret) 7178 goto err; 7179 7180 /* force a restore */ 7181 crtc_state->mode_changed = true; 7182 7183 /* Attach plane to drm_atomic_state */ 7184 plane_state = drm_atomic_get_plane_state(state, plane); 7185 7186 ret = PTR_ERR_OR_ZERO(plane_state); 7187 if (ret) 7188 goto err; 7189 7190 7191 /* Call commit internally with the state we just constructed */ 7192 ret = drm_atomic_commit(state); 7193 if (!ret) 7194 return 0; 7195 7196 err: 7197 DRM_ERROR("Restoring old state failed with %i\n", ret); 7198 drm_atomic_state_put(state); 7199 7200 return ret; 7201 } 7202 7203 /* 7204 * This function handles all cases when set mode does not come upon hotplug. 7205 * This includes when a display is unplugged then plugged back into the 7206 * same port and when running without usermode desktop manager supprot 7207 */ 7208 void dm_restore_drm_connector_state(struct drm_device *dev, 7209 struct drm_connector *connector) 7210 { 7211 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 7212 struct amdgpu_crtc *disconnected_acrtc; 7213 struct dm_crtc_state *acrtc_state; 7214 7215 if (!aconnector->dc_sink || !connector->state || !connector->encoder) 7216 return; 7217 7218 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); 7219 if (!disconnected_acrtc) 7220 return; 7221 7222 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state); 7223 if (!acrtc_state->stream) 7224 return; 7225 7226 /* 7227 * If the previous sink is not released and different from the current, 7228 * we deduce we are in a state where we can not rely on usermode call 7229 * to turn on the display, so we do it here 7230 */ 7231 if (acrtc_state->stream->sink != aconnector->dc_sink) 7232 dm_force_atomic_commit(&aconnector->base); 7233 } 7234 7235 /* 7236 * Grabs all modesetting locks to serialize against any blocking commits, 7237 * Waits for completion of all non blocking commits. 7238 */ 7239 static int do_aquire_global_lock(struct drm_device *dev, 7240 struct drm_atomic_state *state) 7241 { 7242 struct drm_crtc *crtc; 7243 struct drm_crtc_commit *commit; 7244 long ret; 7245 7246 /* 7247 * Adding all modeset locks to aquire_ctx will 7248 * ensure that when the framework release it the 7249 * extra locks we are locking here will get released to 7250 */ 7251 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx); 7252 if (ret) 7253 return ret; 7254 7255 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 7256 spin_lock(&crtc->commit_lock); 7257 commit = list_first_entry_or_null(&crtc->commit_list, 7258 struct drm_crtc_commit, commit_entry); 7259 if (commit) 7260 drm_crtc_commit_get(commit); 7261 spin_unlock(&crtc->commit_lock); 7262 7263 if (!commit) 7264 continue; 7265 7266 /* 7267 * Make sure all pending HW programming completed and 7268 * page flips done 7269 */ 7270 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ); 7271 7272 if (ret > 0) 7273 ret = wait_for_completion_interruptible_timeout( 7274 &commit->flip_done, 10*HZ); 7275 7276 if (ret == 0) 7277 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done " 7278 "timed out\n", crtc->base.id, crtc->name); 7279 7280 drm_crtc_commit_put(commit); 7281 } 7282 7283 return ret < 0 ? ret : 0; 7284 } 7285 7286 static void get_freesync_config_for_crtc( 7287 struct dm_crtc_state *new_crtc_state, 7288 struct dm_connector_state *new_con_state) 7289 { 7290 struct mod_freesync_config config = {0}; 7291 struct amdgpu_dm_connector *aconnector = 7292 to_amdgpu_dm_connector(new_con_state->base.connector); 7293 struct drm_display_mode *mode = &new_crtc_state->base.mode; 7294 int vrefresh = drm_mode_vrefresh(mode); 7295 7296 new_crtc_state->vrr_supported = new_con_state->freesync_capable && 7297 vrefresh >= aconnector->min_vfreq && 7298 vrefresh <= aconnector->max_vfreq; 7299 7300 if (new_crtc_state->vrr_supported) { 7301 new_crtc_state->stream->ignore_msa_timing_param = true; 7302 config.state = new_crtc_state->base.vrr_enabled ? 7303 VRR_STATE_ACTIVE_VARIABLE : 7304 VRR_STATE_INACTIVE; 7305 config.min_refresh_in_uhz = 7306 aconnector->min_vfreq * 1000000; 7307 config.max_refresh_in_uhz = 7308 aconnector->max_vfreq * 1000000; 7309 config.vsif_supported = true; 7310 config.btr = true; 7311 } 7312 7313 new_crtc_state->freesync_config = config; 7314 } 7315 7316 static void reset_freesync_config_for_crtc( 7317 struct dm_crtc_state *new_crtc_state) 7318 { 7319 new_crtc_state->vrr_supported = false; 7320 7321 memset(&new_crtc_state->vrr_params, 0, 7322 sizeof(new_crtc_state->vrr_params)); 7323 memset(&new_crtc_state->vrr_infopacket, 0, 7324 sizeof(new_crtc_state->vrr_infopacket)); 7325 } 7326 7327 static int dm_update_crtc_state(struct amdgpu_display_manager *dm, 7328 struct drm_atomic_state *state, 7329 struct drm_crtc *crtc, 7330 struct drm_crtc_state *old_crtc_state, 7331 struct drm_crtc_state *new_crtc_state, 7332 bool enable, 7333 bool *lock_and_validation_needed) 7334 { 7335 struct dm_atomic_state *dm_state = NULL; 7336 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 7337 struct dc_stream_state *new_stream; 7338 int ret = 0; 7339 7340 /* 7341 * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set 7342 * update changed items 7343 */ 7344 struct amdgpu_crtc *acrtc = NULL; 7345 struct amdgpu_dm_connector *aconnector = NULL; 7346 struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL; 7347 struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL; 7348 7349 new_stream = NULL; 7350 7351 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 7352 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 7353 acrtc = to_amdgpu_crtc(crtc); 7354 aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc); 7355 7356 /* TODO This hack should go away */ 7357 if (aconnector && enable) { 7358 /* Make sure fake sink is created in plug-in scenario */ 7359 drm_new_conn_state = drm_atomic_get_new_connector_state(state, 7360 &aconnector->base); 7361 drm_old_conn_state = drm_atomic_get_old_connector_state(state, 7362 &aconnector->base); 7363 7364 if (IS_ERR(drm_new_conn_state)) { 7365 ret = PTR_ERR_OR_ZERO(drm_new_conn_state); 7366 goto fail; 7367 } 7368 7369 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state); 7370 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state); 7371 7372 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 7373 goto skip_modeset; 7374 7375 new_stream = create_stream_for_sink(aconnector, 7376 &new_crtc_state->mode, 7377 dm_new_conn_state, 7378 dm_old_crtc_state->stream); 7379 7380 /* 7381 * we can have no stream on ACTION_SET if a display 7382 * was disconnected during S3, in this case it is not an 7383 * error, the OS will be updated after detection, and 7384 * will do the right thing on next atomic commit 7385 */ 7386 7387 if (!new_stream) { 7388 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n", 7389 __func__, acrtc->base.base.id); 7390 ret = -ENOMEM; 7391 goto fail; 7392 } 7393 7394 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level; 7395 7396 ret = fill_hdr_info_packet(drm_new_conn_state, 7397 &new_stream->hdr_static_metadata); 7398 if (ret) 7399 goto fail; 7400 7401 /* 7402 * If we already removed the old stream from the context 7403 * (and set the new stream to NULL) then we can't reuse 7404 * the old stream even if the stream and scaling are unchanged. 7405 * We'll hit the BUG_ON and black screen. 7406 * 7407 * TODO: Refactor this function to allow this check to work 7408 * in all conditions. 7409 */ 7410 if (dm_new_crtc_state->stream && 7411 dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) && 7412 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) { 7413 new_crtc_state->mode_changed = false; 7414 DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d", 7415 new_crtc_state->mode_changed); 7416 } 7417 } 7418 7419 /* mode_changed flag may get updated above, need to check again */ 7420 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 7421 goto skip_modeset; 7422 7423 DRM_DEBUG_DRIVER( 7424 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, " 7425 "planes_changed:%d, mode_changed:%d,active_changed:%d," 7426 "connectors_changed:%d\n", 7427 acrtc->crtc_id, 7428 new_crtc_state->enable, 7429 new_crtc_state->active, 7430 new_crtc_state->planes_changed, 7431 new_crtc_state->mode_changed, 7432 new_crtc_state->active_changed, 7433 new_crtc_state->connectors_changed); 7434 7435 /* Remove stream for any changed/disabled CRTC */ 7436 if (!enable) { 7437 7438 if (!dm_old_crtc_state->stream) 7439 goto skip_modeset; 7440 7441 ret = dm_atomic_get_state(state, &dm_state); 7442 if (ret) 7443 goto fail; 7444 7445 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n", 7446 crtc->base.id); 7447 7448 /* i.e. reset mode */ 7449 if (dc_remove_stream_from_ctx( 7450 dm->dc, 7451 dm_state->context, 7452 dm_old_crtc_state->stream) != DC_OK) { 7453 ret = -EINVAL; 7454 goto fail; 7455 } 7456 7457 dc_stream_release(dm_old_crtc_state->stream); 7458 dm_new_crtc_state->stream = NULL; 7459 7460 reset_freesync_config_for_crtc(dm_new_crtc_state); 7461 7462 *lock_and_validation_needed = true; 7463 7464 } else {/* Add stream for any updated/enabled CRTC */ 7465 /* 7466 * Quick fix to prevent NULL pointer on new_stream when 7467 * added MST connectors not found in existing crtc_state in the chained mode 7468 * TODO: need to dig out the root cause of that 7469 */ 7470 if (!aconnector || (!aconnector->dc_sink && aconnector->mst_port)) 7471 goto skip_modeset; 7472 7473 if (modereset_required(new_crtc_state)) 7474 goto skip_modeset; 7475 7476 if (modeset_required(new_crtc_state, new_stream, 7477 dm_old_crtc_state->stream)) { 7478 7479 WARN_ON(dm_new_crtc_state->stream); 7480 7481 ret = dm_atomic_get_state(state, &dm_state); 7482 if (ret) 7483 goto fail; 7484 7485 dm_new_crtc_state->stream = new_stream; 7486 7487 dc_stream_retain(new_stream); 7488 7489 DRM_DEBUG_DRIVER("Enabling DRM crtc: %d\n", 7490 crtc->base.id); 7491 7492 if (dc_add_stream_to_ctx( 7493 dm->dc, 7494 dm_state->context, 7495 dm_new_crtc_state->stream) != DC_OK) { 7496 ret = -EINVAL; 7497 goto fail; 7498 } 7499 7500 *lock_and_validation_needed = true; 7501 } 7502 } 7503 7504 skip_modeset: 7505 /* Release extra reference */ 7506 if (new_stream) 7507 dc_stream_release(new_stream); 7508 7509 /* 7510 * We want to do dc stream updates that do not require a 7511 * full modeset below. 7512 */ 7513 if (!(enable && aconnector && new_crtc_state->enable && 7514 new_crtc_state->active)) 7515 return 0; 7516 /* 7517 * Given above conditions, the dc state cannot be NULL because: 7518 * 1. We're in the process of enabling CRTCs (just been added 7519 * to the dc context, or already is on the context) 7520 * 2. Has a valid connector attached, and 7521 * 3. Is currently active and enabled. 7522 * => The dc stream state currently exists. 7523 */ 7524 BUG_ON(dm_new_crtc_state->stream == NULL); 7525 7526 /* Scaling or underscan settings */ 7527 if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state)) 7528 update_stream_scaling_settings( 7529 &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream); 7530 7531 /* ABM settings */ 7532 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level; 7533 7534 /* 7535 * Color management settings. We also update color properties 7536 * when a modeset is needed, to ensure it gets reprogrammed. 7537 */ 7538 if (dm_new_crtc_state->base.color_mgmt_changed || 7539 drm_atomic_crtc_needs_modeset(new_crtc_state)) { 7540 ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state); 7541 if (ret) 7542 goto fail; 7543 } 7544 7545 /* Update Freesync settings. */ 7546 get_freesync_config_for_crtc(dm_new_crtc_state, 7547 dm_new_conn_state); 7548 7549 return ret; 7550 7551 fail: 7552 if (new_stream) 7553 dc_stream_release(new_stream); 7554 return ret; 7555 } 7556 7557 static bool should_reset_plane(struct drm_atomic_state *state, 7558 struct drm_plane *plane, 7559 struct drm_plane_state *old_plane_state, 7560 struct drm_plane_state *new_plane_state) 7561 { 7562 struct drm_plane *other; 7563 struct drm_plane_state *old_other_state, *new_other_state; 7564 struct drm_crtc_state *new_crtc_state; 7565 int i; 7566 7567 /* 7568 * TODO: Remove this hack once the checks below are sufficient 7569 * enough to determine when we need to reset all the planes on 7570 * the stream. 7571 */ 7572 if (state->allow_modeset) 7573 return true; 7574 7575 /* Exit early if we know that we're adding or removing the plane. */ 7576 if (old_plane_state->crtc != new_plane_state->crtc) 7577 return true; 7578 7579 /* old crtc == new_crtc == NULL, plane not in context. */ 7580 if (!new_plane_state->crtc) 7581 return false; 7582 7583 new_crtc_state = 7584 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc); 7585 7586 if (!new_crtc_state) 7587 return true; 7588 7589 /* CRTC Degamma changes currently require us to recreate planes. */ 7590 if (new_crtc_state->color_mgmt_changed) 7591 return true; 7592 7593 if (drm_atomic_crtc_needs_modeset(new_crtc_state)) 7594 return true; 7595 7596 /* 7597 * If there are any new primary or overlay planes being added or 7598 * removed then the z-order can potentially change. To ensure 7599 * correct z-order and pipe acquisition the current DC architecture 7600 * requires us to remove and recreate all existing planes. 7601 * 7602 * TODO: Come up with a more elegant solution for this. 7603 */ 7604 for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) { 7605 if (other->type == DRM_PLANE_TYPE_CURSOR) 7606 continue; 7607 7608 if (old_other_state->crtc != new_plane_state->crtc && 7609 new_other_state->crtc != new_plane_state->crtc) 7610 continue; 7611 7612 if (old_other_state->crtc != new_other_state->crtc) 7613 return true; 7614 7615 /* TODO: Remove this once we can handle fast format changes. */ 7616 if (old_other_state->fb && new_other_state->fb && 7617 old_other_state->fb->format != new_other_state->fb->format) 7618 return true; 7619 } 7620 7621 return false; 7622 } 7623 7624 static int dm_update_plane_state(struct dc *dc, 7625 struct drm_atomic_state *state, 7626 struct drm_plane *plane, 7627 struct drm_plane_state *old_plane_state, 7628 struct drm_plane_state *new_plane_state, 7629 bool enable, 7630 bool *lock_and_validation_needed) 7631 { 7632 7633 struct dm_atomic_state *dm_state = NULL; 7634 struct drm_crtc *new_plane_crtc, *old_plane_crtc; 7635 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 7636 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state; 7637 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state; 7638 bool needs_reset; 7639 int ret = 0; 7640 7641 7642 new_plane_crtc = new_plane_state->crtc; 7643 old_plane_crtc = old_plane_state->crtc; 7644 dm_new_plane_state = to_dm_plane_state(new_plane_state); 7645 dm_old_plane_state = to_dm_plane_state(old_plane_state); 7646 7647 /*TODO Implement atomic check for cursor plane */ 7648 if (plane->type == DRM_PLANE_TYPE_CURSOR) 7649 return 0; 7650 7651 needs_reset = should_reset_plane(state, plane, old_plane_state, 7652 new_plane_state); 7653 7654 /* Remove any changed/removed planes */ 7655 if (!enable) { 7656 if (!needs_reset) 7657 return 0; 7658 7659 if (!old_plane_crtc) 7660 return 0; 7661 7662 old_crtc_state = drm_atomic_get_old_crtc_state( 7663 state, old_plane_crtc); 7664 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 7665 7666 if (!dm_old_crtc_state->stream) 7667 return 0; 7668 7669 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n", 7670 plane->base.id, old_plane_crtc->base.id); 7671 7672 ret = dm_atomic_get_state(state, &dm_state); 7673 if (ret) 7674 return ret; 7675 7676 if (!dc_remove_plane_from_context( 7677 dc, 7678 dm_old_crtc_state->stream, 7679 dm_old_plane_state->dc_state, 7680 dm_state->context)) { 7681 7682 ret = EINVAL; 7683 return ret; 7684 } 7685 7686 7687 dc_plane_state_release(dm_old_plane_state->dc_state); 7688 dm_new_plane_state->dc_state = NULL; 7689 7690 *lock_and_validation_needed = true; 7691 7692 } else { /* Add new planes */ 7693 struct dc_plane_state *dc_new_plane_state; 7694 7695 if (drm_atomic_plane_disabling(plane->state, new_plane_state)) 7696 return 0; 7697 7698 if (!new_plane_crtc) 7699 return 0; 7700 7701 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc); 7702 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 7703 7704 if (!dm_new_crtc_state->stream) 7705 return 0; 7706 7707 if (!needs_reset) 7708 return 0; 7709 7710 WARN_ON(dm_new_plane_state->dc_state); 7711 7712 dc_new_plane_state = dc_create_plane_state(dc); 7713 if (!dc_new_plane_state) 7714 return -ENOMEM; 7715 7716 DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n", 7717 plane->base.id, new_plane_crtc->base.id); 7718 7719 ret = fill_dc_plane_attributes( 7720 new_plane_crtc->dev->dev_private, 7721 dc_new_plane_state, 7722 new_plane_state, 7723 new_crtc_state); 7724 if (ret) { 7725 dc_plane_state_release(dc_new_plane_state); 7726 return ret; 7727 } 7728 7729 ret = dm_atomic_get_state(state, &dm_state); 7730 if (ret) { 7731 dc_plane_state_release(dc_new_plane_state); 7732 return ret; 7733 } 7734 7735 /* 7736 * Any atomic check errors that occur after this will 7737 * not need a release. The plane state will be attached 7738 * to the stream, and therefore part of the atomic 7739 * state. It'll be released when the atomic state is 7740 * cleaned. 7741 */ 7742 if (!dc_add_plane_to_context( 7743 dc, 7744 dm_new_crtc_state->stream, 7745 dc_new_plane_state, 7746 dm_state->context)) { 7747 7748 dc_plane_state_release(dc_new_plane_state); 7749 return -EINVAL; 7750 } 7751 7752 dm_new_plane_state->dc_state = dc_new_plane_state; 7753 7754 /* Tell DC to do a full surface update every time there 7755 * is a plane change. Inefficient, but works for now. 7756 */ 7757 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1; 7758 7759 *lock_and_validation_needed = true; 7760 } 7761 7762 7763 return ret; 7764 } 7765 7766 static int 7767 dm_determine_update_type_for_commit(struct amdgpu_display_manager *dm, 7768 struct drm_atomic_state *state, 7769 enum surface_update_type *out_type) 7770 { 7771 struct dc *dc = dm->dc; 7772 struct dm_atomic_state *dm_state = NULL, *old_dm_state = NULL; 7773 int i, j, num_plane, ret = 0; 7774 struct drm_plane_state *old_plane_state, *new_plane_state; 7775 struct dm_plane_state *new_dm_plane_state, *old_dm_plane_state; 7776 struct drm_crtc *new_plane_crtc; 7777 struct drm_plane *plane; 7778 7779 struct drm_crtc *crtc; 7780 struct drm_crtc_state *new_crtc_state, *old_crtc_state; 7781 struct dm_crtc_state *new_dm_crtc_state, *old_dm_crtc_state; 7782 struct dc_stream_status *status = NULL; 7783 enum surface_update_type update_type = UPDATE_TYPE_FAST; 7784 struct surface_info_bundle { 7785 struct dc_surface_update surface_updates[MAX_SURFACES]; 7786 struct dc_plane_info plane_infos[MAX_SURFACES]; 7787 struct dc_scaling_info scaling_infos[MAX_SURFACES]; 7788 struct dc_flip_addrs flip_addrs[MAX_SURFACES]; 7789 struct dc_stream_update stream_update; 7790 } *bundle; 7791 7792 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL); 7793 7794 if (!bundle) { 7795 DRM_ERROR("Failed to allocate update bundle\n"); 7796 /* Set type to FULL to avoid crashing in DC*/ 7797 update_type = UPDATE_TYPE_FULL; 7798 goto cleanup; 7799 } 7800 7801 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 7802 7803 memset(bundle, 0, sizeof(struct surface_info_bundle)); 7804 7805 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state); 7806 old_dm_crtc_state = to_dm_crtc_state(old_crtc_state); 7807 num_plane = 0; 7808 7809 if (new_dm_crtc_state->stream != old_dm_crtc_state->stream) { 7810 update_type = UPDATE_TYPE_FULL; 7811 goto cleanup; 7812 } 7813 7814 if (!new_dm_crtc_state->stream) 7815 continue; 7816 7817 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, j) { 7818 const struct amdgpu_framebuffer *amdgpu_fb = 7819 to_amdgpu_framebuffer(new_plane_state->fb); 7820 struct dc_plane_info *plane_info = &bundle->plane_infos[num_plane]; 7821 struct dc_flip_addrs *flip_addr = &bundle->flip_addrs[num_plane]; 7822 struct dc_scaling_info *scaling_info = &bundle->scaling_infos[num_plane]; 7823 uint64_t tiling_flags; 7824 7825 new_plane_crtc = new_plane_state->crtc; 7826 new_dm_plane_state = to_dm_plane_state(new_plane_state); 7827 old_dm_plane_state = to_dm_plane_state(old_plane_state); 7828 7829 if (plane->type == DRM_PLANE_TYPE_CURSOR) 7830 continue; 7831 7832 if (new_dm_plane_state->dc_state != old_dm_plane_state->dc_state) { 7833 update_type = UPDATE_TYPE_FULL; 7834 goto cleanup; 7835 } 7836 7837 if (crtc != new_plane_crtc) 7838 continue; 7839 7840 bundle->surface_updates[num_plane].surface = 7841 new_dm_plane_state->dc_state; 7842 7843 if (new_crtc_state->mode_changed) { 7844 bundle->stream_update.dst = new_dm_crtc_state->stream->dst; 7845 bundle->stream_update.src = new_dm_crtc_state->stream->src; 7846 } 7847 7848 if (new_crtc_state->color_mgmt_changed) { 7849 bundle->surface_updates[num_plane].gamma = 7850 new_dm_plane_state->dc_state->gamma_correction; 7851 bundle->surface_updates[num_plane].in_transfer_func = 7852 new_dm_plane_state->dc_state->in_transfer_func; 7853 bundle->stream_update.gamut_remap = 7854 &new_dm_crtc_state->stream->gamut_remap_matrix; 7855 bundle->stream_update.output_csc_transform = 7856 &new_dm_crtc_state->stream->csc_color_matrix; 7857 bundle->stream_update.out_transfer_func = 7858 new_dm_crtc_state->stream->out_transfer_func; 7859 } 7860 7861 ret = fill_dc_scaling_info(new_plane_state, 7862 scaling_info); 7863 if (ret) 7864 goto cleanup; 7865 7866 bundle->surface_updates[num_plane].scaling_info = scaling_info; 7867 7868 if (amdgpu_fb) { 7869 ret = get_fb_info(amdgpu_fb, &tiling_flags); 7870 if (ret) 7871 goto cleanup; 7872 7873 ret = fill_dc_plane_info_and_addr( 7874 dm->adev, new_plane_state, tiling_flags, 7875 plane_info, 7876 &flip_addr->address); 7877 if (ret) 7878 goto cleanup; 7879 7880 bundle->surface_updates[num_plane].plane_info = plane_info; 7881 bundle->surface_updates[num_plane].flip_addr = flip_addr; 7882 } 7883 7884 num_plane++; 7885 } 7886 7887 if (num_plane == 0) 7888 continue; 7889 7890 ret = dm_atomic_get_state(state, &dm_state); 7891 if (ret) 7892 goto cleanup; 7893 7894 old_dm_state = dm_atomic_get_old_state(state); 7895 if (!old_dm_state) { 7896 ret = -EINVAL; 7897 goto cleanup; 7898 } 7899 7900 status = dc_stream_get_status_from_state(old_dm_state->context, 7901 new_dm_crtc_state->stream); 7902 bundle->stream_update.stream = new_dm_crtc_state->stream; 7903 /* 7904 * TODO: DC modifies the surface during this call so we need 7905 * to lock here - find a way to do this without locking. 7906 */ 7907 mutex_lock(&dm->dc_lock); 7908 update_type = dc_check_update_surfaces_for_stream( 7909 dc, bundle->surface_updates, num_plane, 7910 &bundle->stream_update, status); 7911 mutex_unlock(&dm->dc_lock); 7912 7913 if (update_type > UPDATE_TYPE_MED) { 7914 update_type = UPDATE_TYPE_FULL; 7915 goto cleanup; 7916 } 7917 } 7918 7919 cleanup: 7920 kfree(bundle); 7921 7922 *out_type = update_type; 7923 return ret; 7924 } 7925 7926 static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc) 7927 { 7928 struct drm_connector *connector; 7929 struct drm_connector_state *conn_state; 7930 struct amdgpu_dm_connector *aconnector = NULL; 7931 int i; 7932 for_each_new_connector_in_state(state, connector, conn_state, i) { 7933 if (conn_state->crtc != crtc) 7934 continue; 7935 7936 aconnector = to_amdgpu_dm_connector(connector); 7937 if (!aconnector->port || !aconnector->mst_port) 7938 aconnector = NULL; 7939 else 7940 break; 7941 } 7942 7943 if (!aconnector) 7944 return 0; 7945 7946 return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_port->mst_mgr); 7947 } 7948 7949 /** 7950 * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM. 7951 * @dev: The DRM device 7952 * @state: The atomic state to commit 7953 * 7954 * Validate that the given atomic state is programmable by DC into hardware. 7955 * This involves constructing a &struct dc_state reflecting the new hardware 7956 * state we wish to commit, then querying DC to see if it is programmable. It's 7957 * important not to modify the existing DC state. Otherwise, atomic_check 7958 * may unexpectedly commit hardware changes. 7959 * 7960 * When validating the DC state, it's important that the right locks are 7961 * acquired. For full updates case which removes/adds/updates streams on one 7962 * CRTC while flipping on another CRTC, acquiring global lock will guarantee 7963 * that any such full update commit will wait for completion of any outstanding 7964 * flip using DRMs synchronization events. See 7965 * dm_determine_update_type_for_commit() 7966 * 7967 * Note that DM adds the affected connectors for all CRTCs in state, when that 7968 * might not seem necessary. This is because DC stream creation requires the 7969 * DC sink, which is tied to the DRM connector state. Cleaning this up should 7970 * be possible but non-trivial - a possible TODO item. 7971 * 7972 * Return: -Error code if validation failed. 7973 */ 7974 static int amdgpu_dm_atomic_check(struct drm_device *dev, 7975 struct drm_atomic_state *state) 7976 { 7977 struct amdgpu_device *adev = dev->dev_private; 7978 struct dm_atomic_state *dm_state = NULL; 7979 struct dc *dc = adev->dm.dc; 7980 struct drm_connector *connector; 7981 struct drm_connector_state *old_con_state, *new_con_state; 7982 struct drm_crtc *crtc; 7983 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 7984 struct drm_plane *plane; 7985 struct drm_plane_state *old_plane_state, *new_plane_state; 7986 enum surface_update_type update_type = UPDATE_TYPE_FAST; 7987 enum surface_update_type overall_update_type = UPDATE_TYPE_FAST; 7988 7989 int ret, i; 7990 7991 /* 7992 * This bool will be set for true for any modeset/reset 7993 * or plane update which implies non fast surface update. 7994 */ 7995 bool lock_and_validation_needed = false; 7996 7997 ret = drm_atomic_helper_check_modeset(dev, state); 7998 if (ret) 7999 goto fail; 8000 8001 if (adev->asic_type >= CHIP_NAVI10) { 8002 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 8003 if (drm_atomic_crtc_needs_modeset(new_crtc_state)) { 8004 ret = add_affected_mst_dsc_crtcs(state, crtc); 8005 if (ret) 8006 goto fail; 8007 } 8008 } 8009 } 8010 8011 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 8012 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) && 8013 !new_crtc_state->color_mgmt_changed && 8014 old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled) 8015 continue; 8016 8017 if (!new_crtc_state->enable) 8018 continue; 8019 8020 ret = drm_atomic_add_affected_connectors(state, crtc); 8021 if (ret) 8022 return ret; 8023 8024 ret = drm_atomic_add_affected_planes(state, crtc); 8025 if (ret) 8026 goto fail; 8027 } 8028 8029 /* 8030 * Add all primary and overlay planes on the CRTC to the state 8031 * whenever a plane is enabled to maintain correct z-ordering 8032 * and to enable fast surface updates. 8033 */ 8034 drm_for_each_crtc(crtc, dev) { 8035 bool modified = false; 8036 8037 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { 8038 if (plane->type == DRM_PLANE_TYPE_CURSOR) 8039 continue; 8040 8041 if (new_plane_state->crtc == crtc || 8042 old_plane_state->crtc == crtc) { 8043 modified = true; 8044 break; 8045 } 8046 } 8047 8048 if (!modified) 8049 continue; 8050 8051 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) { 8052 if (plane->type == DRM_PLANE_TYPE_CURSOR) 8053 continue; 8054 8055 new_plane_state = 8056 drm_atomic_get_plane_state(state, plane); 8057 8058 if (IS_ERR(new_plane_state)) { 8059 ret = PTR_ERR(new_plane_state); 8060 goto fail; 8061 } 8062 } 8063 } 8064 8065 /* Remove exiting planes if they are modified */ 8066 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) { 8067 ret = dm_update_plane_state(dc, state, plane, 8068 old_plane_state, 8069 new_plane_state, 8070 false, 8071 &lock_and_validation_needed); 8072 if (ret) 8073 goto fail; 8074 } 8075 8076 /* Disable all crtcs which require disable */ 8077 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 8078 ret = dm_update_crtc_state(&adev->dm, state, crtc, 8079 old_crtc_state, 8080 new_crtc_state, 8081 false, 8082 &lock_and_validation_needed); 8083 if (ret) 8084 goto fail; 8085 } 8086 8087 /* Enable all crtcs which require enable */ 8088 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 8089 ret = dm_update_crtc_state(&adev->dm, state, crtc, 8090 old_crtc_state, 8091 new_crtc_state, 8092 true, 8093 &lock_and_validation_needed); 8094 if (ret) 8095 goto fail; 8096 } 8097 8098 /* Add new/modified planes */ 8099 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) { 8100 ret = dm_update_plane_state(dc, state, plane, 8101 old_plane_state, 8102 new_plane_state, 8103 true, 8104 &lock_and_validation_needed); 8105 if (ret) 8106 goto fail; 8107 } 8108 8109 /* Run this here since we want to validate the streams we created */ 8110 ret = drm_atomic_helper_check_planes(dev, state); 8111 if (ret) 8112 goto fail; 8113 8114 if (state->legacy_cursor_update) { 8115 /* 8116 * This is a fast cursor update coming from the plane update 8117 * helper, check if it can be done asynchronously for better 8118 * performance. 8119 */ 8120 state->async_update = 8121 !drm_atomic_helper_async_check(dev, state); 8122 8123 /* 8124 * Skip the remaining global validation if this is an async 8125 * update. Cursor updates can be done without affecting 8126 * state or bandwidth calcs and this avoids the performance 8127 * penalty of locking the private state object and 8128 * allocating a new dc_state. 8129 */ 8130 if (state->async_update) 8131 return 0; 8132 } 8133 8134 /* Check scaling and underscan changes*/ 8135 /* TODO Removed scaling changes validation due to inability to commit 8136 * new stream into context w\o causing full reset. Need to 8137 * decide how to handle. 8138 */ 8139 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 8140 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 8141 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 8142 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 8143 8144 /* Skip any modesets/resets */ 8145 if (!acrtc || drm_atomic_crtc_needs_modeset( 8146 drm_atomic_get_new_crtc_state(state, &acrtc->base))) 8147 continue; 8148 8149 /* Skip any thing not scale or underscan changes */ 8150 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state)) 8151 continue; 8152 8153 overall_update_type = UPDATE_TYPE_FULL; 8154 lock_and_validation_needed = true; 8155 } 8156 8157 ret = dm_determine_update_type_for_commit(&adev->dm, state, &update_type); 8158 if (ret) 8159 goto fail; 8160 8161 if (overall_update_type < update_type) 8162 overall_update_type = update_type; 8163 8164 /* 8165 * lock_and_validation_needed was an old way to determine if we need to set 8166 * the global lock. Leaving it in to check if we broke any corner cases 8167 * lock_and_validation_needed true = UPDATE_TYPE_FULL or UPDATE_TYPE_MED 8168 * lock_and_validation_needed false = UPDATE_TYPE_FAST 8169 */ 8170 if (lock_and_validation_needed && overall_update_type <= UPDATE_TYPE_FAST) 8171 WARN(1, "Global lock should be Set, overall_update_type should be UPDATE_TYPE_MED or UPDATE_TYPE_FULL"); 8172 8173 if (overall_update_type > UPDATE_TYPE_FAST) { 8174 ret = dm_atomic_get_state(state, &dm_state); 8175 if (ret) 8176 goto fail; 8177 8178 ret = do_aquire_global_lock(dev, state); 8179 if (ret) 8180 goto fail; 8181 8182 #if defined(CONFIG_DRM_AMD_DC_DCN) 8183 if (!compute_mst_dsc_configs_for_state(state, dm_state->context)) 8184 goto fail; 8185 8186 ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context); 8187 if (ret) 8188 goto fail; 8189 #endif 8190 8191 /* 8192 * Perform validation of MST topology in the state: 8193 * We need to perform MST atomic check before calling 8194 * dc_validate_global_state(), or there is a chance 8195 * to get stuck in an infinite loop and hang eventually. 8196 */ 8197 ret = drm_dp_mst_atomic_check(state); 8198 if (ret) 8199 goto fail; 8200 8201 if (dc_validate_global_state(dc, dm_state->context, false) != DC_OK) { 8202 ret = -EINVAL; 8203 goto fail; 8204 } 8205 } else { 8206 /* 8207 * The commit is a fast update. Fast updates shouldn't change 8208 * the DC context, affect global validation, and can have their 8209 * commit work done in parallel with other commits not touching 8210 * the same resource. If we have a new DC context as part of 8211 * the DM atomic state from validation we need to free it and 8212 * retain the existing one instead. 8213 */ 8214 struct dm_atomic_state *new_dm_state, *old_dm_state; 8215 8216 new_dm_state = dm_atomic_get_new_state(state); 8217 old_dm_state = dm_atomic_get_old_state(state); 8218 8219 if (new_dm_state && old_dm_state) { 8220 if (new_dm_state->context) 8221 dc_release_state(new_dm_state->context); 8222 8223 new_dm_state->context = old_dm_state->context; 8224 8225 if (old_dm_state->context) 8226 dc_retain_state(old_dm_state->context); 8227 } 8228 } 8229 8230 /* Store the overall update type for use later in atomic check. */ 8231 for_each_new_crtc_in_state (state, crtc, new_crtc_state, i) { 8232 struct dm_crtc_state *dm_new_crtc_state = 8233 to_dm_crtc_state(new_crtc_state); 8234 8235 dm_new_crtc_state->update_type = (int)overall_update_type; 8236 } 8237 8238 /* Must be success */ 8239 WARN_ON(ret); 8240 return ret; 8241 8242 fail: 8243 if (ret == -EDEADLK) 8244 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n"); 8245 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS) 8246 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n"); 8247 else 8248 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret); 8249 8250 return ret; 8251 } 8252 8253 static bool is_dp_capable_without_timing_msa(struct dc *dc, 8254 struct amdgpu_dm_connector *amdgpu_dm_connector) 8255 { 8256 uint8_t dpcd_data; 8257 bool capable = false; 8258 8259 if (amdgpu_dm_connector->dc_link && 8260 dm_helpers_dp_read_dpcd( 8261 NULL, 8262 amdgpu_dm_connector->dc_link, 8263 DP_DOWN_STREAM_PORT_COUNT, 8264 &dpcd_data, 8265 sizeof(dpcd_data))) { 8266 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false; 8267 } 8268 8269 return capable; 8270 } 8271 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, 8272 struct edid *edid) 8273 { 8274 int i; 8275 bool edid_check_required; 8276 struct detailed_timing *timing; 8277 struct detailed_non_pixel *data; 8278 struct detailed_data_monitor_range *range; 8279 struct amdgpu_dm_connector *amdgpu_dm_connector = 8280 to_amdgpu_dm_connector(connector); 8281 struct dm_connector_state *dm_con_state = NULL; 8282 8283 struct drm_device *dev = connector->dev; 8284 struct amdgpu_device *adev = dev->dev_private; 8285 bool freesync_capable = false; 8286 8287 if (!connector->state) { 8288 DRM_ERROR("%s - Connector has no state", __func__); 8289 goto update; 8290 } 8291 8292 if (!edid) { 8293 dm_con_state = to_dm_connector_state(connector->state); 8294 8295 amdgpu_dm_connector->min_vfreq = 0; 8296 amdgpu_dm_connector->max_vfreq = 0; 8297 amdgpu_dm_connector->pixel_clock_mhz = 0; 8298 8299 goto update; 8300 } 8301 8302 dm_con_state = to_dm_connector_state(connector->state); 8303 8304 edid_check_required = false; 8305 if (!amdgpu_dm_connector->dc_sink) { 8306 DRM_ERROR("dc_sink NULL, could not add free_sync module.\n"); 8307 goto update; 8308 } 8309 if (!adev->dm.freesync_module) 8310 goto update; 8311 /* 8312 * if edid non zero restrict freesync only for dp and edp 8313 */ 8314 if (edid) { 8315 if (amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT 8316 || amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) { 8317 edid_check_required = is_dp_capable_without_timing_msa( 8318 adev->dm.dc, 8319 amdgpu_dm_connector); 8320 } 8321 } 8322 if (edid_check_required == true && (edid->version > 1 || 8323 (edid->version == 1 && edid->revision > 1))) { 8324 for (i = 0; i < 4; i++) { 8325 8326 timing = &edid->detailed_timings[i]; 8327 data = &timing->data.other_data; 8328 range = &data->data.range; 8329 /* 8330 * Check if monitor has continuous frequency mode 8331 */ 8332 if (data->type != EDID_DETAIL_MONITOR_RANGE) 8333 continue; 8334 /* 8335 * Check for flag range limits only. If flag == 1 then 8336 * no additional timing information provided. 8337 * Default GTF, GTF Secondary curve and CVT are not 8338 * supported 8339 */ 8340 if (range->flags != 1) 8341 continue; 8342 8343 amdgpu_dm_connector->min_vfreq = range->min_vfreq; 8344 amdgpu_dm_connector->max_vfreq = range->max_vfreq; 8345 amdgpu_dm_connector->pixel_clock_mhz = 8346 range->pixel_clock_mhz * 10; 8347 break; 8348 } 8349 8350 if (amdgpu_dm_connector->max_vfreq - 8351 amdgpu_dm_connector->min_vfreq > 10) { 8352 8353 freesync_capable = true; 8354 } 8355 } 8356 8357 update: 8358 if (dm_con_state) 8359 dm_con_state->freesync_capable = freesync_capable; 8360 8361 if (connector->vrr_capable_property) 8362 drm_connector_set_vrr_capable_property(connector, 8363 freesync_capable); 8364 } 8365 8366 static void amdgpu_dm_set_psr_caps(struct dc_link *link) 8367 { 8368 uint8_t dpcd_data[EDP_PSR_RECEIVER_CAP_SIZE]; 8369 8370 if (!(link->connector_signal & SIGNAL_TYPE_EDP)) 8371 return; 8372 if (link->type == dc_connection_none) 8373 return; 8374 if (dm_helpers_dp_read_dpcd(NULL, link, DP_PSR_SUPPORT, 8375 dpcd_data, sizeof(dpcd_data))) { 8376 link->psr_feature_enabled = dpcd_data[0] ? true:false; 8377 DRM_INFO("PSR support:%d\n", link->psr_feature_enabled); 8378 } 8379 } 8380 8381 /* 8382 * amdgpu_dm_link_setup_psr() - configure psr link 8383 * @stream: stream state 8384 * 8385 * Return: true if success 8386 */ 8387 static bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream) 8388 { 8389 struct dc_link *link = NULL; 8390 struct psr_config psr_config = {0}; 8391 struct psr_context psr_context = {0}; 8392 struct dc *dc = NULL; 8393 bool ret = false; 8394 8395 if (stream == NULL) 8396 return false; 8397 8398 link = stream->link; 8399 dc = link->ctx->dc; 8400 8401 psr_config.psr_version = dc->res_pool->dmcu->dmcu_version.psr_version; 8402 8403 if (psr_config.psr_version > 0) { 8404 psr_config.psr_exit_link_training_required = 0x1; 8405 psr_config.psr_frame_capture_indication_req = 0; 8406 psr_config.psr_rfb_setup_time = 0x37; 8407 psr_config.psr_sdp_transmit_line_num_deadline = 0x20; 8408 psr_config.allow_smu_optimizations = 0x0; 8409 8410 ret = dc_link_setup_psr(link, stream, &psr_config, &psr_context); 8411 8412 } 8413 DRM_DEBUG_DRIVER("PSR link: %d\n", link->psr_feature_enabled); 8414 8415 return ret; 8416 } 8417 8418 /* 8419 * amdgpu_dm_psr_enable() - enable psr f/w 8420 * @stream: stream state 8421 * 8422 * Return: true if success 8423 */ 8424 bool amdgpu_dm_psr_enable(struct dc_stream_state *stream) 8425 { 8426 struct dc_link *link = stream->link; 8427 unsigned int vsync_rate_hz = 0; 8428 struct dc_static_screen_params params = {0}; 8429 /* Calculate number of static frames before generating interrupt to 8430 * enter PSR. 8431 */ 8432 // Init fail safe of 2 frames static 8433 unsigned int num_frames_static = 2; 8434 8435 DRM_DEBUG_DRIVER("Enabling psr...\n"); 8436 8437 vsync_rate_hz = div64_u64(div64_u64(( 8438 stream->timing.pix_clk_100hz * 100), 8439 stream->timing.v_total), 8440 stream->timing.h_total); 8441 8442 /* Round up 8443 * Calculate number of frames such that at least 30 ms of time has 8444 * passed. 8445 */ 8446 if (vsync_rate_hz != 0) { 8447 unsigned int frame_time_microsec = 1000000 / vsync_rate_hz; 8448 num_frames_static = (30000 / frame_time_microsec) + 1; 8449 } 8450 8451 params.triggers.cursor_update = true; 8452 params.triggers.overlay_update = true; 8453 params.triggers.surface_update = true; 8454 params.num_frames = num_frames_static; 8455 8456 dc_stream_set_static_screen_params(link->ctx->dc, 8457 &stream, 1, 8458 ¶ms); 8459 8460 return dc_link_set_psr_allow_active(link, true, false); 8461 } 8462 8463 /* 8464 * amdgpu_dm_psr_disable() - disable psr f/w 8465 * @stream: stream state 8466 * 8467 * Return: true if success 8468 */ 8469 static bool amdgpu_dm_psr_disable(struct dc_stream_state *stream) 8470 { 8471 8472 DRM_DEBUG_DRIVER("Disabling psr...\n"); 8473 8474 return dc_link_set_psr_allow_active(stream->link, false, true); 8475 } 8476
Indexes created Sun Sep 21 16:09:51 GMT 2025