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      1 /*	$NetBSD: i82557reg.h,v 1.25 2011/09/02 03:16:19 msaitoh Exp $	*/
      2 
      3 /*-
      4  * Copyright (c) 1998, 1999, 2001 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to The NetBSD Foundation
      8  * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
      9  * NASA Ames Research Center.
     10  *
     11  * Redistribution and use in source and binary forms, with or without
     12  * modification, are permitted provided that the following conditions
     13  * are met:
     14  * 1. Redistributions of source code must retain the above copyright
     15  *    notice, this list of conditions and the following disclaimer.
     16  * 2. Redistributions in binary form must reproduce the above copyright
     17  *    notice, this list of conditions and the following disclaimer in the
     18  *    documentation and/or other materials provided with the distribution.
     19  *
     20  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     21  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     22  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     23  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     30  * POSSIBILITY OF SUCH DAMAGE.
     31  */
     32 
     33 /*
     34  * Copyright (c) 1995, David Greenman
     35  * Copyright (c) 2001 Jonathan Lemon <jlemon (at) freebsd.org>
     36  * All rights reserved.
     37  *
     38  * Redistribution and use in source and binary forms, with or without
     39  * modification, are permitted provided that the following conditions
     40  * are met:
     41  * 1. Redistributions of source code must retain the above copyright
     42  *    notice unmodified, this list of conditions, and the following
     43  *    disclaimer.
     44  * 2. Redistributions in binary form must reproduce the above copyright
     45  *    notice, this list of conditions and the following disclaimer in the
     46  *    documentation and/or other materials provided with the distribution.
     47  *
     48  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
     49  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     50  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     51  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
     52  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     53  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     54  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     55  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     56  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     57  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     58  * SUCH DAMAGE.
     59  *
     60  *	Id: if_fxpreg.h,v 1.24 2001/05/15 18:52:40 jlemon Exp
     61  */
     62 
     63 #define FXP_PCI_MMBA	0x10
     64 #define FXP_PCI_IOBA	0x14
     65 
     66 /*
     67  * Control/status registers.
     68  */
     69 #define	FXP_CSR_SCB_RUSCUS	0x00	/* scb_rus/scb_cus (1 byte) */
     70 #define	FXP_CSR_SCB_STATACK	0x01	/* scb_statack (1 byte) */
     71 #define	FXP_CSR_SCB_COMMAND	0x02	/* scb_command (1 byte) */
     72 #define	FXP_CSR_SCB_INTRCNTL	0x03	/* scb_intrcntl (1 byte) */
     73 #define	FXP_CSR_SCB_GENERAL	0x04	/* scb_general (4 bytes) */
     74 #define	FXP_CSR_PORT		0x08	/* port (4 bytes) */
     75 #define	FXP_CSR_FLASHCONTROL	0x0c	/* flash control (2 bytes) */
     76 #define	FXP_CSR_EEPROMCONTROL	0x0e	/* eeprom control (2 bytes) */
     77 #define	FXP_CSR_MDICONTROL	0x10	/* mdi control (4 bytes) */
     78 #define	FXP_CSR_FLOWCONTROL	0x19	/* flow control (2 bytes) */
     79 
     80 /*
     81  * FOR REFERENCE ONLY, the old definition of FXP_CSR_SCB_RUSCUS:
     82  *
     83  *	volatile uint8_t	:2,
     84  *				scb_rus:4,
     85  *				scb_cus:2;
     86  */
     87 
     88 #define FXP_PORT_SOFTWARE_RESET		0
     89 #define FXP_PORT_SELFTEST		1
     90 #define FXP_PORT_SELECTIVE_RESET	2
     91 #define FXP_PORT_DUMP			3
     92 
     93 #define FXP_SCB_RUS_IDLE		0
     94 #define FXP_SCB_RUS_SUSPENDED		1
     95 #define FXP_SCB_RUS_NORESOURCES		2
     96 #define FXP_SCB_RUS_READY		4
     97 #define FXP_SCB_RUS_SUSP_NORBDS		9
     98 #define FXP_SCB_RUS_NORES_NORBDS	10
     99 #define FXP_SCB_RUS_READY_NORBDS	12
    100 
    101 #define FXP_SCB_CUS_IDLE		0
    102 #define FXP_SCB_CUS_SUSPENDED		1
    103 #define FXP_SCB_CUS_ACTIVE		2
    104 
    105 #define	FXP_SCB_INTR_DISABLE		0x01	/* disable all interrupts */
    106 #define	FXP_SCB_INTR_SWI		0x02	/* generate SWI */
    107 #define	FXP_SCB_INTMASK_FCP		0x04
    108 #define	FXP_SCB_INTMASK_ER		0x08
    109 #define	FXP_SCB_INTMASK_RNR		0x10
    110 #define	FXP_SCB_INTMASK_CNA		0x20
    111 #define	FXP_SCB_INTMASK_FR		0x40
    112 #define	FXP_SCB_INTMASK_CXTNO		0x80
    113 
    114 #define	FXP_SCB_STATACK_FCP		0x01	/* flow control pause */
    115 #define	FXP_SCB_STATACK_ER		0x02	/* early receive */
    116 #define FXP_SCB_STATACK_SWI		0x04
    117 #define FXP_SCB_STATACK_MDI		0x08
    118 #define FXP_SCB_STATACK_RNR		0x10
    119 #define FXP_SCB_STATACK_CNA		0x20
    120 #define FXP_SCB_STATACK_FR		0x40
    121 #define FXP_SCB_STATACK_CXTNO		0x80
    122 
    123 #define FXP_SCB_COMMAND_CU_NOP		0x00
    124 #define FXP_SCB_COMMAND_CU_START	0x10
    125 #define FXP_SCB_COMMAND_CU_RESUME	0x20
    126 #define FXP_SCB_COMMAND_CU_DUMP_ADR	0x40
    127 #define FXP_SCB_COMMAND_CU_DUMP		0x50
    128 #define FXP_SCB_COMMAND_CU_BASE		0x60
    129 #define FXP_SCB_COMMAND_CU_DUMPRESET	0x70
    130 
    131 #define FXP_SCB_COMMAND_RU_NOP		0
    132 #define FXP_SCB_COMMAND_RU_START	1
    133 #define FXP_SCB_COMMAND_RU_RESUME	2
    134 #define FXP_SCB_COMMAND_RU_ABORT	4
    135 #define FXP_SCB_COMMAND_RU_LOADHDS	5
    136 #define FXP_SCB_COMMAND_RU_BASE		6
    137 #define FXP_SCB_COMMAND_RU_RBDRESUME	7
    138 
    139 #define FXP_SCB_INTRCNTL_REQUEST_SWI	0x02
    140 /*
    141  * Command block definitions
    142  */
    143 
    144 /*
    145  * NOP command.
    146  */
    147 struct fxp_cb_nop {
    148 	volatile uint16_t cb_status;
    149 	volatile uint16_t cb_command;
    150 	volatile uint32_t link_addr;
    151 };
    152 
    153 /*
    154  * Individual Address command.
    155  */
    156 struct fxp_cb_ias {
    157 	volatile uint16_t cb_status;
    158 	volatile uint16_t cb_command;
    159 	volatile uint32_t link_addr;
    160 	uint8_t macaddr[6];
    161 };
    162 
    163 #if BYTE_ORDER == LITTLE_ENDIAN
    164 #define	__FXP_BITFIELD2(a, b)			a, b
    165 #define	__FXP_BITFIELD3(a, b, c)		a, b, c
    166 #define	__FXP_BITFIELD4(a, b, c, d)		a, b, c, d
    167 #define	__FXP_BITFIELD5(a, b, c, d, e)		a, b, c, d, e
    168 #define	__FXP_BITFIELD6(a, b, c, d, e, f)	a, b, c, d, e, f
    169 #define	__FXP_BITFIELD7(a, b, c, d, e, f, g)	a, b, c, d, e, f, g
    170 #define	__FXP_BITFIELD8(a, b, c, d, e, f, g, h)	a, b, c, d, e, f, g, h
    171 #else
    172 #define	__FXP_BITFIELD2(a, b)			b, a
    173 #define	__FXP_BITFIELD3(a, b, c)		c, b, a
    174 #define	__FXP_BITFIELD4(a, b, c, d)		d, c, b, a
    175 #define	__FXP_BITFIELD5(a, b, c, d, e)		e, d, c, b, a
    176 #define	__FXP_BITFIELD6(a, b, c, d, e, f)	f, e, d, c, b, a
    177 #define	__FXP_BITFIELD7(a, b, c, d, e, f, g)	g, f, e, d, c, b, a
    178 #define	__FXP_BITFIELD8(a, b, c, d, e, f, g, h)	h, g, f, e, d, c, b, a
    179 #endif
    180 
    181 /*
    182  * Configure command.
    183  */
    184 struct fxp_cb_config {
    185 	volatile uint16_t	cb_status;
    186 	volatile uint16_t	cb_command;
    187 	volatile uint32_t	link_addr;
    188 
    189 	/* Bytes 0 - 21 -- common to all i8255x */
    190 /*0*/	volatile uint8_t	__FXP_BITFIELD2(byte_count:6, :2);
    191 /*1*/	volatile uint8_t	__FXP_BITFIELD3(rx_fifo_limit:4,
    192 				    tx_fifo_limit:3,
    193 				    :1);
    194 /*2*/	volatile uint8_t	adaptive_ifs;
    195 /*3*/	volatile uint8_t	__FXP_BITFIELD5(mwi_enable:1,	/* 8,9 */
    196 				    type_enable:1,		/* 8,9 */
    197 				    read_align_en:1,		/* 8,9 */
    198 				    end_wr_on_cl:1,		/* 8,9 */
    199 				    :4);
    200 /*4*/	volatile uint8_t	__FXP_BITFIELD2(rx_dma_bytecount:7,
    201 				    :1);
    202 /*5*/	volatile uint8_t	__FXP_BITFIELD2(tx_dma_bytecount:7,
    203 				    dma_mbce:1);
    204 /*6*/	volatile uint8_t	__FXP_BITFIELD8(late_scb:1,	/* 7 */
    205 				    direct_dma_dis:1,		/* 8,9 */
    206 				    tno_int_or_tco_en:1,	/* 7,9 */
    207 				    ci_int:1,
    208 				    ext_txcb_dis:1,		/* 8,9 */
    209 				    ext_stats_dis:1,		/* 8,9 */
    210 				    keep_overrun_rx:1,
    211 				    save_bf:1);
    212 /*7*/	volatile uint8_t	__FXP_BITFIELD6(disc_short_rx:1,
    213 				    underrun_retry:2,
    214 				    :2,
    215 				    ext_rfa:1,			/* 0 */
    216 				    two_frames:1,		/* 8,9 */
    217 				    dyn_tbd:1);			/* 8,9 */
    218 /*8*/	volatile uint8_t	__FXP_BITFIELD3(mediatype:1,	/* 7 */
    219 				    :6,
    220 				    csma_dis:1);		/* 8,9 */
    221 /*9*/	volatile uint8_t	__FXP_BITFIELD6(tcp_udp_cksum:1,/* 9 */
    222 				    :3,
    223 				    vlan_tco:1,			/* 8,9 */
    224 				    link_wake_en:1,		/* 8,9 */
    225 				    arp_wake_en:1,		/* 8 */
    226 				    mc_wake_en:1);		/* 8 */
    227 /*10*/	volatile uint8_t	__FXP_BITFIELD4(:3,
    228 				    nsai:1,
    229 				    preamble_length:2,
    230 				    loopback:2);
    231 /*11*/	volatile uint8_t	__FXP_BITFIELD2(linear_priority:3,/* 7 */
    232 				    :5);
    233 /*12*/	volatile uint8_t	__FXP_BITFIELD3(linear_pri_mode:1,/* 7 */
    234 				    :3,
    235 				    interfrm_spacing:4);
    236 /*13*/	volatile uint8_t	:8;
    237 /*14*/	volatile uint8_t	:8;
    238 /*15*/	volatile uint8_t	__FXP_BITFIELD8(promiscuous:1,
    239 				    bcast_disable:1,
    240 				    wait_after_win:1,		/* 8,9 */
    241 				    :1,
    242 				    ignore_ul:1,		/* 8,9 */
    243 				    crc16_en:1,			/* 9 */
    244 				    :1,
    245 				    crscdt:1);
    246 /*16*/	volatile uint8_t	fc_delay_lsb:8;			/* 8,9 */
    247 /*17*/	volatile uint8_t	fc_delay_msb:8;			/* 8,9 */
    248 /*18*/	volatile uint8_t	__FXP_BITFIELD6(stripping:1,
    249 				    padding:1,
    250 				    rcv_crc_xfer:1,
    251 				    long_rx_en:1,		/* 8,9 */
    252 				    pri_fc_thresh:3,		/* 8,9 */
    253 				    :1);
    254 /*19*/	volatile uint8_t	__FXP_BITFIELD8(ia_wake_en:1,	/* 8 */
    255 				    magic_pkt_dis:1,		/* 8,9,!9ER */
    256 				    tx_fc_dis:1,		/* 8,9 */
    257 				    rx_fc_restop:1,		/* 8,9 */
    258 				    rx_fc_restart:1,		/* 8,9 */
    259 				    fc_filter:1,		/* 8,9 */
    260 				    force_fdx:1,
    261 				    fdx_pin_en:1);
    262 /*20*/	volatile uint8_t	__FXP_BITFIELD4(:5,
    263 				    pri_fc_loc:1		/* 8,9 */,
    264 				    multi_ia:1,
    265 				    :1);
    266 /*21*/	volatile uint8_t	__FXP_BITFIELD3(:3, mc_all:1, :4);
    267 
    268 	/* Bytes 22 - 31 -- i82550 only */
    269 /*22*/	volatile uint8_t	__FXP_BITFIELD3(ext_rx_mode:1,
    270 				    vlan_drop_en:1,
    271 				    :6);
    272 	volatile uint8_t	reserved[9];
    273 };
    274 
    275 #define	FXP_CONFIG_LEN		22	/* i8255x */
    276 #define	FXP_EXT_CONFIG_LEN	32	/* i82550 */
    277 
    278 /*
    279  * Multicast setup command.
    280  */
    281 #define MAXMCADDR 80
    282 struct fxp_cb_mcs {
    283 	volatile uint16_t cb_status;
    284 	volatile uint16_t cb_command;
    285 	volatile uint32_t link_addr;
    286 	volatile uint16_t mc_cnt;
    287 	uint8_t mc_addr[MAXMCADDR][6];
    288 };
    289 
    290 #define	MAXUCODESIZE		192
    291 struct fxp_cb_ucode {
    292 	volatile uint16_t cb_status;
    293 	volatile uint16_t cb_command;
    294 	volatile uint32_t link_addr;
    295 	uint32_t ucode[MAXUCODESIZE];
    296 };
    297 
    298 struct fxp_ipcb {
    299 	/*
    300 	 * The following fields are valid only when
    301 	 * using the IPCB command block for TX checksum offload
    302 	 * (and TCP large send, VLANs, and (I think) IPsec). To use
    303 	 * them, you must enable extended TxCBs (available only
    304 	 * on the 82559 and later) and use the IPCBXMIT command.
    305 	 * Note that Intel defines the IPCB to be 32 bytes long,
    306 	 * the last 8 bytes of which comprise the first entry
    307 	 * in the TBD array. This means we only have to define
    308 	 * 8 extra bytes here.
    309          */
    310 	volatile uint16_t ipcb_schedule_low;
    311 	volatile uint8_t ipcb_ip_schedule;
    312 	volatile uint8_t ipcb_ip_activation_high;
    313 	volatile uint16_t ipcb_vlan_id;
    314 	volatile uint8_t ipcb_ip_header_offset;
    315 	volatile uint8_t ipcb_tcp_header_offset;
    316 };
    317 
    318 /*
    319  * IPCB field definitions
    320  */
    321 /* for ipcb_ip_schedule */
    322 #define FXP_IPCB_IP_CHECKSUM_ENABLE	0x10
    323 #define FXP_IPCB_TCPUDP_CHECKSUM_ENABLE	0x20
    324 #define FXP_IPCB_TCP_PACKET		0x40
    325 #define FXP_IPCB_LARGESEND_ENABLE	0x80
    326 /* for ipcb_ip_activation_high */
    327 #define FXP_IPCB_HARDWAREPARSING_ENABLE	0x01
    328 #define FXP_IPCB_INSERTVLAN_ENABLE	0x02
    329 
    330 /*
    331  * hardware ip4csum-tx on fxp(4) doesn't set IP checksums properly
    332  * if the TX IP packet length is 21 or 22 bytes and it requires autopadding.
    333  * To avoid this bug, we have to pad such very short packets manually.
    334  */
    335 #define FXP_IP4CSUMTX_MINLEN	22
    336 #define FXP_IP4CSUMTX_PADLEN	(ETHER_HDR_LEN + FXP_IP4CSUMTX_MINLEN)
    337 
    338 /*
    339  * Transmit command.
    340  */
    341 struct fxp_cb_tx {
    342 	volatile uint16_t cb_status;
    343 	volatile uint16_t cb_command;
    344 	volatile uint32_t link_addr;
    345 	volatile uint32_t tbd_array_addr;
    346 	volatile uint16_t byte_count;
    347 	volatile uint8_t tx_threshold;
    348 	volatile uint8_t tbd_number;
    349 	/*
    350 	 * If using the extended TxCB feature, there is a
    351 	 * two TBDs right here.  We handle this in the
    352 	 * fxp_control_data in i82557var.h.
    353 	 */
    354 };
    355 
    356 /*
    357  * Transmit buffer descriptors.
    358  */
    359 struct fxp_tbd {
    360 	volatile uint32_t tb_addr;
    361 	volatile uint32_t tb_size;
    362 };
    363 
    364 /*
    365  * Control Block (CB) definitions
    366  */
    367 
    368 /* status */
    369 #define FXP_CB_STATUS_OK	0x2000
    370 #define FXP_CB_STATUS_C		0x8000
    371 
    372 /* commands */
    373 #define FXP_CB_COMMAND_CMD	0x0007
    374 #define FXP_CB_COMMAND_NOP	0x0
    375 #define FXP_CB_COMMAND_IAS	0x1
    376 #define FXP_CB_COMMAND_CONFIG	0x2
    377 #define FXP_CB_COMMAND_MCAS	0x3
    378 #define FXP_CB_COMMAND_XMIT	0x4
    379 #define FXP_CB_COMMAND_UCODE	0x5
    380 #define FXP_CB_COMMAND_DUMP	0x6
    381 #define FXP_CB_COMMAND_DIAG	0x7
    382 #define FXP_CB_COMMAND_IPCBXMIT	0x9
    383 
    384 /* command flags */
    385 #define FXP_CB_COMMAND_SF	0x0008	/* simple/flexible mode */
    386 #define FXP_CB_COMMAND_I	0x2000	/* generate interrupt on completion */
    387 #define FXP_CB_COMMAND_S	0x4000	/* suspend on completion */
    388 #define FXP_CB_COMMAND_EL	0x8000	/* end of list */
    389 
    390 /*
    391  * Receive Frame Area.
    392  *
    393  * NOTE!  The RFA will NOT be aligned on a 4-byte boundary in the DMA
    394  * area!  To prevent EGCS from optimizing the copy of link_addr and
    395  * rbd_addr (which would cause an unaligned access fault on RISC systems),
    396  * we must make them an array of bytes!
    397  */
    398 struct fxp_rfa {
    399 	/* Fields common to all i8255x chips. */
    400 	volatile uint16_t rfa_status;
    401 	volatile uint16_t rfa_control;
    402 	volatile uint8_t link_addr[4];
    403 	volatile uint8_t rbd_addr[4];
    404 	volatile uint16_t actual_size;
    405 	volatile uint16_t size;
    406 
    407 	/* Fields available only on the i82550/i82551 in extended RFD mode. */
    408 	volatile uint16_t vlan_id;
    409 	volatile uint8_t rx_parse_stat;
    410 	volatile uint8_t reserved;
    411 	volatile uint16_t security_stat;
    412 	volatile uint8_t cksum_stat;
    413 	volatile uint8_t zerocopy_stat;
    414 	volatile uint8_t unused[8];
    415 };
    416 
    417 #define	RFA_SIZE		16
    418 #define	RFA_EXT_SIZE		32
    419 
    420 #define FXP_RFA_STATUS_RCOL	0x0001	/* receive collision */
    421 #define FXP_RFA_STATUS_IAMATCH	0x0002	/* 0 = matches station address */
    422 #define FXP_RFA_STATUS_NOAMATCH	0x0004	/* 1 = doesn't match anything */
    423 #define FXP_RFA_STATUS_PARSE	0x0008	/* pkt parse ok (82550/1 only) */
    424 #define FXP_RFA_STATUS_S4	0x0010	/* receive error from PHY */
    425 #define FXP_RFA_STATUS_TL	0x0020	/* type/length */
    426 #define FXP_RFA_STATUS_FTS	0x0080	/* frame too short */
    427 #define FXP_RFA_STATUS_OVERRUN	0x0100	/* DMA overrun */
    428 #define FXP_RFA_STATUS_RNR	0x0200	/* no resources */
    429 #define FXP_RFA_STATUS_ALIGN	0x0400	/* alignment error */
    430 #define FXP_RFA_STATUS_CRC	0x0800	/* CRC error */
    431 #define FXP_RFA_STATUS_VLAN	0x1000	/* VLAN */
    432 #define FXP_RFA_STATUS_OK	0x2000	/* packet received okay */
    433 #define FXP_RFA_STATUS_C	0x8000	/* packet reception complete */
    434 
    435 #define FXP_RFA_CONTROL_SF	0x0008	/* simple/flexible memory mode */
    436 #define FXP_RFA_CONTROL_H	0x0010	/* header RFD */
    437 #define FXP_RFA_CONTROL_S	0x4000	/* suspend after reception */
    438 #define FXP_RFA_CONTROL_EL	0x8000	/* end of list */
    439 
    440 /* Bits in the 'cksum_stat' byte */
    441 #define FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID	0x10
    442 #define FXP_RFDX_CS_TCPUDP_CSUM_VALID		0x20
    443 #define FXP_RFDX_CS_IP_CSUM_BIT_VALID		0x01
    444 #define FXP_RFDX_CS_IP_CSUM_VALID		0x02
    445 
    446 /* Bits in the 'rx_parse_stat' byte */
    447 #define FXP_RFDX_P_PARSE_BIT			0x08
    448 #define FXP_RFDX_P_CSUM_PROTOCOL_MASK		0x03
    449 #define FXP_RFDX_P_TCP_PACKET			0x00
    450 #define FXP_RFDX_P_UDP_PACKET			0x01
    451 #define FXP_RFDX_P_IP_PACKET			0x03
    452 
    453 /*
    454  * Statistics dump area definitions
    455  */
    456 struct fxp_stats {
    457 	volatile uint32_t tx_good;
    458 	volatile uint32_t tx_maxcols;
    459 	volatile uint32_t tx_latecols;
    460 	volatile uint32_t tx_underruns;
    461 	volatile uint32_t tx_lostcrs;
    462 	volatile uint32_t tx_deferred;
    463 	volatile uint32_t tx_single_collisions;
    464 	volatile uint32_t tx_multiple_collisions;
    465 	volatile uint32_t tx_total_collisions;
    466 	volatile uint32_t rx_good;
    467 	volatile uint32_t rx_crc_errors;
    468 	volatile uint32_t rx_alignment_errors;
    469 	volatile uint32_t rx_rnr_errors;
    470 	volatile uint32_t rx_overrun_errors;
    471 	volatile uint32_t rx_cdt_errors;
    472 	volatile uint32_t rx_shortframes;
    473 	volatile uint32_t tx_pauseframes;
    474 #define	completion_status	tx_pauseframes
    475 	volatile uint32_t rx_pauseframes;
    476 	volatile uint32_t rx_unsupportedframes;
    477 	volatile uint32_t tx_tco_frames;
    478 	volatile uint32_t rx_tco_frames;
    479 	volatile uint32_t ext_completion_status;
    480 };
    481 #define FXP_STATS_DUMP_COMPLETE	0xa005
    482 #define FXP_STATS_DR_COMPLETE	0xa007
    483 
    484 /*
    485  * Serial EEPROM control register bits
    486  */
    487 #define FXP_EEPROM_EESK		0x01		/* shift clock */
    488 #define FXP_EEPROM_EECS		0x02		/* chip select */
    489 #define FXP_EEPROM_EEDI		0x04		/* data in */
    490 #define FXP_EEPROM_EEDO		0x08		/* data out */
    491 
    492 /*
    493  * Serial EEPROM opcodes, including start bit
    494  */
    495 #define FXP_EEPROM_OPC_ERASE	0x4
    496 #define FXP_EEPROM_OPC_WRITE	0x5
    497 #define FXP_EEPROM_OPC_READ	0x6
    498 
    499 /*
    500  * Management Data Interface opcodes
    501  */
    502 #define FXP_MDI_WRITE		0x1
    503 #define FXP_MDI_READ		0x2
    504 
    505 /*
    506  * PHY device types (from EEPROM)
    507  */
    508 #define	FXP_PHY_DEVICE_MASK	0x3f00
    509 #define	FXP_PHY_DEVICE_SHIFT	8
    510 #define	FXP_PHY_DEVADDR_MASK	0x00ff
    511 #define	FXP_PHY_SERIAL_ONLY	0x8000
    512 #define FXP_PHY_NONE		0
    513 #define FXP_PHY_82553A		1
    514 #define FXP_PHY_82553C		2
    515 #define FXP_PHY_82503		3
    516 #define FXP_PHY_DP83840		4
    517 #define FXP_PHY_80C240		5
    518 #define FXP_PHY_80C24		6
    519 #define FXP_PHY_82555		7
    520 #define FXP_PHY_DP83840A	10
    521 #define	FXP_PHY_DP82555B	11
    522 
    523 /*
    524  * PCI revisions.
    525  */
    526 #define	FXP_REV_82558_A4	4
    527 #define	FXP_REV_82558_B0	5
    528 #define	FXP_REV_82559_A0	8
    529 #define	FXP_REV_82559S_A	9
    530 #define	FXP_REV_82550		12
    531 #define	FXP_REV_82550_C		13
    532 #define	FXP_REV_82551_E		14	/* 82551 */
    533 #define	FXP_REV_82551_F		15
    534 #define	FXP_REV_82551_10	16	/* 82551 */
    535