1 /* $NetBSD: g1bus_bus_mem.c,v 1.1 2016/12/29 11:49:05 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Bus space implementation for the SEGA G1 bus, for GD-ROM and IDE port. 34 */ 35 36 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 37 __KERNEL_RCSID(0, "$NetBSD: g1bus_bus_mem.c,v 1.1 2016/12/29 11:49:05 tsutsui Exp $"); 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/device.h> 42 #include <sys/bus.h> 43 44 #include <machine/cpu.h> 45 46 #include <dreamcast/dev/g1/g1busvar.h> 47 48 int g1bus_bus_mem_map(void *, bus_addr_t, bus_size_t, int, 49 bus_space_handle_t *); 50 void g1bus_bus_mem_unmap(void *, bus_space_handle_t, bus_size_t); 51 int g1bus_bus_mem_subregion(void *, bus_space_handle_t, bus_size_t, 52 bus_size_t, bus_space_handle_t *); 53 paddr_t g1bus_bus_mem_mmap(void *, bus_addr_t, off_t, int, int); 54 55 uint8_t g1bus_bus_mem_read_1(void *, bus_space_handle_t, bus_size_t); 56 uint16_t g1bus_bus_mem_read_2(void *, bus_space_handle_t, bus_size_t); 57 uint32_t g1bus_bus_mem_read_4(void *, bus_space_handle_t, bus_size_t); 58 59 void g1bus_bus_mem_write_1(void *, bus_space_handle_t, bus_size_t, 60 uint8_t); 61 void g1bus_bus_mem_write_2(void *, bus_space_handle_t, bus_size_t, 62 uint16_t); 63 void g1bus_bus_mem_write_4(void *, bus_space_handle_t, bus_size_t, 64 uint32_t); 65 66 void g1bus_bus_mem_read_region_1(void *, bus_space_handle_t, bus_size_t, 67 uint8_t *, bus_size_t); 68 void g1bus_bus_mem_read_region_2(void *, bus_space_handle_t, bus_size_t, 69 uint16_t *, bus_size_t); 70 void g1bus_bus_mem_read_region_4(void *, bus_space_handle_t, bus_size_t, 71 uint32_t *, bus_size_t); 72 73 void g1bus_bus_mem_write_region_1(void *, bus_space_handle_t, bus_size_t, 74 const uint8_t *, bus_size_t); 75 void g1bus_bus_mem_write_region_2(void *, bus_space_handle_t, bus_size_t, 76 const uint16_t *, bus_size_t); 77 void g1bus_bus_mem_write_region_4(void *, bus_space_handle_t, bus_size_t, 78 const uint32_t *, bus_size_t); 79 80 void g1bus_bus_mem_set_region_4(void *, bus_space_handle_t, bus_size_t, 81 uint32_t, bus_size_t); 82 83 void g1bus_bus_mem_read_multi_1(void *, bus_space_handle_t, 84 bus_size_t, uint8_t *, bus_size_t); 85 void g1bus_bus_mem_read_multi_2(void *, bus_space_handle_t, 86 bus_size_t, uint16_t *, bus_size_t); 87 88 void g1bus_bus_mem_write_multi_1(void *, bus_space_handle_t, 89 bus_size_t, const uint8_t *, bus_size_t); 90 void g1bus_bus_mem_write_multi_2(void *, bus_space_handle_t, 91 bus_size_t, const uint16_t *, bus_size_t); 92 93 void 94 g1bus_bus_mem_init(struct g1bus_softc *sc) 95 { 96 bus_space_tag_t t = &sc->sc_memt; 97 98 memset(t, 0, sizeof(*t)); 99 100 t->dbs_map = g1bus_bus_mem_map; 101 t->dbs_unmap = g1bus_bus_mem_unmap; 102 t->dbs_subregion = g1bus_bus_mem_subregion; 103 t->dbs_mmap = g1bus_bus_mem_mmap; 104 105 t->dbs_r_1 = g1bus_bus_mem_read_1; 106 t->dbs_r_2 = g1bus_bus_mem_read_2; 107 t->dbs_r_4 = g1bus_bus_mem_read_4; 108 109 t->dbs_w_1 = g1bus_bus_mem_write_1; 110 t->dbs_w_2 = g1bus_bus_mem_write_2; 111 t->dbs_w_4 = g1bus_bus_mem_write_4; 112 113 t->dbs_rm_1 = g1bus_bus_mem_read_multi_1; 114 t->dbs_rm_2 = g1bus_bus_mem_read_multi_2; 115 116 t->dbs_wm_1 = g1bus_bus_mem_write_multi_1; 117 t->dbs_wm_2 = g1bus_bus_mem_write_multi_2; 118 119 t->dbs_rr_1 = g1bus_bus_mem_read_region_1; 120 t->dbs_rr_2 = g1bus_bus_mem_read_region_2; 121 t->dbs_rr_4 = g1bus_bus_mem_read_region_4; 122 123 t->dbs_wr_1 = g1bus_bus_mem_write_region_1; 124 t->dbs_wr_2 = g1bus_bus_mem_write_region_2; 125 t->dbs_wr_4 = g1bus_bus_mem_write_region_4; 126 127 t->dbs_sr_4 = g1bus_bus_mem_set_region_4; 128 } 129 130 int 131 g1bus_bus_mem_map(void *v, bus_addr_t addr, bus_size_t size, int flags, 132 bus_space_handle_t *shp) 133 { 134 135 KASSERT((addr & SH3_PHYS_MASK) == addr); 136 *shp = SH3_PHYS_TO_P2SEG(addr); 137 138 return 0; 139 } 140 141 void 142 g1bus_bus_mem_unmap(void *v, bus_space_handle_t sh, bus_size_t size) 143 { 144 145 KASSERT(sh >= SH3_P2SEG_BASE && sh <= SH3_P2SEG_END); 146 /* Nothing to do. */ 147 } 148 149 int 150 g1bus_bus_mem_subregion(void *v, bus_space_handle_t handle, bus_size_t offset, 151 bus_size_t size, bus_space_handle_t *nhandlep) 152 { 153 154 *nhandlep = handle + offset; 155 return 0; 156 } 157 158 paddr_t 159 g1bus_bus_mem_mmap(void *v, bus_addr_t addr, off_t offset, int prot, int flags) 160 { 161 162 /* XXX not implemented */ 163 return -1; 164 } 165 166 uint8_t 167 g1bus_bus_mem_read_1(void *v, bus_space_handle_t sh, bus_size_t off) 168 { 169 uint8_t rv; 170 171 rv = *(volatile uint8_t *)(sh + off); 172 173 return rv; 174 } 175 176 uint16_t 177 g1bus_bus_mem_read_2(void *v, bus_space_handle_t sh, bus_size_t off) 178 { 179 uint16_t rv; 180 181 rv = *(volatile uint16_t *)(sh + off); 182 183 return rv; 184 } 185 186 uint32_t 187 g1bus_bus_mem_read_4(void *v, bus_space_handle_t sh, bus_size_t off) 188 { 189 uint32_t rv; 190 191 rv = *(volatile uint32_t *)(sh + off); 192 193 return rv; 194 } 195 196 void 197 g1bus_bus_mem_write_1(void *v, bus_space_handle_t sh, bus_size_t off, 198 uint8_t val) 199 { 200 201 *(volatile uint8_t *)(sh + off) = val; 202 } 203 204 void 205 g1bus_bus_mem_write_2(void *v, bus_space_handle_t sh, bus_size_t off, 206 uint16_t val) 207 { 208 209 *(volatile uint16_t *)(sh + off) = val; 210 } 211 212 void 213 g1bus_bus_mem_write_4(void *v, bus_space_handle_t sh, bus_size_t off, 214 uint32_t val) 215 { 216 217 *(volatile uint32_t *)(sh + off) = val; 218 } 219 220 void 221 g1bus_bus_mem_read_multi_1(void *v, bus_space_handle_t sh, 222 bus_size_t off, uint8_t *addr, bus_size_t len) 223 { 224 volatile const uint8_t *baddr = (uint8_t *)(sh + off); 225 226 while (len--) 227 *addr++ = *baddr; 228 } 229 230 void 231 g1bus_bus_mem_read_multi_2(void *v, bus_space_handle_t sh, 232 bus_size_t off, uint16_t *addr, bus_size_t len) 233 { 234 volatile uint16_t *baddr = (uint16_t *)(sh + off); 235 236 while (len--) 237 *addr++ = *baddr; 238 } 239 240 void 241 g1bus_bus_mem_write_multi_1(void *v, bus_space_handle_t sh, 242 bus_size_t off, const uint8_t *addr, bus_size_t len) 243 { 244 volatile uint8_t *baddr = (uint8_t *)(sh + off); 245 246 while (len--) 247 *baddr = *addr++; 248 } 249 250 void 251 g1bus_bus_mem_write_multi_2(void *v, bus_space_handle_t sh, 252 bus_size_t off, const uint16_t *addr, bus_size_t len) 253 { 254 volatile uint16_t *baddr = (uint16_t *)(sh + off); 255 256 while (len--) 257 *baddr = *addr++; 258 } 259 260 void 261 g1bus_bus_mem_read_region_1(void *v, bus_space_handle_t sh, bus_size_t off, 262 uint8_t *addr, bus_size_t len) 263 { 264 volatile const uint8_t *baddr = (uint8_t *)(sh + off); 265 266 while (len--) 267 *addr++ = *baddr++; 268 } 269 270 void 271 g1bus_bus_mem_read_region_2(void *v, bus_space_handle_t sh, bus_size_t off, 272 uint16_t *addr, bus_size_t len) 273 { 274 volatile const uint16_t *baddr = (uint16_t *)(sh + off); 275 276 while (len--) 277 *addr++ = *baddr++; 278 } 279 280 void 281 g1bus_bus_mem_read_region_4(void *v, bus_space_handle_t sh, bus_size_t off, 282 uint32_t *addr, bus_size_t len) 283 { 284 volatile const uint32_t *baddr = (uint32_t *)(sh + off); 285 286 while (len--) 287 *addr++ = *baddr++; 288 } 289 290 void 291 g1bus_bus_mem_write_region_1(void *v, bus_space_handle_t sh, bus_size_t off, 292 const uint8_t *addr, bus_size_t len) 293 { 294 volatile uint8_t *baddr = (uint8_t *)(sh + off); 295 296 while (len--) 297 *baddr++ = *addr++; 298 } 299 300 void 301 g1bus_bus_mem_write_region_2(void *v, bus_space_handle_t sh, bus_size_t off, 302 const uint16_t *addr, bus_size_t len) 303 { 304 volatile uint16_t *baddr = (uint16_t *)(sh + off); 305 306 while (len--) 307 *baddr++ = *addr++; 308 } 309 310 void 311 g1bus_bus_mem_write_region_4(void *v, bus_space_handle_t sh, bus_size_t off, 312 const uint32_t *addr, bus_size_t len) 313 { 314 volatile uint32_t *baddr = (uint32_t *)(sh + off); 315 316 while (len--) 317 *baddr++ = *addr++; 318 } 319 320 void 321 g1bus_bus_mem_set_region_4(void *v, bus_space_handle_t sh, bus_size_t off, 322 uint32_t val, bus_size_t len) 323 { 324 volatile uint32_t *baddr = (uint32_t *)(sh + off); 325 326 while (len--) 327 *baddr++ = val; 328 } 329
Indexes created Sat Sep 27 14:09:57 GMT 2025