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      1 /*	$NetBSD: nouveau_nvkm_engine_cipher_g84.c,v 1.3 2021/12/18 23:45:34 riastradh Exp $	*/
      2 
      3 /*
      4  * Copyright 2012 Red Hat Inc.
      5  *
      6  * Permission is hereby granted, free of charge, to any person obtaining a
      7  * copy of this software and associated documentation files (the "Software"),
      8  * to deal in the Software without restriction, including without limitation
      9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
     10  * and/or sell copies of the Software, and to permit persons to whom the
     11  * Software is furnished to do so, subject to the following conditions:
     12  *
     13  * The above copyright notice and this permission notice shall be included in
     14  * all copies or substantial portions of the Software.
     15  *
     16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     22  * OTHER DEALINGS IN THE SOFTWARE.
     23  *
     24  * Authors: Ben Skeggs
     25  */
     26 #include <sys/cdefs.h>
     27 __KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_engine_cipher_g84.c,v 1.3 2021/12/18 23:45:34 riastradh Exp $");
     28 
     29 #include <engine/cipher.h>
     30 #include <engine/fifo.h>
     31 
     32 #include <core/client.h>
     33 #include <core/enum.h>
     34 #include <core/gpuobj.h>
     35 
     36 #include <nvif/class.h>
     37 
     38 static int
     39 g84_cipher_oclass_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent,
     40 		       int align, struct nvkm_gpuobj **pgpuobj)
     41 {
     42 	int ret = nvkm_gpuobj_new(object->engine->subdev.device, 16,
     43 				  align, false, parent, pgpuobj);
     44 	if (ret == 0) {
     45 		nvkm_kmap(*pgpuobj);
     46 		nvkm_wo32(*pgpuobj, 0x00, object->oclass);
     47 		nvkm_wo32(*pgpuobj, 0x04, 0x00000000);
     48 		nvkm_wo32(*pgpuobj, 0x08, 0x00000000);
     49 		nvkm_wo32(*pgpuobj, 0x0c, 0x00000000);
     50 		nvkm_done(*pgpuobj);
     51 	}
     52 	return ret;
     53 }
     54 
     55 static const struct nvkm_object_func
     56 g84_cipher_oclass_func = {
     57 	.bind = g84_cipher_oclass_bind,
     58 };
     59 
     60 static int
     61 g84_cipher_cclass_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent,
     62 		       int align, struct nvkm_gpuobj **pgpuobj)
     63 {
     64 	return nvkm_gpuobj_new(object->engine->subdev.device, 256,
     65 			       align, true, parent, pgpuobj);
     66 
     67 }
     68 
     69 static const struct nvkm_object_func
     70 g84_cipher_cclass = {
     71 	.bind = g84_cipher_cclass_bind,
     72 };
     73 
     74 static const struct nvkm_bitfield
     75 g84_cipher_intr_mask[] = {
     76 	{ 0x00000001, "INVALID_STATE" },
     77 	{ 0x00000002, "ILLEGAL_MTHD" },
     78 	{ 0x00000004, "ILLEGAL_CLASS" },
     79 	{ 0x00000080, "QUERY" },
     80 	{ 0x00000100, "FAULT" },
     81 	{}
     82 };
     83 
     84 static void
     85 g84_cipher_intr(struct nvkm_engine *cipher)
     86 {
     87 	struct nvkm_subdev *subdev = &cipher->subdev;
     88 	struct nvkm_device *device = subdev->device;
     89 	struct nvkm_fifo *fifo = device->fifo;
     90 	struct nvkm_fifo_chan *chan;
     91 	u32 stat = nvkm_rd32(device, 0x102130);
     92 	u32 mthd = nvkm_rd32(device, 0x102190);
     93 	u32 data = nvkm_rd32(device, 0x102194);
     94 	u32 inst = nvkm_rd32(device, 0x102188) & 0x7fffffff;
     95 	unsigned long flags;
     96 	char msg[128];
     97 
     98 	chan = nvkm_fifo_chan_inst(fifo, (u64)inst << 12, &flags);
     99 	if (stat) {
    100 		nvkm_snprintbf(msg, sizeof(msg), g84_cipher_intr_mask, stat);
    101 		nvkm_error(subdev,  "%08x [%s] ch %d [%010"PRIx64" %s] "
    102 				    "mthd %04x data %08x\n", stat, msg,
    103 			   chan ? chan->chid : -1, (u64)inst << 12,
    104 			   chan ? chan->object.client->name : "unknown",
    105 			   mthd, data);
    106 	}
    107 	nvkm_fifo_chan_put(fifo, flags, &chan);
    108 
    109 	nvkm_wr32(device, 0x102130, stat);
    110 	nvkm_wr32(device, 0x10200c, 0x10);
    111 }
    112 
    113 static int
    114 g84_cipher_init(struct nvkm_engine *cipher)
    115 {
    116 	struct nvkm_device *device = cipher->subdev.device;
    117 	nvkm_wr32(device, 0x102130, 0xffffffff);
    118 	nvkm_wr32(device, 0x102140, 0xffffffbf);
    119 	nvkm_wr32(device, 0x10200c, 0x00000010);
    120 	return 0;
    121 }
    122 
    123 static const struct nvkm_engine_func
    124 g84_cipher = {
    125 	.init = g84_cipher_init,
    126 	.intr = g84_cipher_intr,
    127 	.cclass = &g84_cipher_cclass,
    128 	.sclass = {
    129 		{ -1, -1, NV74_CIPHER, &g84_cipher_oclass_func },
    130 		{}
    131 	}
    132 };
    133 
    134 int
    135 g84_cipher_new(struct nvkm_device *device, int index,
    136 	       struct nvkm_engine **pengine)
    137 {
    138 	return nvkm_engine_new_(&g84_cipher, device, index, true, pengine);
    139 }
    140