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    Searched defs:getRegClass (Results 1 - 9 of 9) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
MachineIRBuilder.h 104 const TargetRegisterClass *getRegClass() const {
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
MachineRegisterInfo.h 219 return shouldTrackSubRegLiveness(*getRegClass(VReg));
587 /// constrainRegClass(ToReg, getRegClass(FromReg))
590 /// *MRI.getRegClass(FromReg), MRI)
634 const TargetRegisterClass *getRegClass(Register Reg) const {
650 /// the select pass, using getRegClass is safe.
1202 const TargetRegisterClass *RC = MRI->getRegClass(RegUnit);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/MIRParser/
MIParser.cpp 281 const auto *RC = TRI->getRegClass(I);
305 PerTargetMIParsingState::getRegClass(StringRef Name) {
1333 const TargetRegisterClass *RC = PFS.Target.getRegClass(Name);
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86InstructionSelector.cpp 128 const TargetRegisterClass *getRegClass(LLT Ty, const RegisterBank &RB) const;
129 const TargetRegisterClass *getRegClass(LLT Ty, unsigned Reg,
170 X86InstructionSelector::getRegClass(LLT Ty, const RegisterBank &RB) const {
198 X86InstructionSelector::getRegClass(LLT Ty, unsigned Reg,
201 return getRegClass(Ty, RegBank);
249 getRegClass(MRI.getType(SrcReg), SrcRegBank);
279 getRegClass(MRI.getType(DstReg), DstRegBank);
728 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstRB);
729 const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcRB);
814 MRI.createVirtualRegister(getRegClass(DstTy, DstReg, MRI))
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
TargetInstrInfo.cpp 47 TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum,
62 return TRI->getRegClass(RegClass);
463 const TargetRegisterClass *RC = MRI.getRegClass(FoldReg);
468 if (RC->hasSubClassEq(MRI.getRegClass(LiveReg)))
538 MF.getRegInfo().getRegClass(MO.getReg());
1402 OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID));
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIRegisterInfo.cpp 2071 RC = MRI.getRegClass(Reg);
2239 return Reg.isVirtual() ? MRI.getRegClass(Reg) : getPhysRegClass(Reg);
2367 SIRegisterInfo::getRegClass(unsigned RCID) const {
2377 return AMDGPUGenRegisterInfo::getRegClass(RCID);
SIInstrInfo.cpp 988 const TargetRegisterClass *RegClass = MRI.getRegClass(DestReg);
1052 RI.getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
1053 assert(MRI.getRegClass(DstReg) == &AMDGPU::VGPR_32RegClass &&
2501 const TargetRegisterClass *RC = MRI.getRegClass(TrueReg);
2502 if (MRI.getRegClass(FalseReg) != RC)
2516 const TargetRegisterClass *RC = MRI.getRegClass(TrueReg);
2517 if (MRI.getRegClass(FalseReg) != RC)
2545 const TargetRegisterClass *DstRC = MRI.getRegClass(DstReg);
2788 if (!Src1->isReg() || RI.isSGPRClass(MRI->getRegClass(Src1->getReg())))
2791 if (!Src2->isReg() || RI.isSGPRClass(MRI->getRegClass(Src2->getReg()))
    [all...]
  /src/external/apache2/llvm/dist/llvm/utils/TableGen/
CodeGenRegisters.cpp 1274 CodeGenRegisterClass *CodeGenRegBank::getRegClass(const Record *Def) const {
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AsmParser/
AMDGPUAsmParser.cpp 1898 return isRegKind() && AsmParser->getMRI()->getRegClass(RCID).contains(getReg());
2184 static int getRegClass(RegisterKind Is, unsigned RegWidth) {
2453 int RCID = getRegClass(RegKind, RegWidth);
2460 const MCRegisterClass RC = TRI->getRegClass(RCID);
4051 const MCRegisterClass &AGRP32 = MRI->getRegClass(AMDGPU::AGPR_32RegClassID);
4091 const MCRegisterClass &VGRP32 = MRI->getRegClass(AMDGPU::VGPR_32RegClassID);
4092 const MCRegisterClass &AGRP32 = MRI->getRegClass(AMDGPU::AGPR_32RegClassID);

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