1 //===-- X86RegisterInfo.h - X86 Register Information Impl -------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the X86 implementation of the TargetRegisterInfo class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_X86_X86REGISTERINFO_H 14 #define LLVM_LIB_TARGET_X86_X86REGISTERINFO_H 15 16 #include "llvm/CodeGen/TargetRegisterInfo.h" 17 18 #define GET_REGINFO_HEADER 19 #include "X86GenRegisterInfo.inc" 20 21 namespace llvm { 22 class Triple; 23 24 class X86RegisterInfo final : public X86GenRegisterInfo { 25 private: 26 /// Is64Bit - Is the target 64-bits. 27 /// 28 bool Is64Bit; 29 30 /// IsWin64 - Is the target on of win64 flavours 31 /// 32 bool IsWin64; 33 34 /// SlotSize - Stack slot size in bytes. 35 /// 36 unsigned SlotSize; 37 38 /// StackPtr - X86 physical register used as stack ptr. 39 /// 40 unsigned StackPtr; 41 42 /// FramePtr - X86 physical register used as frame ptr. 43 /// 44 unsigned FramePtr; 45 46 /// BasePtr - X86 physical register used as a base ptr in complex stack 47 /// frames. I.e., when we need a 3rd base, not just SP and FP, due to 48 /// variable size stack objects. 49 unsigned BasePtr; 50 51 public: 52 explicit X86RegisterInfo(const Triple &TT); 53 54 // FIXME: This should be tablegen'd like getDwarfRegNum is 55 int getSEHRegNum(unsigned i) const; 56 57 /// getMatchingSuperRegClass - Return a subclass of the specified register 58 /// class A so that each register in it has a sub-register of the 59 /// specified sub-register index which is in the specified register class B. 60 const TargetRegisterClass * 61 getMatchingSuperRegClass(const TargetRegisterClass *A, 62 const TargetRegisterClass *B, 63 unsigned Idx) const override; 64 65 const TargetRegisterClass * 66 getSubClassWithSubReg(const TargetRegisterClass *RC, 67 unsigned Idx) const override; 68 69 const TargetRegisterClass * 70 getLargestLegalSuperClass(const TargetRegisterClass *RC, 71 const MachineFunction &MF) const override; 72 73 bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC, 74 unsigned DefSubReg, 75 const TargetRegisterClass *SrcRC, 76 unsigned SrcSubReg) const override; 77 78 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer 79 /// values. 80 const TargetRegisterClass * 81 getPointerRegClass(const MachineFunction &MF, 82 unsigned Kind = 0) const override; 83 84 /// getCrossCopyRegClass - Returns a legal register class to copy a register 85 /// in the specified class to or from. Returns NULL if it is possible to copy 86 /// between a two registers of the specified class. 87 const TargetRegisterClass * 88 getCrossCopyRegClass(const TargetRegisterClass *RC) const override; 89 90 /// getGPRsForTailCall - Returns a register class with registers that can be 91 /// used in forming tail calls. 92 const TargetRegisterClass * 93 getGPRsForTailCall(const MachineFunction &MF) const; 94 95 unsigned getRegPressureLimit(const TargetRegisterClass *RC, 96 MachineFunction &MF) const override; 97 98 /// getCalleeSavedRegs - Return a null-terminated list of all of the 99 /// callee-save registers on this target. 100 const MCPhysReg * 101 getCalleeSavedRegs(const MachineFunction* MF) const override; 102 const MCPhysReg * 103 getCalleeSavedRegsViaCopy(const MachineFunction *MF) const; 104 const uint32_t *getCallPreservedMask(const MachineFunction &MF, 105 CallingConv::ID) const override; 106 const uint32_t *getNoPreservedMask() const override; 107 108 // Calls involved in thread-local variable lookup save more registers than 109 // normal calls, so they need a different mask to represent this. 110 const uint32_t *getDarwinTLSCallPreservedMask() const; 111 112 /// getReservedRegs - Returns a bitset indexed by physical register number 113 /// indicating if a register is a special register that has particular uses and 114 /// should be considered unavailable at all times, e.g. SP, RA. This is used by 115 /// register scavenger to determine what registers are free. 116 BitVector getReservedRegs(const MachineFunction &MF) const override; 117 118 void adjustStackMapLiveOutMask(uint32_t *Mask) const override; 119 120 bool hasBasePointer(const MachineFunction &MF) const; 121 122 bool canRealignStack(const MachineFunction &MF) const override; 123 124 void eliminateFrameIndex(MachineBasicBlock::iterator MI, 125 int SPAdj, unsigned FIOperandNum, 126 RegScavenger *RS = nullptr) const override; 127 128 /// findDeadCallerSavedReg - Return a caller-saved register that isn't live 129 /// when it reaches the "return" instruction. We can then pop a stack object 130 /// to this register without worry about clobbering it. 131 unsigned findDeadCallerSavedReg(MachineBasicBlock &MBB, 132 MachineBasicBlock::iterator &MBBI) const; 133 134 // Debug information queries. 135 Register getFrameRegister(const MachineFunction &MF) const override; 136 unsigned getPtrSizedFrameRegister(const MachineFunction &MF) const; 137 unsigned getPtrSizedStackRegister(const MachineFunction &MF) const; 138 Register getStackRegister() const { return StackPtr; } 139 Register getBaseRegister() const { return BasePtr; } 140 /// Returns physical register used as frame pointer. 141 /// This will always returns the frame pointer register, contrary to 142 /// getFrameRegister() which returns the "base pointer" in situations 143 /// involving a stack, frame and base pointer. 144 Register getFramePtr() const { return FramePtr; } 145 // FIXME: Move to FrameInfok 146 unsigned getSlotSize() const { return SlotSize; } 147 148 bool getRegAllocationHints(Register VirtReg, ArrayRef<MCPhysReg> Order, 149 SmallVectorImpl<MCPhysReg> &Hints, 150 const MachineFunction &MF, const VirtRegMap *VRM, 151 const LiveRegMatrix *Matrix) const override; 152 }; 153 154 } // End llvm namespace 155 156 #endif 157
Indexes created Sun Jun 21 00:25:28 UTC 2026