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    Searched defs:getSubReg (Results 1 - 5 of 5) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/MC/
MCRegisterInfo.cpp 27 if (RC->contains(*Supers) && Reg == getSubReg(*Supers, SubIdx))
32 MCRegister MCRegisterInfo::getSubReg(MCRegister Reg, unsigned Idx) const {
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
TargetRegisterInfo.h 1092 inline MCRegister getSubReg(MCRegister Reg, unsigned Idx) const {
1093 return static_cast<const MCRegisterInfo *>(this)->getSubReg(Reg, Idx);
1135 unsigned getSubReg() const { return SubReg; }
1137 /// Returns the bit mask of register classes that getSubReg() projects into
MachineOperand.h 365 unsigned getSubReg() const {
460 return !isUndef() && !isInternalRead() && (isUse() || getSubReg());
  /src/external/apache2/llvm/dist/llvm/include/llvm/MC/
MCRegisterInfo.h 461 MCRegister getSubReg(MCRegister Reg, unsigned Idx) const;
620 MCRegister getSubReg() const {
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonHardwareLoops.cpp 349 unsigned getSubReg() const {
890 SR = Start->getSubReg();
893 SR = End->getSubReg();
908 DistSR = End->getSubReg();
919 SubIB.addReg(End->getReg(), 0, End->getSubReg())
920 .addReg(Start->getReg(), 0, Start->getSubReg());
923 .addReg(Start->getReg(), 0, Start->getSubReg());
931 EndValInstr->getOperand(1).getSubReg() == 0 &&
938 SubIB.addReg(End->getReg(), 0, End->getSubReg())
1250 .addReg(TripCount->getReg(), 0, TripCount->getSubReg());
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