1 /* $NetBSD: hw_sequencer_private.h,v 1.2 2021/12/18 23:45:05 riastradh Exp $ */ 2 3 /* 4 * Copyright 2015 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: AMD 25 * 26 */ 27 28 #ifndef __DC_HW_SEQUENCER_PRIVATE_H__ 29 #define __DC_HW_SEQUENCER_PRIVATE_H__ 30 31 #include "dc_types.h" 32 33 enum pipe_gating_control { 34 PIPE_GATING_CONTROL_DISABLE = 0, 35 PIPE_GATING_CONTROL_ENABLE, 36 PIPE_GATING_CONTROL_INIT 37 }; 38 39 struct dce_hwseq_wa { 40 bool blnd_crtc_trigger; 41 bool DEGVIDCN10_253; 42 bool false_optc_underflow; 43 bool DEGVIDCN10_254; 44 bool DEGVIDCN21; 45 }; 46 47 struct hwseq_wa_state { 48 bool DEGVIDCN10_253_applied; 49 }; 50 51 struct pipe_ctx; 52 struct dc_state; 53 struct dc_stream_status; 54 struct dc_writeback_info; 55 struct dchub_init_data; 56 struct dc_static_screen_params; 57 struct resource_pool; 58 struct resource_context; 59 struct stream_resource; 60 struct dc_phy_addr_space_config; 61 struct dc_virtual_addr_space_config; 62 struct hubp; 63 struct dpp; 64 struct dce_hwseq; 65 struct timing_generator; 66 struct tg_color; 67 struct output_pixel_processor; 68 69 struct hwseq_private_funcs { 70 71 void (*disable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx); 72 void (*enable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx); 73 void (*init_pipes)(struct dc *dc, struct dc_state *context); 74 void (*reset_hw_ctx_wrap)(struct dc *dc, struct dc_state *context); 75 void (*update_plane_addr)(const struct dc *dc, 76 struct pipe_ctx *pipe_ctx); 77 void (*plane_atomic_disconnect)(struct dc *dc, 78 struct pipe_ctx *pipe_ctx); 79 void (*update_mpcc)(struct dc *dc, struct pipe_ctx *pipe_ctx); 80 bool (*set_input_transfer_func)(struct dc *dc, 81 struct pipe_ctx *pipe_ctx, 82 const struct dc_plane_state *plane_state); 83 bool (*set_output_transfer_func)(struct dc *dc, 84 struct pipe_ctx *pipe_ctx, 85 const struct dc_stream_state *stream); 86 void (*power_down)(struct dc *dc); 87 void (*enable_display_pipe_clock_gating)(struct dc_context *ctx, 88 bool clock_gating); 89 bool (*enable_display_power_gating)(struct dc *dc, 90 uint8_t controller_id, 91 struct dc_bios *dcb, 92 enum pipe_gating_control power_gating); 93 void (*blank_pixel_data)(struct dc *dc, 94 struct pipe_ctx *pipe_ctx, 95 bool blank); 96 enum dc_status (*enable_stream_timing)( 97 struct pipe_ctx *pipe_ctx, 98 struct dc_state *context, 99 struct dc *dc); 100 void (*edp_backlight_control)(struct dc_link *link, 101 bool enable); 102 void (*setup_vupdate_interrupt)(struct dc *dc, 103 struct pipe_ctx *pipe_ctx); 104 bool (*did_underflow_occur)(struct dc *dc, struct pipe_ctx *pipe_ctx); 105 void (*init_blank)(struct dc *dc, struct timing_generator *tg); 106 void (*disable_vga)(struct dce_hwseq *hws); 107 void (*bios_golden_init)(struct dc *dc); 108 void (*plane_atomic_power_down)(struct dc *dc, 109 struct dpp *dpp, 110 struct hubp *hubp); 111 void (*plane_atomic_disable)(struct dc *dc, struct pipe_ctx *pipe_ctx); 112 void (*enable_power_gating_plane)(struct dce_hwseq *hws, 113 bool enable); 114 void (*dpp_pg_control)(struct dce_hwseq *hws, 115 unsigned int dpp_inst, 116 bool power_on); 117 void (*hubp_pg_control)(struct dce_hwseq *hws, 118 unsigned int hubp_inst, 119 bool power_on); 120 void (*dsc_pg_control)(struct dce_hwseq *hws, 121 unsigned int dsc_inst, 122 bool power_on); 123 void (*update_odm)(struct dc *dc, struct dc_state *context, 124 struct pipe_ctx *pipe_ctx); 125 void (*program_all_writeback_pipes_in_tree)(struct dc *dc, 126 const struct dc_stream_state *stream, 127 struct dc_state *context); 128 bool (*s0i3_golden_init_wa)(struct dc *dc); 129 void (*get_surface_visual_confirm_color)( 130 const struct pipe_ctx *pipe_ctx, 131 struct tg_color *color); 132 void (*get_hdr_visual_confirm_color)(struct pipe_ctx *pipe_ctx, 133 struct tg_color *color); 134 void (*set_hdr_multiplier)(struct pipe_ctx *pipe_ctx); 135 void (*verify_allow_pstate_change_high)(struct dc *dc); 136 void (*program_pipe)(struct dc *dc, 137 struct pipe_ctx *pipe_ctx, 138 struct dc_state *context); 139 bool (*wait_for_blank_complete)(struct output_pixel_processor *opp); 140 void (*dccg_init)(struct dce_hwseq *hws); 141 bool (*set_blend_lut)(struct pipe_ctx *pipe_ctx, 142 const struct dc_plane_state *plane_state); 143 bool (*set_shaper_3dlut)(struct pipe_ctx *pipe_ctx, 144 const struct dc_plane_state *plane_state); 145 }; 146 147 struct dce_hwseq { 148 struct dc_context *ctx; 149 const struct dce_hwseq_registers *regs; 150 const struct dce_hwseq_shift *shifts; 151 const struct dce_hwseq_mask *masks; 152 struct dce_hwseq_wa wa; 153 struct hwseq_wa_state wa_state; 154 struct hwseq_private_funcs funcs; 155 156 }; 157 158 #endif /* __DC_HW_SEQUENCER_PRIVATE_H__ */ 159
Indexes created Sun Sep 21 20:09:37 GMT 2025