1 /* $NetBSD: amdgpu_gfx_v7_0.c,v 1.6 2021/12/19 12:02:39 riastradh Exp $ */ 2 3 /* 4 * Copyright 2014 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 26 #include <sys/cdefs.h> 27 __KERNEL_RCSID(0, "$NetBSD: amdgpu_gfx_v7_0.c,v 1.6 2021/12/19 12:02:39 riastradh Exp $"); 28 29 #include <linux/firmware.h> 30 #include <linux/module.h> 31 32 #include "amdgpu.h" 33 #include "amdgpu_ih.h" 34 #include "amdgpu_gfx.h" 35 #include "cikd.h" 36 #include "cik.h" 37 #include "cik_structs.h" 38 #include "atom.h" 39 #include "amdgpu_ucode.h" 40 #include "clearstate_ci.h" 41 #include "gfx_v7_0.h" 42 43 #include "dce/dce_8_0_d.h" 44 #include "dce/dce_8_0_sh_mask.h" 45 46 #include "bif/bif_4_1_d.h" 47 #include "bif/bif_4_1_sh_mask.h" 48 49 #include "gca/gfx_7_0_d.h" 50 #include "gca/gfx_7_2_enum.h" 51 #include "gca/gfx_7_2_sh_mask.h" 52 53 #include "gmc/gmc_7_0_d.h" 54 #include "gmc/gmc_7_0_sh_mask.h" 55 56 #include "oss/oss_2_0_d.h" 57 #include "oss/oss_2_0_sh_mask.h" 58 59 #include <linux/nbsd-namespace.h> 60 61 #define NUM_SIMD_PER_CU 0x4 /* missing from the gfx_7 IP headers */ 62 63 #define GFX7_NUM_GFX_RINGS 1 64 #define GFX7_MEC_HPD_SIZE 2048 65 66 static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev); 67 static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev); 68 static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev); 69 70 MODULE_FIRMWARE("amdgpu/bonaire_pfp.bin"); 71 MODULE_FIRMWARE("amdgpu/bonaire_me.bin"); 72 MODULE_FIRMWARE("amdgpu/bonaire_ce.bin"); 73 MODULE_FIRMWARE("amdgpu/bonaire_rlc.bin"); 74 MODULE_FIRMWARE("amdgpu/bonaire_mec.bin"); 75 76 MODULE_FIRMWARE("amdgpu/hawaii_pfp.bin"); 77 MODULE_FIRMWARE("amdgpu/hawaii_me.bin"); 78 MODULE_FIRMWARE("amdgpu/hawaii_ce.bin"); 79 MODULE_FIRMWARE("amdgpu/hawaii_rlc.bin"); 80 MODULE_FIRMWARE("amdgpu/hawaii_mec.bin"); 81 82 MODULE_FIRMWARE("amdgpu/kaveri_pfp.bin"); 83 MODULE_FIRMWARE("amdgpu/kaveri_me.bin"); 84 MODULE_FIRMWARE("amdgpu/kaveri_ce.bin"); 85 MODULE_FIRMWARE("amdgpu/kaveri_rlc.bin"); 86 MODULE_FIRMWARE("amdgpu/kaveri_mec.bin"); 87 MODULE_FIRMWARE("amdgpu/kaveri_mec2.bin"); 88 89 MODULE_FIRMWARE("amdgpu/kabini_pfp.bin"); 90 MODULE_FIRMWARE("amdgpu/kabini_me.bin"); 91 MODULE_FIRMWARE("amdgpu/kabini_ce.bin"); 92 MODULE_FIRMWARE("amdgpu/kabini_rlc.bin"); 93 MODULE_FIRMWARE("amdgpu/kabini_mec.bin"); 94 95 MODULE_FIRMWARE("amdgpu/mullins_pfp.bin"); 96 MODULE_FIRMWARE("amdgpu/mullins_me.bin"); 97 MODULE_FIRMWARE("amdgpu/mullins_ce.bin"); 98 MODULE_FIRMWARE("amdgpu/mullins_rlc.bin"); 99 MODULE_FIRMWARE("amdgpu/mullins_mec.bin"); 100 101 static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] = 102 { 103 {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0}, 104 {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1}, 105 {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2}, 106 {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3}, 107 {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4}, 108 {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5}, 109 {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6}, 110 {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7}, 111 {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8}, 112 {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9}, 113 {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10}, 114 {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11}, 115 {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12}, 116 {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13}, 117 {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14}, 118 {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15} 119 }; 120 121 static const u32 spectre_rlc_save_restore_register_list[] = 122 { 123 (0x0e00 << 16) | (0xc12c >> 2), 124 0x00000000, 125 (0x0e00 << 16) | (0xc140 >> 2), 126 0x00000000, 127 (0x0e00 << 16) | (0xc150 >> 2), 128 0x00000000, 129 (0x0e00 << 16) | (0xc15c >> 2), 130 0x00000000, 131 (0x0e00 << 16) | (0xc168 >> 2), 132 0x00000000, 133 (0x0e00 << 16) | (0xc170 >> 2), 134 0x00000000, 135 (0x0e00 << 16) | (0xc178 >> 2), 136 0x00000000, 137 (0x0e00 << 16) | (0xc204 >> 2), 138 0x00000000, 139 (0x0e00 << 16) | (0xc2b4 >> 2), 140 0x00000000, 141 (0x0e00 << 16) | (0xc2b8 >> 2), 142 0x00000000, 143 (0x0e00 << 16) | (0xc2bc >> 2), 144 0x00000000, 145 (0x0e00 << 16) | (0xc2c0 >> 2), 146 0x00000000, 147 (0x0e00 << 16) | (0x8228 >> 2), 148 0x00000000, 149 (0x0e00 << 16) | (0x829c >> 2), 150 0x00000000, 151 (0x0e00 << 16) | (0x869c >> 2), 152 0x00000000, 153 (0x0600 << 16) | (0x98f4 >> 2), 154 0x00000000, 155 (0x0e00 << 16) | (0x98f8 >> 2), 156 0x00000000, 157 (0x0e00 << 16) | (0x9900 >> 2), 158 0x00000000, 159 (0x0e00 << 16) | (0xc260 >> 2), 160 0x00000000, 161 (0x0e00 << 16) | (0x90e8 >> 2), 162 0x00000000, 163 (0x0e00 << 16) | (0x3c000 >> 2), 164 0x00000000, 165 (0x0e00 << 16) | (0x3c00c >> 2), 166 0x00000000, 167 (0x0e00 << 16) | (0x8c1c >> 2), 168 0x00000000, 169 (0x0e00 << 16) | (0x9700 >> 2), 170 0x00000000, 171 (0x0e00 << 16) | (0xcd20 >> 2), 172 0x00000000, 173 (0x4e00 << 16) | (0xcd20 >> 2), 174 0x00000000, 175 (0x5e00 << 16) | (0xcd20 >> 2), 176 0x00000000, 177 (0x6e00 << 16) | (0xcd20 >> 2), 178 0x00000000, 179 (0x7e00 << 16) | (0xcd20 >> 2), 180 0x00000000, 181 (0x8e00 << 16) | (0xcd20 >> 2), 182 0x00000000, 183 (0x9e00 << 16) | (0xcd20 >> 2), 184 0x00000000, 185 (0xae00 << 16) | (0xcd20 >> 2), 186 0x00000000, 187 (0xbe00 << 16) | (0xcd20 >> 2), 188 0x00000000, 189 (0x0e00 << 16) | (0x89bc >> 2), 190 0x00000000, 191 (0x0e00 << 16) | (0x8900 >> 2), 192 0x00000000, 193 0x3, 194 (0x0e00 << 16) | (0xc130 >> 2), 195 0x00000000, 196 (0x0e00 << 16) | (0xc134 >> 2), 197 0x00000000, 198 (0x0e00 << 16) | (0xc1fc >> 2), 199 0x00000000, 200 (0x0e00 << 16) | (0xc208 >> 2), 201 0x00000000, 202 (0x0e00 << 16) | (0xc264 >> 2), 203 0x00000000, 204 (0x0e00 << 16) | (0xc268 >> 2), 205 0x00000000, 206 (0x0e00 << 16) | (0xc26c >> 2), 207 0x00000000, 208 (0x0e00 << 16) | (0xc270 >> 2), 209 0x00000000, 210 (0x0e00 << 16) | (0xc274 >> 2), 211 0x00000000, 212 (0x0e00 << 16) | (0xc278 >> 2), 213 0x00000000, 214 (0x0e00 << 16) | (0xc27c >> 2), 215 0x00000000, 216 (0x0e00 << 16) | (0xc280 >> 2), 217 0x00000000, 218 (0x0e00 << 16) | (0xc284 >> 2), 219 0x00000000, 220 (0x0e00 << 16) | (0xc288 >> 2), 221 0x00000000, 222 (0x0e00 << 16) | (0xc28c >> 2), 223 0x00000000, 224 (0x0e00 << 16) | (0xc290 >> 2), 225 0x00000000, 226 (0x0e00 << 16) | (0xc294 >> 2), 227 0x00000000, 228 (0x0e00 << 16) | (0xc298 >> 2), 229 0x00000000, 230 (0x0e00 << 16) | (0xc29c >> 2), 231 0x00000000, 232 (0x0e00 << 16) | (0xc2a0 >> 2), 233 0x00000000, 234 (0x0e00 << 16) | (0xc2a4 >> 2), 235 0x00000000, 236 (0x0e00 << 16) | (0xc2a8 >> 2), 237 0x00000000, 238 (0x0e00 << 16) | (0xc2ac >> 2), 239 0x00000000, 240 (0x0e00 << 16) | (0xc2b0 >> 2), 241 0x00000000, 242 (0x0e00 << 16) | (0x301d0 >> 2), 243 0x00000000, 244 (0x0e00 << 16) | (0x30238 >> 2), 245 0x00000000, 246 (0x0e00 << 16) | (0x30250 >> 2), 247 0x00000000, 248 (0x0e00 << 16) | (0x30254 >> 2), 249 0x00000000, 250 (0x0e00 << 16) | (0x30258 >> 2), 251 0x00000000, 252 (0x0e00 << 16) | (0x3025c >> 2), 253 0x00000000, 254 (0x4e00 << 16) | (0xc900 >> 2), 255 0x00000000, 256 (0x5e00 << 16) | (0xc900 >> 2), 257 0x00000000, 258 (0x6e00 << 16) | (0xc900 >> 2), 259 0x00000000, 260 (0x7e00 << 16) | (0xc900 >> 2), 261 0x00000000, 262 (0x8e00 << 16) | (0xc900 >> 2), 263 0x00000000, 264 (0x9e00 << 16) | (0xc900 >> 2), 265 0x00000000, 266 (0xae00 << 16) | (0xc900 >> 2), 267 0x00000000, 268 (0xbe00 << 16) | (0xc900 >> 2), 269 0x00000000, 270 (0x4e00 << 16) | (0xc904 >> 2), 271 0x00000000, 272 (0x5e00 << 16) | (0xc904 >> 2), 273 0x00000000, 274 (0x6e00 << 16) | (0xc904 >> 2), 275 0x00000000, 276 (0x7e00 << 16) | (0xc904 >> 2), 277 0x00000000, 278 (0x8e00 << 16) | (0xc904 >> 2), 279 0x00000000, 280 (0x9e00 << 16) | (0xc904 >> 2), 281 0x00000000, 282 (0xae00 << 16) | (0xc904 >> 2), 283 0x00000000, 284 (0xbe00 << 16) | (0xc904 >> 2), 285 0x00000000, 286 (0x4e00 << 16) | (0xc908 >> 2), 287 0x00000000, 288 (0x5e00 << 16) | (0xc908 >> 2), 289 0x00000000, 290 (0x6e00 << 16) | (0xc908 >> 2), 291 0x00000000, 292 (0x7e00 << 16) | (0xc908 >> 2), 293 0x00000000, 294 (0x8e00 << 16) | (0xc908 >> 2), 295 0x00000000, 296 (0x9e00 << 16) | (0xc908 >> 2), 297 0x00000000, 298 (0xae00 << 16) | (0xc908 >> 2), 299 0x00000000, 300 (0xbe00 << 16) | (0xc908 >> 2), 301 0x00000000, 302 (0x4e00 << 16) | (0xc90c >> 2), 303 0x00000000, 304 (0x5e00 << 16) | (0xc90c >> 2), 305 0x00000000, 306 (0x6e00 << 16) | (0xc90c >> 2), 307 0x00000000, 308 (0x7e00 << 16) | (0xc90c >> 2), 309 0x00000000, 310 (0x8e00 << 16) | (0xc90c >> 2), 311 0x00000000, 312 (0x9e00 << 16) | (0xc90c >> 2), 313 0x00000000, 314 (0xae00 << 16) | (0xc90c >> 2), 315 0x00000000, 316 (0xbe00 << 16) | (0xc90c >> 2), 317 0x00000000, 318 (0x4e00 << 16) | (0xc910 >> 2), 319 0x00000000, 320 (0x5e00 << 16) | (0xc910 >> 2), 321 0x00000000, 322 (0x6e00 << 16) | (0xc910 >> 2), 323 0x00000000, 324 (0x7e00 << 16) | (0xc910 >> 2), 325 0x00000000, 326 (0x8e00 << 16) | (0xc910 >> 2), 327 0x00000000, 328 (0x9e00 << 16) | (0xc910 >> 2), 329 0x00000000, 330 (0xae00 << 16) | (0xc910 >> 2), 331 0x00000000, 332 (0xbe00 << 16) | (0xc910 >> 2), 333 0x00000000, 334 (0x0e00 << 16) | (0xc99c >> 2), 335 0x00000000, 336 (0x0e00 << 16) | (0x9834 >> 2), 337 0x00000000, 338 (0x0000 << 16) | (0x30f00 >> 2), 339 0x00000000, 340 (0x0001 << 16) | (0x30f00 >> 2), 341 0x00000000, 342 (0x0000 << 16) | (0x30f04 >> 2), 343 0x00000000, 344 (0x0001 << 16) | (0x30f04 >> 2), 345 0x00000000, 346 (0x0000 << 16) | (0x30f08 >> 2), 347 0x00000000, 348 (0x0001 << 16) | (0x30f08 >> 2), 349 0x00000000, 350 (0x0000 << 16) | (0x30f0c >> 2), 351 0x00000000, 352 (0x0001 << 16) | (0x30f0c >> 2), 353 0x00000000, 354 (0x0600 << 16) | (0x9b7c >> 2), 355 0x00000000, 356 (0x0e00 << 16) | (0x8a14 >> 2), 357 0x00000000, 358 (0x0e00 << 16) | (0x8a18 >> 2), 359 0x00000000, 360 (0x0600 << 16) | (0x30a00 >> 2), 361 0x00000000, 362 (0x0e00 << 16) | (0x8bf0 >> 2), 363 0x00000000, 364 (0x0e00 << 16) | (0x8bcc >> 2), 365 0x00000000, 366 (0x0e00 << 16) | (0x8b24 >> 2), 367 0x00000000, 368 (0x0e00 << 16) | (0x30a04 >> 2), 369 0x00000000, 370 (0x0600 << 16) | (0x30a10 >> 2), 371 0x00000000, 372 (0x0600 << 16) | (0x30a14 >> 2), 373 0x00000000, 374 (0x0600 << 16) | (0x30a18 >> 2), 375 0x00000000, 376 (0x0600 << 16) | (0x30a2c >> 2), 377 0x00000000, 378 (0x0e00 << 16) | (0xc700 >> 2), 379 0x00000000, 380 (0x0e00 << 16) | (0xc704 >> 2), 381 0x00000000, 382 (0x0e00 << 16) | (0xc708 >> 2), 383 0x00000000, 384 (0x0e00 << 16) | (0xc768 >> 2), 385 0x00000000, 386 (0x0400 << 16) | (0xc770 >> 2), 387 0x00000000, 388 (0x0400 << 16) | (0xc774 >> 2), 389 0x00000000, 390 (0x0400 << 16) | (0xc778 >> 2), 391 0x00000000, 392 (0x0400 << 16) | (0xc77c >> 2), 393 0x00000000, 394 (0x0400 << 16) | (0xc780 >> 2), 395 0x00000000, 396 (0x0400 << 16) | (0xc784 >> 2), 397 0x00000000, 398 (0x0400 << 16) | (0xc788 >> 2), 399 0x00000000, 400 (0x0400 << 16) | (0xc78c >> 2), 401 0x00000000, 402 (0x0400 << 16) | (0xc798 >> 2), 403 0x00000000, 404 (0x0400 << 16) | (0xc79c >> 2), 405 0x00000000, 406 (0x0400 << 16) | (0xc7a0 >> 2), 407 0x00000000, 408 (0x0400 << 16) | (0xc7a4 >> 2), 409 0x00000000, 410 (0x0400 << 16) | (0xc7a8 >> 2), 411 0x00000000, 412 (0x0400 << 16) | (0xc7ac >> 2), 413 0x00000000, 414 (0x0400 << 16) | (0xc7b0 >> 2), 415 0x00000000, 416 (0x0400 << 16) | (0xc7b4 >> 2), 417 0x00000000, 418 (0x0e00 << 16) | (0x9100 >> 2), 419 0x00000000, 420 (0x0e00 << 16) | (0x3c010 >> 2), 421 0x00000000, 422 (0x0e00 << 16) | (0x92a8 >> 2), 423 0x00000000, 424 (0x0e00 << 16) | (0x92ac >> 2), 425 0x00000000, 426 (0x0e00 << 16) | (0x92b4 >> 2), 427 0x00000000, 428 (0x0e00 << 16) | (0x92b8 >> 2), 429 0x00000000, 430 (0x0e00 << 16) | (0x92bc >> 2), 431 0x00000000, 432 (0x0e00 << 16) | (0x92c0 >> 2), 433 0x00000000, 434 (0x0e00 << 16) | (0x92c4 >> 2), 435 0x00000000, 436 (0x0e00 << 16) | (0x92c8 >> 2), 437 0x00000000, 438 (0x0e00 << 16) | (0x92cc >> 2), 439 0x00000000, 440 (0x0e00 << 16) | (0x92d0 >> 2), 441 0x00000000, 442 (0x0e00 << 16) | (0x8c00 >> 2), 443 0x00000000, 444 (0x0e00 << 16) | (0x8c04 >> 2), 445 0x00000000, 446 (0x0e00 << 16) | (0x8c20 >> 2), 447 0x00000000, 448 (0x0e00 << 16) | (0x8c38 >> 2), 449 0x00000000, 450 (0x0e00 << 16) | (0x8c3c >> 2), 451 0x00000000, 452 (0x0e00 << 16) | (0xae00 >> 2), 453 0x00000000, 454 (0x0e00 << 16) | (0x9604 >> 2), 455 0x00000000, 456 (0x0e00 << 16) | (0xac08 >> 2), 457 0x00000000, 458 (0x0e00 << 16) | (0xac0c >> 2), 459 0x00000000, 460 (0x0e00 << 16) | (0xac10 >> 2), 461 0x00000000, 462 (0x0e00 << 16) | (0xac14 >> 2), 463 0x00000000, 464 (0x0e00 << 16) | (0xac58 >> 2), 465 0x00000000, 466 (0x0e00 << 16) | (0xac68 >> 2), 467 0x00000000, 468 (0x0e00 << 16) | (0xac6c >> 2), 469 0x00000000, 470 (0x0e00 << 16) | (0xac70 >> 2), 471 0x00000000, 472 (0x0e00 << 16) | (0xac74 >> 2), 473 0x00000000, 474 (0x0e00 << 16) | (0xac78 >> 2), 475 0x00000000, 476 (0x0e00 << 16) | (0xac7c >> 2), 477 0x00000000, 478 (0x0e00 << 16) | (0xac80 >> 2), 479 0x00000000, 480 (0x0e00 << 16) | (0xac84 >> 2), 481 0x00000000, 482 (0x0e00 << 16) | (0xac88 >> 2), 483 0x00000000, 484 (0x0e00 << 16) | (0xac8c >> 2), 485 0x00000000, 486 (0x0e00 << 16) | (0x970c >> 2), 487 0x00000000, 488 (0x0e00 << 16) | (0x9714 >> 2), 489 0x00000000, 490 (0x0e00 << 16) | (0x9718 >> 2), 491 0x00000000, 492 (0x0e00 << 16) | (0x971c >> 2), 493 0x00000000, 494 (0x0e00 << 16) | (0x31068 >> 2), 495 0x00000000, 496 (0x4e00 << 16) | (0x31068 >> 2), 497 0x00000000, 498 (0x5e00 << 16) | (0x31068 >> 2), 499 0x00000000, 500 (0x6e00 << 16) | (0x31068 >> 2), 501 0x00000000, 502 (0x7e00 << 16) | (0x31068 >> 2), 503 0x00000000, 504 (0x8e00 << 16) | (0x31068 >> 2), 505 0x00000000, 506 (0x9e00 << 16) | (0x31068 >> 2), 507 0x00000000, 508 (0xae00 << 16) | (0x31068 >> 2), 509 0x00000000, 510 (0xbe00 << 16) | (0x31068 >> 2), 511 0x00000000, 512 (0x0e00 << 16) | (0xcd10 >> 2), 513 0x00000000, 514 (0x0e00 << 16) | (0xcd14 >> 2), 515 0x00000000, 516 (0x0e00 << 16) | (0x88b0 >> 2), 517 0x00000000, 518 (0x0e00 << 16) | (0x88b4 >> 2), 519 0x00000000, 520 (0x0e00 << 16) | (0x88b8 >> 2), 521 0x00000000, 522 (0x0e00 << 16) | (0x88bc >> 2), 523 0x00000000, 524 (0x0400 << 16) | (0x89c0 >> 2), 525 0x00000000, 526 (0x0e00 << 16) | (0x88c4 >> 2), 527 0x00000000, 528 (0x0e00 << 16) | (0x88c8 >> 2), 529 0x00000000, 530 (0x0e00 << 16) | (0x88d0 >> 2), 531 0x00000000, 532 (0x0e00 << 16) | (0x88d4 >> 2), 533 0x00000000, 534 (0x0e00 << 16) | (0x88d8 >> 2), 535 0x00000000, 536 (0x0e00 << 16) | (0x8980 >> 2), 537 0x00000000, 538 (0x0e00 << 16) | (0x30938 >> 2), 539 0x00000000, 540 (0x0e00 << 16) | (0x3093c >> 2), 541 0x00000000, 542 (0x0e00 << 16) | (0x30940 >> 2), 543 0x00000000, 544 (0x0e00 << 16) | (0x89a0 >> 2), 545 0x00000000, 546 (0x0e00 << 16) | (0x30900 >> 2), 547 0x00000000, 548 (0x0e00 << 16) | (0x30904 >> 2), 549 0x00000000, 550 (0x0e00 << 16) | (0x89b4 >> 2), 551 0x00000000, 552 (0x0e00 << 16) | (0x3c210 >> 2), 553 0x00000000, 554 (0x0e00 << 16) | (0x3c214 >> 2), 555 0x00000000, 556 (0x0e00 << 16) | (0x3c218 >> 2), 557 0x00000000, 558 (0x0e00 << 16) | (0x8904 >> 2), 559 0x00000000, 560 0x5, 561 (0x0e00 << 16) | (0x8c28 >> 2), 562 (0x0e00 << 16) | (0x8c2c >> 2), 563 (0x0e00 << 16) | (0x8c30 >> 2), 564 (0x0e00 << 16) | (0x8c34 >> 2), 565 (0x0e00 << 16) | (0x9600 >> 2), 566 }; 567 568 static const u32 kalindi_rlc_save_restore_register_list[] = 569 { 570 (0x0e00 << 16) | (0xc12c >> 2), 571 0x00000000, 572 (0x0e00 << 16) | (0xc140 >> 2), 573 0x00000000, 574 (0x0e00 << 16) | (0xc150 >> 2), 575 0x00000000, 576 (0x0e00 << 16) | (0xc15c >> 2), 577 0x00000000, 578 (0x0e00 << 16) | (0xc168 >> 2), 579 0x00000000, 580 (0x0e00 << 16) | (0xc170 >> 2), 581 0x00000000, 582 (0x0e00 << 16) | (0xc204 >> 2), 583 0x00000000, 584 (0x0e00 << 16) | (0xc2b4 >> 2), 585 0x00000000, 586 (0x0e00 << 16) | (0xc2b8 >> 2), 587 0x00000000, 588 (0x0e00 << 16) | (0xc2bc >> 2), 589 0x00000000, 590 (0x0e00 << 16) | (0xc2c0 >> 2), 591 0x00000000, 592 (0x0e00 << 16) | (0x8228 >> 2), 593 0x00000000, 594 (0x0e00 << 16) | (0x829c >> 2), 595 0x00000000, 596 (0x0e00 << 16) | (0x869c >> 2), 597 0x00000000, 598 (0x0600 << 16) | (0x98f4 >> 2), 599 0x00000000, 600 (0x0e00 << 16) | (0x98f8 >> 2), 601 0x00000000, 602 (0x0e00 << 16) | (0x9900 >> 2), 603 0x00000000, 604 (0x0e00 << 16) | (0xc260 >> 2), 605 0x00000000, 606 (0x0e00 << 16) | (0x90e8 >> 2), 607 0x00000000, 608 (0x0e00 << 16) | (0x3c000 >> 2), 609 0x00000000, 610 (0x0e00 << 16) | (0x3c00c >> 2), 611 0x00000000, 612 (0x0e00 << 16) | (0x8c1c >> 2), 613 0x00000000, 614 (0x0e00 << 16) | (0x9700 >> 2), 615 0x00000000, 616 (0x0e00 << 16) | (0xcd20 >> 2), 617 0x00000000, 618 (0x4e00 << 16) | (0xcd20 >> 2), 619 0x00000000, 620 (0x5e00 << 16) | (0xcd20 >> 2), 621 0x00000000, 622 (0x6e00 << 16) | (0xcd20 >> 2), 623 0x00000000, 624 (0x7e00 << 16) | (0xcd20 >> 2), 625 0x00000000, 626 (0x0e00 << 16) | (0x89bc >> 2), 627 0x00000000, 628 (0x0e00 << 16) | (0x8900 >> 2), 629 0x00000000, 630 0x3, 631 (0x0e00 << 16) | (0xc130 >> 2), 632 0x00000000, 633 (0x0e00 << 16) | (0xc134 >> 2), 634 0x00000000, 635 (0x0e00 << 16) | (0xc1fc >> 2), 636 0x00000000, 637 (0x0e00 << 16) | (0xc208 >> 2), 638 0x00000000, 639 (0x0e00 << 16) | (0xc264 >> 2), 640 0x00000000, 641 (0x0e00 << 16) | (0xc268 >> 2), 642 0x00000000, 643 (0x0e00 << 16) | (0xc26c >> 2), 644 0x00000000, 645 (0x0e00 << 16) | (0xc270 >> 2), 646 0x00000000, 647 (0x0e00 << 16) | (0xc274 >> 2), 648 0x00000000, 649 (0x0e00 << 16) | (0xc28c >> 2), 650 0x00000000, 651 (0x0e00 << 16) | (0xc290 >> 2), 652 0x00000000, 653 (0x0e00 << 16) | (0xc294 >> 2), 654 0x00000000, 655 (0x0e00 << 16) | (0xc298 >> 2), 656 0x00000000, 657 (0x0e00 << 16) | (0xc2a0 >> 2), 658 0x00000000, 659 (0x0e00 << 16) | (0xc2a4 >> 2), 660 0x00000000, 661 (0x0e00 << 16) | (0xc2a8 >> 2), 662 0x00000000, 663 (0x0e00 << 16) | (0xc2ac >> 2), 664 0x00000000, 665 (0x0e00 << 16) | (0x301d0 >> 2), 666 0x00000000, 667 (0x0e00 << 16) | (0x30238 >> 2), 668 0x00000000, 669 (0x0e00 << 16) | (0x30250 >> 2), 670 0x00000000, 671 (0x0e00 << 16) | (0x30254 >> 2), 672 0x00000000, 673 (0x0e00 << 16) | (0x30258 >> 2), 674 0x00000000, 675 (0x0e00 << 16) | (0x3025c >> 2), 676 0x00000000, 677 (0x4e00 << 16) | (0xc900 >> 2), 678 0x00000000, 679 (0x5e00 << 16) | (0xc900 >> 2), 680 0x00000000, 681 (0x6e00 << 16) | (0xc900 >> 2), 682 0x00000000, 683 (0x7e00 << 16) | (0xc900 >> 2), 684 0x00000000, 685 (0x4e00 << 16) | (0xc904 >> 2), 686 0x00000000, 687 (0x5e00 << 16) | (0xc904 >> 2), 688 0x00000000, 689 (0x6e00 << 16) | (0xc904 >> 2), 690 0x00000000, 691 (0x7e00 << 16) | (0xc904 >> 2), 692 0x00000000, 693 (0x4e00 << 16) | (0xc908 >> 2), 694 0x00000000, 695 (0x5e00 << 16) | (0xc908 >> 2), 696 0x00000000, 697 (0x6e00 << 16) | (0xc908 >> 2), 698 0x00000000, 699 (0x7e00 << 16) | (0xc908 >> 2), 700 0x00000000, 701 (0x4e00 << 16) | (0xc90c >> 2), 702 0x00000000, 703 (0x5e00 << 16) | (0xc90c >> 2), 704 0x00000000, 705 (0x6e00 << 16) | (0xc90c >> 2), 706 0x00000000, 707 (0x7e00 << 16) | (0xc90c >> 2), 708 0x00000000, 709 (0x4e00 << 16) | (0xc910 >> 2), 710 0x00000000, 711 (0x5e00 << 16) | (0xc910 >> 2), 712 0x00000000, 713 (0x6e00 << 16) | (0xc910 >> 2), 714 0x00000000, 715 (0x7e00 << 16) | (0xc910 >> 2), 716 0x00000000, 717 (0x0e00 << 16) | (0xc99c >> 2), 718 0x00000000, 719 (0x0e00 << 16) | (0x9834 >> 2), 720 0x00000000, 721 (0x0000 << 16) | (0x30f00 >> 2), 722 0x00000000, 723 (0x0000 << 16) | (0x30f04 >> 2), 724 0x00000000, 725 (0x0000 << 16) | (0x30f08 >> 2), 726 0x00000000, 727 (0x0000 << 16) | (0x30f0c >> 2), 728 0x00000000, 729 (0x0600 << 16) | (0x9b7c >> 2), 730 0x00000000, 731 (0x0e00 << 16) | (0x8a14 >> 2), 732 0x00000000, 733 (0x0e00 << 16) | (0x8a18 >> 2), 734 0x00000000, 735 (0x0600 << 16) | (0x30a00 >> 2), 736 0x00000000, 737 (0x0e00 << 16) | (0x8bf0 >> 2), 738 0x00000000, 739 (0x0e00 << 16) | (0x8bcc >> 2), 740 0x00000000, 741 (0x0e00 << 16) | (0x8b24 >> 2), 742 0x00000000, 743 (0x0e00 << 16) | (0x30a04 >> 2), 744 0x00000000, 745 (0x0600 << 16) | (0x30a10 >> 2), 746 0x00000000, 747 (0x0600 << 16) | (0x30a14 >> 2), 748 0x00000000, 749 (0x0600 << 16) | (0x30a18 >> 2), 750 0x00000000, 751 (0x0600 << 16) | (0x30a2c >> 2), 752 0x00000000, 753 (0x0e00 << 16) | (0xc700 >> 2), 754 0x00000000, 755 (0x0e00 << 16) | (0xc704 >> 2), 756 0x00000000, 757 (0x0e00 << 16) | (0xc708 >> 2), 758 0x00000000, 759 (0x0e00 << 16) | (0xc768 >> 2), 760 0x00000000, 761 (0x0400 << 16) | (0xc770 >> 2), 762 0x00000000, 763 (0x0400 << 16) | (0xc774 >> 2), 764 0x00000000, 765 (0x0400 << 16) | (0xc798 >> 2), 766 0x00000000, 767 (0x0400 << 16) | (0xc79c >> 2), 768 0x00000000, 769 (0x0e00 << 16) | (0x9100 >> 2), 770 0x00000000, 771 (0x0e00 << 16) | (0x3c010 >> 2), 772 0x00000000, 773 (0x0e00 << 16) | (0x8c00 >> 2), 774 0x00000000, 775 (0x0e00 << 16) | (0x8c04 >> 2), 776 0x00000000, 777 (0x0e00 << 16) | (0x8c20 >> 2), 778 0x00000000, 779 (0x0e00 << 16) | (0x8c38 >> 2), 780 0x00000000, 781 (0x0e00 << 16) | (0x8c3c >> 2), 782 0x00000000, 783 (0x0e00 << 16) | (0xae00 >> 2), 784 0x00000000, 785 (0x0e00 << 16) | (0x9604 >> 2), 786 0x00000000, 787 (0x0e00 << 16) | (0xac08 >> 2), 788 0x00000000, 789 (0x0e00 << 16) | (0xac0c >> 2), 790 0x00000000, 791 (0x0e00 << 16) | (0xac10 >> 2), 792 0x00000000, 793 (0x0e00 << 16) | (0xac14 >> 2), 794 0x00000000, 795 (0x0e00 << 16) | (0xac58 >> 2), 796 0x00000000, 797 (0x0e00 << 16) | (0xac68 >> 2), 798 0x00000000, 799 (0x0e00 << 16) | (0xac6c >> 2), 800 0x00000000, 801 (0x0e00 << 16) | (0xac70 >> 2), 802 0x00000000, 803 (0x0e00 << 16) | (0xac74 >> 2), 804 0x00000000, 805 (0x0e00 << 16) | (0xac78 >> 2), 806 0x00000000, 807 (0x0e00 << 16) | (0xac7c >> 2), 808 0x00000000, 809 (0x0e00 << 16) | (0xac80 >> 2), 810 0x00000000, 811 (0x0e00 << 16) | (0xac84 >> 2), 812 0x00000000, 813 (0x0e00 << 16) | (0xac88 >> 2), 814 0x00000000, 815 (0x0e00 << 16) | (0xac8c >> 2), 816 0x00000000, 817 (0x0e00 << 16) | (0x970c >> 2), 818 0x00000000, 819 (0x0e00 << 16) | (0x9714 >> 2), 820 0x00000000, 821 (0x0e00 << 16) | (0x9718 >> 2), 822 0x00000000, 823 (0x0e00 << 16) | (0x971c >> 2), 824 0x00000000, 825 (0x0e00 << 16) | (0x31068 >> 2), 826 0x00000000, 827 (0x4e00 << 16) | (0x31068 >> 2), 828 0x00000000, 829 (0x5e00 << 16) | (0x31068 >> 2), 830 0x00000000, 831 (0x6e00 << 16) | (0x31068 >> 2), 832 0x00000000, 833 (0x7e00 << 16) | (0x31068 >> 2), 834 0x00000000, 835 (0x0e00 << 16) | (0xcd10 >> 2), 836 0x00000000, 837 (0x0e00 << 16) | (0xcd14 >> 2), 838 0x00000000, 839 (0x0e00 << 16) | (0x88b0 >> 2), 840 0x00000000, 841 (0x0e00 << 16) | (0x88b4 >> 2), 842 0x00000000, 843 (0x0e00 << 16) | (0x88b8 >> 2), 844 0x00000000, 845 (0x0e00 << 16) | (0x88bc >> 2), 846 0x00000000, 847 (0x0400 << 16) | (0x89c0 >> 2), 848 0x00000000, 849 (0x0e00 << 16) | (0x88c4 >> 2), 850 0x00000000, 851 (0x0e00 << 16) | (0x88c8 >> 2), 852 0x00000000, 853 (0x0e00 << 16) | (0x88d0 >> 2), 854 0x00000000, 855 (0x0e00 << 16) | (0x88d4 >> 2), 856 0x00000000, 857 (0x0e00 << 16) | (0x88d8 >> 2), 858 0x00000000, 859 (0x0e00 << 16) | (0x8980 >> 2), 860 0x00000000, 861 (0x0e00 << 16) | (0x30938 >> 2), 862 0x00000000, 863 (0x0e00 << 16) | (0x3093c >> 2), 864 0x00000000, 865 (0x0e00 << 16) | (0x30940 >> 2), 866 0x00000000, 867 (0x0e00 << 16) | (0x89a0 >> 2), 868 0x00000000, 869 (0x0e00 << 16) | (0x30900 >> 2), 870 0x00000000, 871 (0x0e00 << 16) | (0x30904 >> 2), 872 0x00000000, 873 (0x0e00 << 16) | (0x89b4 >> 2), 874 0x00000000, 875 (0x0e00 << 16) | (0x3e1fc >> 2), 876 0x00000000, 877 (0x0e00 << 16) | (0x3c210 >> 2), 878 0x00000000, 879 (0x0e00 << 16) | (0x3c214 >> 2), 880 0x00000000, 881 (0x0e00 << 16) | (0x3c218 >> 2), 882 0x00000000, 883 (0x0e00 << 16) | (0x8904 >> 2), 884 0x00000000, 885 0x5, 886 (0x0e00 << 16) | (0x8c28 >> 2), 887 (0x0e00 << 16) | (0x8c2c >> 2), 888 (0x0e00 << 16) | (0x8c30 >> 2), 889 (0x0e00 << 16) | (0x8c34 >> 2), 890 (0x0e00 << 16) | (0x9600 >> 2), 891 }; 892 893 static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev); 894 static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer); 895 static void gfx_v7_0_init_pg(struct amdgpu_device *adev); 896 static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev); 897 898 /* 899 * Core functions 900 */ 901 /** 902 * gfx_v7_0_init_microcode - load ucode images from disk 903 * 904 * @adev: amdgpu_device pointer 905 * 906 * Use the firmware interface to load the ucode images into 907 * the driver (not loaded into hw). 908 * Returns 0 on success, error on failure. 909 */ 910 static int gfx_v7_0_init_microcode(struct amdgpu_device *adev) 911 { 912 const char *chip_name; 913 char fw_name[30]; 914 int err; 915 916 DRM_DEBUG("\n"); 917 918 switch (adev->asic_type) { 919 case CHIP_BONAIRE: 920 chip_name = "bonaire"; 921 break; 922 case CHIP_HAWAII: 923 chip_name = "hawaii"; 924 break; 925 case CHIP_KAVERI: 926 chip_name = "kaveri"; 927 break; 928 case CHIP_KABINI: 929 chip_name = "kabini"; 930 break; 931 case CHIP_MULLINS: 932 chip_name = "mullins"; 933 break; 934 default: BUG(); 935 } 936 937 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name); 938 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); 939 if (err) 940 goto out; 941 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); 942 if (err) 943 goto out; 944 945 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name); 946 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); 947 if (err) 948 goto out; 949 err = amdgpu_ucode_validate(adev->gfx.me_fw); 950 if (err) 951 goto out; 952 953 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name); 954 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); 955 if (err) 956 goto out; 957 err = amdgpu_ucode_validate(adev->gfx.ce_fw); 958 if (err) 959 goto out; 960 961 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name); 962 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); 963 if (err) 964 goto out; 965 err = amdgpu_ucode_validate(adev->gfx.mec_fw); 966 if (err) 967 goto out; 968 969 if (adev->asic_type == CHIP_KAVERI) { 970 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name); 971 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); 972 if (err) 973 goto out; 974 err = amdgpu_ucode_validate(adev->gfx.mec2_fw); 975 if (err) 976 goto out; 977 } 978 979 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); 980 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); 981 if (err) 982 goto out; 983 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); 984 985 out: 986 if (err) { 987 pr_err("gfx7: Failed to load firmware \"%s\"\n", fw_name); 988 release_firmware(adev->gfx.pfp_fw); 989 adev->gfx.pfp_fw = NULL; 990 release_firmware(adev->gfx.me_fw); 991 adev->gfx.me_fw = NULL; 992 release_firmware(adev->gfx.ce_fw); 993 adev->gfx.ce_fw = NULL; 994 release_firmware(adev->gfx.mec_fw); 995 adev->gfx.mec_fw = NULL; 996 release_firmware(adev->gfx.mec2_fw); 997 adev->gfx.mec2_fw = NULL; 998 release_firmware(adev->gfx.rlc_fw); 999 adev->gfx.rlc_fw = NULL; 1000 } 1001 return err; 1002 } 1003 1004 static void gfx_v7_0_free_microcode(struct amdgpu_device *adev) 1005 { 1006 release_firmware(adev->gfx.pfp_fw); 1007 adev->gfx.pfp_fw = NULL; 1008 release_firmware(adev->gfx.me_fw); 1009 adev->gfx.me_fw = NULL; 1010 release_firmware(adev->gfx.ce_fw); 1011 adev->gfx.ce_fw = NULL; 1012 release_firmware(adev->gfx.mec_fw); 1013 adev->gfx.mec_fw = NULL; 1014 release_firmware(adev->gfx.mec2_fw); 1015 adev->gfx.mec2_fw = NULL; 1016 release_firmware(adev->gfx.rlc_fw); 1017 adev->gfx.rlc_fw = NULL; 1018 } 1019 1020 /** 1021 * gfx_v7_0_tiling_mode_table_init - init the hw tiling table 1022 * 1023 * @adev: amdgpu_device pointer 1024 * 1025 * Starting with SI, the tiling setup is done globally in a 1026 * set of 32 tiling modes. Rather than selecting each set of 1027 * parameters per surface as on older asics, we just select 1028 * which index in the tiling table we want to use, and the 1029 * surface uses those parameters (CIK). 1030 */ 1031 static void gfx_v7_0_tiling_mode_table_init(struct amdgpu_device *adev) 1032 { 1033 const u32 num_tile_mode_states = 1034 ARRAY_SIZE(adev->gfx.config.tile_mode_array); 1035 const u32 num_secondary_tile_mode_states = 1036 ARRAY_SIZE(adev->gfx.config.macrotile_mode_array); 1037 u32 reg_offset, split_equal_to_row_size; 1038 uint32_t *tile, *macrotile; 1039 1040 tile = adev->gfx.config.tile_mode_array; 1041 macrotile = adev->gfx.config.macrotile_mode_array; 1042 1043 switch (adev->gfx.config.mem_row_size_in_kb) { 1044 case 1: 1045 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB; 1046 break; 1047 case 2: 1048 default: 1049 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB; 1050 break; 1051 case 4: 1052 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB; 1053 break; 1054 } 1055 1056 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 1057 tile[reg_offset] = 0; 1058 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) 1059 macrotile[reg_offset] = 0; 1060 1061 switch (adev->asic_type) { 1062 case CHIP_BONAIRE: 1063 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1064 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1065 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1066 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1067 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1068 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1069 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 1070 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1071 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1072 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1073 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1074 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1075 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1076 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1077 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1078 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1079 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1080 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1081 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1082 TILE_SPLIT(split_equal_to_row_size)); 1083 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1084 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1085 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1086 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1087 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1088 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1089 TILE_SPLIT(split_equal_to_row_size)); 1090 tile[7] = (TILE_SPLIT(split_equal_to_row_size)); 1091 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 1092 PIPE_CONFIG(ADDR_SURF_P4_16x16)); 1093 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1094 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1095 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); 1096 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1097 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1098 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1099 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1100 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1101 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1102 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1103 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1104 tile[12] = (TILE_SPLIT(split_equal_to_row_size)); 1105 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1106 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1107 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); 1108 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1109 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1110 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1111 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1112 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | 1113 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1114 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1115 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1116 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1117 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1118 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1119 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1120 tile[17] = (TILE_SPLIT(split_equal_to_row_size)); 1121 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1122 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1123 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1124 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1125 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1126 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1127 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); 1128 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1129 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1130 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1131 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1132 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | 1133 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1134 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1135 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1136 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 1137 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1138 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1139 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1140 tile[23] = (TILE_SPLIT(split_equal_to_row_size)); 1141 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1142 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1143 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1144 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1145 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 1146 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1147 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1148 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1149 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | 1150 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1151 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1152 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1153 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1154 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1155 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)); 1156 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1157 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1158 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1159 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1160 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1161 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1162 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1163 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1164 tile[30] = (TILE_SPLIT(split_equal_to_row_size)); 1165 1166 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1167 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1168 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1169 NUM_BANKS(ADDR_SURF_16_BANK)); 1170 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1171 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1172 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1173 NUM_BANKS(ADDR_SURF_16_BANK)); 1174 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1175 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1176 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1177 NUM_BANKS(ADDR_SURF_16_BANK)); 1178 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1179 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1180 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1181 NUM_BANKS(ADDR_SURF_16_BANK)); 1182 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1183 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1184 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1185 NUM_BANKS(ADDR_SURF_16_BANK)); 1186 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1187 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1188 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1189 NUM_BANKS(ADDR_SURF_8_BANK)); 1190 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1191 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1192 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1193 NUM_BANKS(ADDR_SURF_4_BANK)); 1194 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 1195 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 1196 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1197 NUM_BANKS(ADDR_SURF_16_BANK)); 1198 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 1199 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1200 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1201 NUM_BANKS(ADDR_SURF_16_BANK)); 1202 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1203 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1204 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1205 NUM_BANKS(ADDR_SURF_16_BANK)); 1206 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1207 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1208 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1209 NUM_BANKS(ADDR_SURF_16_BANK)); 1210 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1211 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1212 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1213 NUM_BANKS(ADDR_SURF_16_BANK)); 1214 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1215 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1216 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1217 NUM_BANKS(ADDR_SURF_8_BANK)); 1218 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1219 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1220 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1221 NUM_BANKS(ADDR_SURF_4_BANK)); 1222 1223 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 1224 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]); 1225 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) 1226 if (reg_offset != 7) 1227 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]); 1228 break; 1229 case CHIP_HAWAII: 1230 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1231 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1232 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1233 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1234 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1235 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1236 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 1237 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1238 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1239 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1240 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1241 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1242 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1243 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1244 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1245 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1246 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1247 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1248 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1249 TILE_SPLIT(split_equal_to_row_size)); 1250 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1251 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1252 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1253 TILE_SPLIT(split_equal_to_row_size)); 1254 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1255 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1256 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1257 TILE_SPLIT(split_equal_to_row_size)); 1258 tile[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1259 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1260 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1261 TILE_SPLIT(split_equal_to_row_size)); 1262 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 1263 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16)); 1264 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1265 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1266 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); 1267 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1268 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1269 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1270 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1271 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1272 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1273 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1274 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1275 tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | 1276 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1277 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1278 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1279 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1280 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1281 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); 1282 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1283 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1284 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1285 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1286 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | 1287 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1288 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1289 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1290 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1291 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1292 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1293 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1294 tile[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1295 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1296 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1297 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1298 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1299 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1300 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1301 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1302 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1303 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1304 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)); 1305 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1306 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1307 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1308 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1309 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | 1310 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1311 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1312 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1313 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 1314 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1315 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1316 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1317 tile[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 1318 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1319 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1320 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1321 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1322 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1323 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1324 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1325 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 1326 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1327 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1328 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1329 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | 1330 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1331 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1332 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1333 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1334 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1335 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)); 1336 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1337 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1338 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1339 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1340 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1341 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1342 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1343 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1344 tile[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1345 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1346 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1347 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1348 1349 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1350 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1351 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1352 NUM_BANKS(ADDR_SURF_16_BANK)); 1353 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1354 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1355 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1356 NUM_BANKS(ADDR_SURF_16_BANK)); 1357 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1358 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1359 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1360 NUM_BANKS(ADDR_SURF_16_BANK)); 1361 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1362 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1363 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1364 NUM_BANKS(ADDR_SURF_16_BANK)); 1365 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1366 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1367 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1368 NUM_BANKS(ADDR_SURF_8_BANK)); 1369 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1370 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1371 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1372 NUM_BANKS(ADDR_SURF_4_BANK)); 1373 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1374 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1375 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1376 NUM_BANKS(ADDR_SURF_4_BANK)); 1377 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1378 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1379 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1380 NUM_BANKS(ADDR_SURF_16_BANK)); 1381 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1382 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1383 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1384 NUM_BANKS(ADDR_SURF_16_BANK)); 1385 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1386 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1387 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1388 NUM_BANKS(ADDR_SURF_16_BANK)); 1389 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1390 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1391 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1392 NUM_BANKS(ADDR_SURF_8_BANK)); 1393 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1394 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1395 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1396 NUM_BANKS(ADDR_SURF_16_BANK)); 1397 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1398 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1399 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1400 NUM_BANKS(ADDR_SURF_8_BANK)); 1401 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1402 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1403 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1404 NUM_BANKS(ADDR_SURF_4_BANK)); 1405 1406 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 1407 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]); 1408 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) 1409 if (reg_offset != 7) 1410 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]); 1411 break; 1412 case CHIP_KABINI: 1413 case CHIP_KAVERI: 1414 case CHIP_MULLINS: 1415 default: 1416 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1417 PIPE_CONFIG(ADDR_SURF_P2) | 1418 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1419 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1420 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1421 PIPE_CONFIG(ADDR_SURF_P2) | 1422 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 1423 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1424 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1425 PIPE_CONFIG(ADDR_SURF_P2) | 1426 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1427 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1428 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1429 PIPE_CONFIG(ADDR_SURF_P2) | 1430 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1431 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1432 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1433 PIPE_CONFIG(ADDR_SURF_P2) | 1434 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1435 TILE_SPLIT(split_equal_to_row_size)); 1436 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1437 PIPE_CONFIG(ADDR_SURF_P2) | 1438 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1439 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1440 PIPE_CONFIG(ADDR_SURF_P2) | 1441 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1442 TILE_SPLIT(split_equal_to_row_size)); 1443 tile[7] = (TILE_SPLIT(split_equal_to_row_size)); 1444 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 1445 PIPE_CONFIG(ADDR_SURF_P2)); 1446 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1447 PIPE_CONFIG(ADDR_SURF_P2) | 1448 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); 1449 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1450 PIPE_CONFIG(ADDR_SURF_P2) | 1451 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1452 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1453 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1454 PIPE_CONFIG(ADDR_SURF_P2) | 1455 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1456 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1457 tile[12] = (TILE_SPLIT(split_equal_to_row_size)); 1458 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1459 PIPE_CONFIG(ADDR_SURF_P2) | 1460 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); 1461 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1462 PIPE_CONFIG(ADDR_SURF_P2) | 1463 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1464 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1465 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | 1466 PIPE_CONFIG(ADDR_SURF_P2) | 1467 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1468 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1469 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1470 PIPE_CONFIG(ADDR_SURF_P2) | 1471 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1472 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1473 tile[17] = (TILE_SPLIT(split_equal_to_row_size)); 1474 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1475 PIPE_CONFIG(ADDR_SURF_P2) | 1476 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1477 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1478 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1479 PIPE_CONFIG(ADDR_SURF_P2) | 1480 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)); 1481 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1482 PIPE_CONFIG(ADDR_SURF_P2) | 1483 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1484 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1485 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | 1486 PIPE_CONFIG(ADDR_SURF_P2) | 1487 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1488 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1489 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 1490 PIPE_CONFIG(ADDR_SURF_P2) | 1491 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1492 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1493 tile[23] = (TILE_SPLIT(split_equal_to_row_size)); 1494 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1495 PIPE_CONFIG(ADDR_SURF_P2) | 1496 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1497 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1498 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 1499 PIPE_CONFIG(ADDR_SURF_P2) | 1500 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1501 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1502 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | 1503 PIPE_CONFIG(ADDR_SURF_P2) | 1504 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1505 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1506 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1507 PIPE_CONFIG(ADDR_SURF_P2) | 1508 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)); 1509 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1510 PIPE_CONFIG(ADDR_SURF_P2) | 1511 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1512 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1513 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1514 PIPE_CONFIG(ADDR_SURF_P2) | 1515 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1516 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1517 tile[30] = (TILE_SPLIT(split_equal_to_row_size)); 1518 1519 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1520 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1521 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1522 NUM_BANKS(ADDR_SURF_8_BANK)); 1523 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1524 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1525 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1526 NUM_BANKS(ADDR_SURF_8_BANK)); 1527 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1528 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1529 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1530 NUM_BANKS(ADDR_SURF_8_BANK)); 1531 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1532 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1533 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1534 NUM_BANKS(ADDR_SURF_8_BANK)); 1535 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1536 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1537 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1538 NUM_BANKS(ADDR_SURF_8_BANK)); 1539 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1540 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1541 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1542 NUM_BANKS(ADDR_SURF_8_BANK)); 1543 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1544 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1545 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1546 NUM_BANKS(ADDR_SURF_8_BANK)); 1547 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | 1548 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 1549 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1550 NUM_BANKS(ADDR_SURF_16_BANK)); 1551 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | 1552 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1553 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1554 NUM_BANKS(ADDR_SURF_16_BANK)); 1555 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 1556 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1557 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1558 NUM_BANKS(ADDR_SURF_16_BANK)); 1559 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 1560 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1561 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1562 NUM_BANKS(ADDR_SURF_16_BANK)); 1563 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1564 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1565 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1566 NUM_BANKS(ADDR_SURF_16_BANK)); 1567 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1568 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1569 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1570 NUM_BANKS(ADDR_SURF_16_BANK)); 1571 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1572 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1573 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1574 NUM_BANKS(ADDR_SURF_8_BANK)); 1575 1576 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 1577 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]); 1578 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) 1579 if (reg_offset != 7) 1580 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]); 1581 break; 1582 } 1583 } 1584 1585 /** 1586 * gfx_v7_0_select_se_sh - select which SE, SH to address 1587 * 1588 * @adev: amdgpu_device pointer 1589 * @se_num: shader engine to address 1590 * @sh_num: sh block to address 1591 * 1592 * Select which SE, SH combinations to address. Certain 1593 * registers are instanced per SE or SH. 0xffffffff means 1594 * broadcast to all SEs or SHs (CIK). 1595 */ 1596 static void gfx_v7_0_select_se_sh(struct amdgpu_device *adev, 1597 u32 se_num, u32 sh_num, u32 instance) 1598 { 1599 u32 data; 1600 1601 if (instance == 0xffffffff) 1602 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); 1603 else 1604 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance); 1605 1606 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) 1607 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | 1608 GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK; 1609 else if (se_num == 0xffffffff) 1610 data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK | 1611 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT); 1612 else if (sh_num == 0xffffffff) 1613 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | 1614 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); 1615 else 1616 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) | 1617 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); 1618 WREG32(mmGRBM_GFX_INDEX, data); 1619 } 1620 1621 /** 1622 * gfx_v7_0_get_rb_active_bitmap - computes the mask of enabled RBs 1623 * 1624 * @adev: amdgpu_device pointer 1625 * 1626 * Calculates the bitmask of enabled RBs (CIK). 1627 * Returns the enabled RB bitmask. 1628 */ 1629 static u32 gfx_v7_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1630 { 1631 u32 data, mask; 1632 1633 data = RREG32(mmCC_RB_BACKEND_DISABLE); 1634 data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE); 1635 1636 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 1637 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 1638 1639 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / 1640 adev->gfx.config.max_sh_per_se); 1641 1642 return (~data) & mask; 1643 } 1644 1645 static void 1646 gfx_v7_0_raster_config(struct amdgpu_device *adev, u32 *rconf, u32 *rconf1) 1647 { 1648 switch (adev->asic_type) { 1649 case CHIP_BONAIRE: 1650 *rconf |= RB_MAP_PKR0(2) | RB_XSEL2(1) | SE_MAP(2) | 1651 SE_XSEL(1) | SE_YSEL(1); 1652 *rconf1 |= 0x0; 1653 break; 1654 case CHIP_HAWAII: 1655 *rconf |= RB_MAP_PKR0(2) | RB_MAP_PKR1(2) | 1656 RB_XSEL2(1) | PKR_MAP(2) | PKR_XSEL(1) | 1657 PKR_YSEL(1) | SE_MAP(2) | SE_XSEL(2) | 1658 SE_YSEL(3); 1659 *rconf1 |= SE_PAIR_MAP(2) | SE_PAIR_XSEL(3) | 1660 SE_PAIR_YSEL(2); 1661 break; 1662 case CHIP_KAVERI: 1663 *rconf |= RB_MAP_PKR0(2); 1664 *rconf1 |= 0x0; 1665 break; 1666 case CHIP_KABINI: 1667 case CHIP_MULLINS: 1668 *rconf |= 0x0; 1669 *rconf1 |= 0x0; 1670 break; 1671 default: 1672 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type); 1673 break; 1674 } 1675 } 1676 1677 static void 1678 gfx_v7_0_write_harvested_raster_configs(struct amdgpu_device *adev, 1679 u32 raster_config, u32 raster_config_1, 1680 unsigned rb_mask, unsigned num_rb) 1681 { 1682 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1); 1683 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1); 1684 unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2); 1685 unsigned rb_per_se = num_rb / num_se; 1686 unsigned se_mask[4]; 1687 unsigned se; 1688 1689 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask; 1690 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask; 1691 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask; 1692 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask; 1693 1694 WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4)); 1695 WARN_ON(!(sh_per_se == 1 || sh_per_se == 2)); 1696 WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2)); 1697 1698 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) || 1699 (!se_mask[2] && !se_mask[3]))) { 1700 raster_config_1 &= ~SE_PAIR_MAP_MASK; 1701 1702 if (!se_mask[0] && !se_mask[1]) { 1703 raster_config_1 |= 1704 SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_3); 1705 } else { 1706 raster_config_1 |= 1707 SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_0); 1708 } 1709 } 1710 1711 for (se = 0; se < num_se; se++) { 1712 unsigned raster_config_se = raster_config; 1713 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se); 1714 unsigned pkr1_mask = pkr0_mask << rb_per_pkr; 1715 int idx = (se / 2) * 2; 1716 1717 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) { 1718 raster_config_se &= ~SE_MAP_MASK; 1719 1720 if (!se_mask[idx]) { 1721 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_3); 1722 } else { 1723 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_0); 1724 } 1725 } 1726 1727 pkr0_mask &= rb_mask; 1728 pkr1_mask &= rb_mask; 1729 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) { 1730 raster_config_se &= ~PKR_MAP_MASK; 1731 1732 if (!pkr0_mask) { 1733 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_3); 1734 } else { 1735 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_0); 1736 } 1737 } 1738 1739 if (rb_per_se >= 2) { 1740 unsigned rb0_mask = 1 << (se * rb_per_se); 1741 unsigned rb1_mask = rb0_mask << 1; 1742 1743 rb0_mask &= rb_mask; 1744 rb1_mask &= rb_mask; 1745 if (!rb0_mask || !rb1_mask) { 1746 raster_config_se &= ~RB_MAP_PKR0_MASK; 1747 1748 if (!rb0_mask) { 1749 raster_config_se |= 1750 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_3); 1751 } else { 1752 raster_config_se |= 1753 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_0); 1754 } 1755 } 1756 1757 if (rb_per_se > 2) { 1758 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr); 1759 rb1_mask = rb0_mask << 1; 1760 rb0_mask &= rb_mask; 1761 rb1_mask &= rb_mask; 1762 if (!rb0_mask || !rb1_mask) { 1763 raster_config_se &= ~RB_MAP_PKR1_MASK; 1764 1765 if (!rb0_mask) { 1766 raster_config_se |= 1767 RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_3); 1768 } else { 1769 raster_config_se |= 1770 RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_0); 1771 } 1772 } 1773 } 1774 } 1775 1776 /* GRBM_GFX_INDEX has a different offset on CI+ */ 1777 gfx_v7_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff); 1778 WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se); 1779 WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1); 1780 } 1781 1782 /* GRBM_GFX_INDEX has a different offset on CI+ */ 1783 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1784 } 1785 1786 /** 1787 * gfx_v7_0_setup_rb - setup the RBs on the asic 1788 * 1789 * @adev: amdgpu_device pointer 1790 * @se_num: number of SEs (shader engines) for the asic 1791 * @sh_per_se: number of SH blocks per SE for the asic 1792 * 1793 * Configures per-SE/SH RB registers (CIK). 1794 */ 1795 static void gfx_v7_0_setup_rb(struct amdgpu_device *adev) 1796 { 1797 int i, j; 1798 u32 data; 1799 u32 raster_config = 0, raster_config_1 = 0; 1800 u32 active_rbs = 0; 1801 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 1802 adev->gfx.config.max_sh_per_se; 1803 unsigned num_rb_pipes; 1804 1805 mutex_lock(&adev->grbm_idx_mutex); 1806 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1807 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1808 gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff); 1809 data = gfx_v7_0_get_rb_active_bitmap(adev); 1810 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 1811 rb_bitmap_width_per_sh); 1812 } 1813 } 1814 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1815 1816 adev->gfx.config.backend_enable_mask = active_rbs; 1817 adev->gfx.config.num_rbs = hweight32(active_rbs); 1818 1819 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se * 1820 adev->gfx.config.max_shader_engines, 16); 1821 1822 gfx_v7_0_raster_config(adev, &raster_config, &raster_config_1); 1823 1824 if (!adev->gfx.config.backend_enable_mask || 1825 adev->gfx.config.num_rbs >= num_rb_pipes) { 1826 WREG32(mmPA_SC_RASTER_CONFIG, raster_config); 1827 WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1); 1828 } else { 1829 gfx_v7_0_write_harvested_raster_configs(adev, raster_config, raster_config_1, 1830 adev->gfx.config.backend_enable_mask, 1831 num_rb_pipes); 1832 } 1833 1834 /* cache the values for userspace */ 1835 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1836 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1837 gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff); 1838 adev->gfx.config.rb_config[i][j].rb_backend_disable = 1839 RREG32(mmCC_RB_BACKEND_DISABLE); 1840 adev->gfx.config.rb_config[i][j].user_rb_backend_disable = 1841 RREG32(mmGC_USER_RB_BACKEND_DISABLE); 1842 adev->gfx.config.rb_config[i][j].raster_config = 1843 RREG32(mmPA_SC_RASTER_CONFIG); 1844 adev->gfx.config.rb_config[i][j].raster_config_1 = 1845 RREG32(mmPA_SC_RASTER_CONFIG_1); 1846 } 1847 } 1848 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1849 mutex_unlock(&adev->grbm_idx_mutex); 1850 } 1851 1852 /** 1853 * gfx_v7_0_init_compute_vmid - gart enable 1854 * 1855 * @adev: amdgpu_device pointer 1856 * 1857 * Initialize compute vmid sh_mem registers 1858 * 1859 */ 1860 #define DEFAULT_SH_MEM_BASES (0x6000) 1861 #define FIRST_COMPUTE_VMID (8) 1862 #define LAST_COMPUTE_VMID (16) 1863 static void gfx_v7_0_init_compute_vmid(struct amdgpu_device *adev) 1864 { 1865 int i; 1866 uint32_t sh_mem_config; 1867 uint32_t sh_mem_bases; 1868 1869 /* 1870 * Configure apertures: 1871 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1872 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1873 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1874 */ 1875 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 1876 sh_mem_config = SH_MEM_ALIGNMENT_MODE_UNALIGNED << 1877 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; 1878 sh_mem_config |= MTYPE_NONCACHED << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT; 1879 mutex_lock(&adev->srbm_mutex); 1880 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) { 1881 cik_srbm_select(adev, 0, 0, 0, i); 1882 /* CP and shaders */ 1883 WREG32(mmSH_MEM_CONFIG, sh_mem_config); 1884 WREG32(mmSH_MEM_APE1_BASE, 1); 1885 WREG32(mmSH_MEM_APE1_LIMIT, 0); 1886 WREG32(mmSH_MEM_BASES, sh_mem_bases); 1887 } 1888 cik_srbm_select(adev, 0, 0, 0, 0); 1889 mutex_unlock(&adev->srbm_mutex); 1890 1891 /* Initialize all compute VMIDs to have no GDS, GWS, or OA 1892 acccess. These should be enabled by FW for target VMIDs. */ 1893 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) { 1894 WREG32(amdgpu_gds_reg_offset[i].mem_base, 0); 1895 WREG32(amdgpu_gds_reg_offset[i].mem_size, 0); 1896 WREG32(amdgpu_gds_reg_offset[i].gws, 0); 1897 WREG32(amdgpu_gds_reg_offset[i].oa, 0); 1898 } 1899 } 1900 1901 static void gfx_v7_0_init_gds_vmid(struct amdgpu_device *adev) 1902 { 1903 int vmid; 1904 1905 /* 1906 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 1907 * access. Compute VMIDs should be enabled by FW for target VMIDs, 1908 * the driver can enable them for graphics. VMID0 should maintain 1909 * access so that HWS firmware can save/restore entries. 1910 */ 1911 for (vmid = 1; vmid < 16; vmid++) { 1912 WREG32(amdgpu_gds_reg_offset[vmid].mem_base, 0); 1913 WREG32(amdgpu_gds_reg_offset[vmid].mem_size, 0); 1914 WREG32(amdgpu_gds_reg_offset[vmid].gws, 0); 1915 WREG32(amdgpu_gds_reg_offset[vmid].oa, 0); 1916 } 1917 } 1918 1919 static void gfx_v7_0_config_init(struct amdgpu_device *adev) 1920 { 1921 adev->gfx.config.double_offchip_lds_buf = 1; 1922 } 1923 1924 /** 1925 * gfx_v7_0_constants_init - setup the 3D engine 1926 * 1927 * @adev: amdgpu_device pointer 1928 * 1929 * init the gfx constants such as the 3D engine, tiling configuration 1930 * registers, maximum number of quad pipes, render backends... 1931 */ 1932 static void gfx_v7_0_constants_init(struct amdgpu_device *adev) 1933 { 1934 u32 sh_mem_cfg, sh_static_mem_cfg, sh_mem_base; 1935 u32 tmp; 1936 int i; 1937 1938 WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT)); 1939 1940 WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 1941 WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 1942 WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config); 1943 1944 gfx_v7_0_tiling_mode_table_init(adev); 1945 1946 gfx_v7_0_setup_rb(adev); 1947 gfx_v7_0_get_cu_info(adev); 1948 gfx_v7_0_config_init(adev); 1949 1950 /* set HW defaults for 3D engine */ 1951 WREG32(mmCP_MEQ_THRESHOLDS, 1952 (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) | 1953 (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT)); 1954 1955 mutex_lock(&adev->grbm_idx_mutex); 1956 /* 1957 * making sure that the following register writes will be broadcasted 1958 * to all the shaders 1959 */ 1960 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1961 1962 /* XXX SH_MEM regs */ 1963 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1964 sh_mem_cfg = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 1965 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 1966 sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, DEFAULT_MTYPE, 1967 MTYPE_NC); 1968 sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, APE1_MTYPE, 1969 MTYPE_UC); 1970 sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, PRIVATE_ATC, 0); 1971 1972 sh_static_mem_cfg = REG_SET_FIELD(0, SH_STATIC_MEM_CONFIG, 1973 SWIZZLE_ENABLE, 1); 1974 sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG, 1975 ELEMENT_SIZE, 1); 1976 sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG, 1977 INDEX_STRIDE, 3); 1978 WREG32(mmSH_STATIC_MEM_CONFIG, sh_static_mem_cfg); 1979 1980 mutex_lock(&adev->srbm_mutex); 1981 for (i = 0; i < adev->vm_manager.id_mgr[0].num_ids; i++) { 1982 if (i == 0) 1983 sh_mem_base = 0; 1984 else 1985 sh_mem_base = adev->gmc.shared_aperture_start >> 48; 1986 cik_srbm_select(adev, 0, 0, 0, i); 1987 /* CP and shaders */ 1988 WREG32(mmSH_MEM_CONFIG, sh_mem_cfg); 1989 WREG32(mmSH_MEM_APE1_BASE, 1); 1990 WREG32(mmSH_MEM_APE1_LIMIT, 0); 1991 WREG32(mmSH_MEM_BASES, sh_mem_base); 1992 } 1993 cik_srbm_select(adev, 0, 0, 0, 0); 1994 mutex_unlock(&adev->srbm_mutex); 1995 1996 gfx_v7_0_init_compute_vmid(adev); 1997 gfx_v7_0_init_gds_vmid(adev); 1998 1999 WREG32(mmSX_DEBUG_1, 0x20); 2000 2001 WREG32(mmTA_CNTL_AUX, 0x00010000); 2002 2003 tmp = RREG32(mmSPI_CONFIG_CNTL); 2004 tmp |= 0x03000000; 2005 WREG32(mmSPI_CONFIG_CNTL, tmp); 2006 2007 WREG32(mmSQ_CONFIG, 1); 2008 2009 WREG32(mmDB_DEBUG, 0); 2010 2011 tmp = RREG32(mmDB_DEBUG2) & ~0xf00fffff; 2012 tmp |= 0x00000400; 2013 WREG32(mmDB_DEBUG2, tmp); 2014 2015 tmp = RREG32(mmDB_DEBUG3) & ~0x0002021c; 2016 tmp |= 0x00020200; 2017 WREG32(mmDB_DEBUG3, tmp); 2018 2019 tmp = RREG32(mmCB_HW_CONTROL) & ~0x00010000; 2020 tmp |= 0x00018208; 2021 WREG32(mmCB_HW_CONTROL, tmp); 2022 2023 WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT)); 2024 2025 WREG32(mmPA_SC_FIFO_SIZE, 2026 ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) | 2027 (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) | 2028 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) | 2029 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT))); 2030 2031 WREG32(mmVGT_NUM_INSTANCES, 1); 2032 2033 WREG32(mmCP_PERFMON_CNTL, 0); 2034 2035 WREG32(mmSQ_CONFIG, 0); 2036 2037 WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS, 2038 ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) | 2039 (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT))); 2040 2041 WREG32(mmVGT_CACHE_INVALIDATION, 2042 (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) | 2043 (ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT)); 2044 2045 WREG32(mmVGT_GS_VERTEX_REUSE, 16); 2046 WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0); 2047 2048 WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK | 2049 (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT)); 2050 WREG32(mmPA_SC_ENHANCE, PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK); 2051 2052 tmp = RREG32(mmSPI_ARB_PRIORITY); 2053 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS0, 2); 2054 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS1, 2); 2055 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS2, 2); 2056 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS3, 2); 2057 WREG32(mmSPI_ARB_PRIORITY, tmp); 2058 2059 mutex_unlock(&adev->grbm_idx_mutex); 2060 2061 udelay(50); 2062 } 2063 2064 /* 2065 * GPU scratch registers helpers function. 2066 */ 2067 /** 2068 * gfx_v7_0_scratch_init - setup driver info for CP scratch regs 2069 * 2070 * @adev: amdgpu_device pointer 2071 * 2072 * Set up the number and offset of the CP scratch registers. 2073 * NOTE: use of CP scratch registers is a legacy inferface and 2074 * is not used by default on newer asics (r6xx+). On newer asics, 2075 * memory buffers are used for fences rather than scratch regs. 2076 */ 2077 static void gfx_v7_0_scratch_init(struct amdgpu_device *adev) 2078 { 2079 adev->gfx.scratch.num_reg = 8; 2080 adev->gfx.scratch.reg_base = mmSCRATCH_REG0; 2081 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; 2082 } 2083 2084 /** 2085 * gfx_v7_0_ring_test_ring - basic gfx ring test 2086 * 2087 * @adev: amdgpu_device pointer 2088 * @ring: amdgpu_ring structure holding ring information 2089 * 2090 * Allocate a scratch register and write to it using the gfx ring (CIK). 2091 * Provides a basic gfx ring test to verify that the ring is working. 2092 * Used by gfx_v7_0_cp_gfx_resume(); 2093 * Returns 0 on success, error on failure. 2094 */ 2095 static int gfx_v7_0_ring_test_ring(struct amdgpu_ring *ring) 2096 { 2097 struct amdgpu_device *adev = ring->adev; 2098 uint32_t scratch; 2099 uint32_t tmp = 0; 2100 unsigned i; 2101 int r; 2102 2103 r = amdgpu_gfx_scratch_get(adev, &scratch); 2104 if (r) 2105 return r; 2106 2107 WREG32(scratch, 0xCAFEDEAD); 2108 r = amdgpu_ring_alloc(ring, 3); 2109 if (r) 2110 goto error_free_scratch; 2111 2112 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 2113 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); 2114 amdgpu_ring_write(ring, 0xDEADBEEF); 2115 amdgpu_ring_commit(ring); 2116 2117 for (i = 0; i < adev->usec_timeout; i++) { 2118 tmp = RREG32(scratch); 2119 if (tmp == 0xDEADBEEF) 2120 break; 2121 udelay(1); 2122 } 2123 if (i >= adev->usec_timeout) 2124 r = -ETIMEDOUT; 2125 2126 error_free_scratch: 2127 amdgpu_gfx_scratch_free(adev, scratch); 2128 return r; 2129 } 2130 2131 /** 2132 * gfx_v7_0_ring_emit_hdp - emit an hdp flush on the cp 2133 * 2134 * @adev: amdgpu_device pointer 2135 * @ridx: amdgpu ring index 2136 * 2137 * Emits an hdp flush on the cp. 2138 */ 2139 static void gfx_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 2140 { 2141 u32 ref_and_mask; 2142 int usepfp = ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE ? 0 : 1; 2143 2144 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 2145 switch (ring->me) { 2146 case 1: 2147 ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe; 2148 break; 2149 case 2: 2150 ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe; 2151 break; 2152 default: 2153 return; 2154 } 2155 } else { 2156 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK; 2157 } 2158 2159 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 2160 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */ 2161 WAIT_REG_MEM_FUNCTION(3) | /* == */ 2162 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */ 2163 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ); 2164 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE); 2165 amdgpu_ring_write(ring, ref_and_mask); 2166 amdgpu_ring_write(ring, ref_and_mask); 2167 amdgpu_ring_write(ring, 0x20); /* poll interval */ 2168 } 2169 2170 static void gfx_v7_0_ring_emit_vgt_flush(struct amdgpu_ring *ring) 2171 { 2172 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); 2173 amdgpu_ring_write(ring, EVENT_TYPE(VS_PARTIAL_FLUSH) | 2174 EVENT_INDEX(4)); 2175 2176 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); 2177 amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) | 2178 EVENT_INDEX(0)); 2179 } 2180 2181 /** 2182 * gfx_v7_0_ring_emit_fence_gfx - emit a fence on the gfx ring 2183 * 2184 * @adev: amdgpu_device pointer 2185 * @fence: amdgpu fence object 2186 * 2187 * Emits a fence sequnce number on the gfx ring and flushes 2188 * GPU caches. 2189 */ 2190 static void gfx_v7_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr, 2191 u64 seq, unsigned flags) 2192 { 2193 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 2194 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 2195 /* Workaround for cache flush problems. First send a dummy EOP 2196 * event down the pipe with seq one below. 2197 */ 2198 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 2199 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN | 2200 EOP_TC_ACTION_EN | 2201 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 2202 EVENT_INDEX(5))); 2203 amdgpu_ring_write(ring, addr & 0xfffffffc); 2204 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | 2205 DATA_SEL(1) | INT_SEL(0)); 2206 amdgpu_ring_write(ring, lower_32_bits(seq - 1)); 2207 amdgpu_ring_write(ring, upper_32_bits(seq - 1)); 2208 2209 /* Then send the real EOP event down the pipe. */ 2210 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 2211 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN | 2212 EOP_TC_ACTION_EN | 2213 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 2214 EVENT_INDEX(5))); 2215 amdgpu_ring_write(ring, addr & 0xfffffffc); 2216 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | 2217 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 2218 amdgpu_ring_write(ring, lower_32_bits(seq)); 2219 amdgpu_ring_write(ring, upper_32_bits(seq)); 2220 } 2221 2222 /** 2223 * gfx_v7_0_ring_emit_fence_compute - emit a fence on the compute ring 2224 * 2225 * @adev: amdgpu_device pointer 2226 * @fence: amdgpu fence object 2227 * 2228 * Emits a fence sequnce number on the compute ring and flushes 2229 * GPU caches. 2230 */ 2231 static void gfx_v7_0_ring_emit_fence_compute(struct amdgpu_ring *ring, 2232 u64 addr, u64 seq, 2233 unsigned flags) 2234 { 2235 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 2236 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 2237 2238 /* RELEASE_MEM - flush caches, send int */ 2239 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5)); 2240 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN | 2241 EOP_TC_ACTION_EN | 2242 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 2243 EVENT_INDEX(5))); 2244 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 2245 amdgpu_ring_write(ring, addr & 0xfffffffc); 2246 amdgpu_ring_write(ring, upper_32_bits(addr)); 2247 amdgpu_ring_write(ring, lower_32_bits(seq)); 2248 amdgpu_ring_write(ring, upper_32_bits(seq)); 2249 } 2250 2251 /* 2252 * IB stuff 2253 */ 2254 /** 2255 * gfx_v7_0_ring_emit_ib - emit an IB (Indirect Buffer) on the ring 2256 * 2257 * @ring: amdgpu_ring structure holding ring information 2258 * @ib: amdgpu indirect buffer object 2259 * 2260 * Emits an DE (drawing engine) or CE (constant engine) IB 2261 * on the gfx ring. IBs are usually generated by userspace 2262 * acceleration drivers and submitted to the kernel for 2263 * sheduling on the ring. This function schedules the IB 2264 * on the gfx ring for execution by the GPU. 2265 */ 2266 static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 2267 struct amdgpu_job *job, 2268 struct amdgpu_ib *ib, 2269 uint32_t flags) 2270 { 2271 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 2272 u32 header, control = 0; 2273 2274 /* insert SWITCH_BUFFER packet before first IB in the ring frame */ 2275 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 2276 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 2277 amdgpu_ring_write(ring, 0); 2278 } 2279 2280 if (ib->flags & AMDGPU_IB_FLAG_CE) 2281 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); 2282 else 2283 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 2284 2285 control |= ib->length_dw | (vmid << 24); 2286 2287 amdgpu_ring_write(ring, header); 2288 amdgpu_ring_write(ring, 2289 #ifdef __BIG_ENDIAN 2290 (2 << 0) | 2291 #endif 2292 (ib->gpu_addr & 0xFFFFFFFC)); 2293 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); 2294 amdgpu_ring_write(ring, control); 2295 } 2296 2297 static void gfx_v7_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 2298 struct amdgpu_job *job, 2299 struct amdgpu_ib *ib, 2300 uint32_t flags) 2301 { 2302 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 2303 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 2304 2305 /* Currently, there is a high possibility to get wave ID mismatch 2306 * between ME and GDS, leading to a hw deadlock, because ME generates 2307 * different wave IDs than the GDS expects. This situation happens 2308 * randomly when at least 5 compute pipes use GDS ordered append. 2309 * The wave IDs generated by ME are also wrong after suspend/resume. 2310 * Those are probably bugs somewhere else in the kernel driver. 2311 * 2312 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 2313 * GDS to 0 for this ring (me/pipe). 2314 */ 2315 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 2316 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2317 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID - PACKET3_SET_CONFIG_REG_START); 2318 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 2319 } 2320 2321 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 2322 amdgpu_ring_write(ring, 2323 #ifdef __BIG_ENDIAN 2324 (2 << 0) | 2325 #endif 2326 (ib->gpu_addr & 0xFFFFFFFC)); 2327 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); 2328 amdgpu_ring_write(ring, control); 2329 } 2330 2331 static void gfx_v7_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) 2332 { 2333 uint32_t dw2 = 0; 2334 2335 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 2336 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 2337 gfx_v7_0_ring_emit_vgt_flush(ring); 2338 /* set load_global_config & load_global_uconfig */ 2339 dw2 |= 0x8001; 2340 /* set load_cs_sh_regs */ 2341 dw2 |= 0x01000000; 2342 /* set load_per_context_state & load_gfx_sh_regs */ 2343 dw2 |= 0x10002; 2344 } 2345 2346 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 2347 amdgpu_ring_write(ring, dw2); 2348 amdgpu_ring_write(ring, 0); 2349 } 2350 2351 /** 2352 * gfx_v7_0_ring_test_ib - basic ring IB test 2353 * 2354 * @ring: amdgpu_ring structure holding ring information 2355 * 2356 * Allocate an IB and execute it on the gfx ring (CIK). 2357 * Provides a basic gfx ring test to verify that IBs are working. 2358 * Returns 0 on success, error on failure. 2359 */ 2360 static int gfx_v7_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 2361 { 2362 struct amdgpu_device *adev = ring->adev; 2363 struct amdgpu_ib ib; 2364 struct dma_fence *f = NULL; 2365 uint32_t scratch; 2366 uint32_t tmp = 0; 2367 long r; 2368 2369 r = amdgpu_gfx_scratch_get(adev, &scratch); 2370 if (r) 2371 return r; 2372 2373 WREG32(scratch, 0xCAFEDEAD); 2374 memset(&ib, 0, sizeof(ib)); 2375 r = amdgpu_ib_get(adev, NULL, 256, &ib); 2376 if (r) 2377 goto err1; 2378 2379 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1); 2380 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START)); 2381 ib.ptr[2] = 0xDEADBEEF; 2382 ib.length_dw = 3; 2383 2384 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 2385 if (r) 2386 goto err2; 2387 2388 r = dma_fence_wait_timeout(f, false, timeout); 2389 if (r == 0) { 2390 r = -ETIMEDOUT; 2391 goto err2; 2392 } else if (r < 0) { 2393 goto err2; 2394 } 2395 tmp = RREG32(scratch); 2396 if (tmp == 0xDEADBEEF) 2397 r = 0; 2398 else 2399 r = -EINVAL; 2400 2401 err2: 2402 amdgpu_ib_free(adev, &ib, NULL); 2403 dma_fence_put(f); 2404 err1: 2405 amdgpu_gfx_scratch_free(adev, scratch); 2406 return r; 2407 } 2408 2409 /* 2410 * CP. 2411 * On CIK, gfx and compute now have independant command processors. 2412 * 2413 * GFX 2414 * Gfx consists of a single ring and can process both gfx jobs and 2415 * compute jobs. The gfx CP consists of three microengines (ME): 2416 * PFP - Pre-Fetch Parser 2417 * ME - Micro Engine 2418 * CE - Constant Engine 2419 * The PFP and ME make up what is considered the Drawing Engine (DE). 2420 * The CE is an asynchronous engine used for updating buffer desciptors 2421 * used by the DE so that they can be loaded into cache in parallel 2422 * while the DE is processing state update packets. 2423 * 2424 * Compute 2425 * The compute CP consists of two microengines (ME): 2426 * MEC1 - Compute MicroEngine 1 2427 * MEC2 - Compute MicroEngine 2 2428 * Each MEC supports 4 compute pipes and each pipe supports 8 queues. 2429 * The queues are exposed to userspace and are programmed directly 2430 * by the compute runtime. 2431 */ 2432 /** 2433 * gfx_v7_0_cp_gfx_enable - enable/disable the gfx CP MEs 2434 * 2435 * @adev: amdgpu_device pointer 2436 * @enable: enable or disable the MEs 2437 * 2438 * Halts or unhalts the gfx MEs. 2439 */ 2440 static void gfx_v7_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 2441 { 2442 int i; 2443 2444 if (enable) { 2445 WREG32(mmCP_ME_CNTL, 0); 2446 } else { 2447 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK)); 2448 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 2449 adev->gfx.gfx_ring[i].sched.ready = false; 2450 } 2451 udelay(50); 2452 } 2453 2454 /** 2455 * gfx_v7_0_cp_gfx_load_microcode - load the gfx CP ME ucode 2456 * 2457 * @adev: amdgpu_device pointer 2458 * 2459 * Loads the gfx PFP, ME, and CE ucode. 2460 * Returns 0 for success, -EINVAL if the ucode is not available. 2461 */ 2462 static int gfx_v7_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 2463 { 2464 const struct gfx_firmware_header_v1_0 *pfp_hdr; 2465 const struct gfx_firmware_header_v1_0 *ce_hdr; 2466 const struct gfx_firmware_header_v1_0 *me_hdr; 2467 const __le32 *fw_data; 2468 unsigned i, fw_size; 2469 2470 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 2471 return -EINVAL; 2472 2473 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 2474 ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 2475 me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 2476 2477 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2478 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 2479 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 2480 adev->gfx.pfp_fw_version = le32_to_cpu(pfp_hdr->header.ucode_version); 2481 adev->gfx.ce_fw_version = le32_to_cpu(ce_hdr->header.ucode_version); 2482 adev->gfx.me_fw_version = le32_to_cpu(me_hdr->header.ucode_version); 2483 adev->gfx.me_feature_version = le32_to_cpu(me_hdr->ucode_feature_version); 2484 adev->gfx.ce_feature_version = le32_to_cpu(ce_hdr->ucode_feature_version); 2485 adev->gfx.pfp_feature_version = le32_to_cpu(pfp_hdr->ucode_feature_version); 2486 2487 gfx_v7_0_cp_gfx_enable(adev, false); 2488 2489 /* PFP */ 2490 fw_data = (const __le32 *) 2491 (adev->gfx.pfp_fw->data + 2492 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 2493 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4; 2494 WREG32(mmCP_PFP_UCODE_ADDR, 0); 2495 for (i = 0; i < fw_size; i++) 2496 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++)); 2497 WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 2498 2499 /* CE */ 2500 fw_data = (const __le32 *) 2501 (adev->gfx.ce_fw->data + 2502 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 2503 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4; 2504 WREG32(mmCP_CE_UCODE_ADDR, 0); 2505 for (i = 0; i < fw_size; i++) 2506 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++)); 2507 WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); 2508 2509 /* ME */ 2510 fw_data = (const __le32 *) 2511 (adev->gfx.me_fw->data + 2512 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 2513 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4; 2514 WREG32(mmCP_ME_RAM_WADDR, 0); 2515 for (i = 0; i < fw_size; i++) 2516 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++)); 2517 WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version); 2518 2519 return 0; 2520 } 2521 2522 /** 2523 * gfx_v7_0_cp_gfx_start - start the gfx ring 2524 * 2525 * @adev: amdgpu_device pointer 2526 * 2527 * Enables the ring and loads the clear state context and other 2528 * packets required to init the ring. 2529 * Returns 0 for success, error for failure. 2530 */ 2531 static int gfx_v7_0_cp_gfx_start(struct amdgpu_device *adev) 2532 { 2533 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; 2534 const struct cs_section_def *sect = NULL; 2535 const struct cs_extent_def *ext = NULL; 2536 int r, i; 2537 2538 /* init the CP */ 2539 WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1); 2540 WREG32(mmCP_ENDIAN_SWAP, 0); 2541 WREG32(mmCP_DEVICE_ID, 1); 2542 2543 gfx_v7_0_cp_gfx_enable(adev, true); 2544 2545 r = amdgpu_ring_alloc(ring, gfx_v7_0_get_csb_size(adev) + 8); 2546 if (r) { 2547 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 2548 return r; 2549 } 2550 2551 /* init the CE partitions. CE only used for gfx on CIK */ 2552 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 2553 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 2554 amdgpu_ring_write(ring, 0x8000); 2555 amdgpu_ring_write(ring, 0x8000); 2556 2557 /* clear state buffer */ 2558 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2559 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 2560 2561 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 2562 amdgpu_ring_write(ring, 0x80000000); 2563 amdgpu_ring_write(ring, 0x80000000); 2564 2565 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 2566 for (ext = sect->section; ext->extent != NULL; ++ext) { 2567 if (sect->id == SECT_CONTEXT) { 2568 amdgpu_ring_write(ring, 2569 PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 2570 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START); 2571 for (i = 0; i < ext->reg_count; i++) 2572 amdgpu_ring_write(ring, ext->extent[i]); 2573 } 2574 } 2575 } 2576 2577 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); 2578 amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); 2579 amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config); 2580 amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config_1); 2581 2582 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2583 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 2584 2585 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 2586 amdgpu_ring_write(ring, 0); 2587 2588 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); 2589 amdgpu_ring_write(ring, 0x00000316); 2590 amdgpu_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ 2591 amdgpu_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */ 2592 2593 amdgpu_ring_commit(ring); 2594 2595 return 0; 2596 } 2597 2598 /** 2599 * gfx_v7_0_cp_gfx_resume - setup the gfx ring buffer registers 2600 * 2601 * @adev: amdgpu_device pointer 2602 * 2603 * Program the location and size of the gfx ring buffer 2604 * and test it to make sure it's working. 2605 * Returns 0 for success, error for failure. 2606 */ 2607 static int gfx_v7_0_cp_gfx_resume(struct amdgpu_device *adev) 2608 { 2609 struct amdgpu_ring *ring; 2610 u32 tmp; 2611 u32 rb_bufsz; 2612 u64 rb_addr, rptr_addr; 2613 int r; 2614 2615 WREG32(mmCP_SEM_WAIT_TIMER, 0x0); 2616 if (adev->asic_type != CHIP_HAWAII) 2617 WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); 2618 2619 /* Set the write pointer delay */ 2620 WREG32(mmCP_RB_WPTR_DELAY, 0); 2621 2622 /* set the RB to use vmid 0 */ 2623 WREG32(mmCP_RB_VMID, 0); 2624 2625 WREG32(mmSCRATCH_ADDR, 0); 2626 2627 /* ring 0 - compute and gfx */ 2628 /* Set ring buffer size */ 2629 ring = &adev->gfx.gfx_ring[0]; 2630 rb_bufsz = order_base_2(ring->ring_size / 8); 2631 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2632 #ifdef __BIG_ENDIAN 2633 tmp |= 2 << CP_RB0_CNTL__BUF_SWAP__SHIFT; 2634 #endif 2635 WREG32(mmCP_RB0_CNTL, tmp); 2636 2637 /* Initialize the ring buffer's read and write pointers */ 2638 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK); 2639 ring->wptr = 0; 2640 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 2641 2642 /* set the wb address wether it's enabled or not */ 2643 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 2644 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 2645 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); 2646 2647 /* scratch register shadowing is no longer supported */ 2648 WREG32(mmSCRATCH_UMSK, 0); 2649 2650 mdelay(1); 2651 WREG32(mmCP_RB0_CNTL, tmp); 2652 2653 rb_addr = ring->gpu_addr >> 8; 2654 WREG32(mmCP_RB0_BASE, rb_addr); 2655 WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 2656 2657 /* start the ring */ 2658 gfx_v7_0_cp_gfx_start(adev); 2659 r = amdgpu_ring_test_helper(ring); 2660 if (r) 2661 return r; 2662 2663 return 0; 2664 } 2665 2666 static u64 gfx_v7_0_ring_get_rptr(struct amdgpu_ring *ring) 2667 { 2668 return ring->adev->wb.wb[ring->rptr_offs]; 2669 } 2670 2671 static u64 gfx_v7_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 2672 { 2673 struct amdgpu_device *adev = ring->adev; 2674 2675 return RREG32(mmCP_RB0_WPTR); 2676 } 2677 2678 static void gfx_v7_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 2679 { 2680 struct amdgpu_device *adev = ring->adev; 2681 2682 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 2683 (void)RREG32(mmCP_RB0_WPTR); 2684 } 2685 2686 static u64 gfx_v7_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 2687 { 2688 /* XXX check if swapping is necessary on BE */ 2689 return ring->adev->wb.wb[ring->wptr_offs]; 2690 } 2691 2692 static void gfx_v7_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 2693 { 2694 struct amdgpu_device *adev = ring->adev; 2695 2696 /* XXX check if swapping is necessary on BE */ 2697 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 2698 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 2699 } 2700 2701 /** 2702 * gfx_v7_0_cp_compute_enable - enable/disable the compute CP MEs 2703 * 2704 * @adev: amdgpu_device pointer 2705 * @enable: enable or disable the MEs 2706 * 2707 * Halts or unhalts the compute MEs. 2708 */ 2709 static void gfx_v7_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 2710 { 2711 int i; 2712 2713 if (enable) { 2714 WREG32(mmCP_MEC_CNTL, 0); 2715 } else { 2716 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 2717 for (i = 0; i < adev->gfx.num_compute_rings; i++) 2718 adev->gfx.compute_ring[i].sched.ready = false; 2719 } 2720 udelay(50); 2721 } 2722 2723 /** 2724 * gfx_v7_0_cp_compute_load_microcode - load the compute CP ME ucode 2725 * 2726 * @adev: amdgpu_device pointer 2727 * 2728 * Loads the compute MEC1&2 ucode. 2729 * Returns 0 for success, -EINVAL if the ucode is not available. 2730 */ 2731 static int gfx_v7_0_cp_compute_load_microcode(struct amdgpu_device *adev) 2732 { 2733 const struct gfx_firmware_header_v1_0 *mec_hdr; 2734 const __le32 *fw_data; 2735 unsigned i, fw_size; 2736 2737 if (!adev->gfx.mec_fw) 2738 return -EINVAL; 2739 2740 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 2741 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 2742 adev->gfx.mec_fw_version = le32_to_cpu(mec_hdr->header.ucode_version); 2743 adev->gfx.mec_feature_version = le32_to_cpu( 2744 mec_hdr->ucode_feature_version); 2745 2746 gfx_v7_0_cp_compute_enable(adev, false); 2747 2748 /* MEC1 */ 2749 fw_data = (const __le32 *) 2750 (adev->gfx.mec_fw->data + 2751 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 2752 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4; 2753 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0); 2754 for (i = 0; i < fw_size; i++) 2755 WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data++)); 2756 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0); 2757 2758 if (adev->asic_type == CHIP_KAVERI) { 2759 const struct gfx_firmware_header_v1_0 *mec2_hdr; 2760 2761 if (!adev->gfx.mec2_fw) 2762 return -EINVAL; 2763 2764 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data; 2765 amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header); 2766 adev->gfx.mec2_fw_version = le32_to_cpu(mec2_hdr->header.ucode_version); 2767 adev->gfx.mec2_feature_version = le32_to_cpu( 2768 mec2_hdr->ucode_feature_version); 2769 2770 /* MEC2 */ 2771 fw_data = (const __le32 *) 2772 (adev->gfx.mec2_fw->data + 2773 le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes)); 2774 fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4; 2775 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0); 2776 for (i = 0; i < fw_size; i++) 2777 WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data++)); 2778 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0); 2779 } 2780 2781 return 0; 2782 } 2783 2784 /** 2785 * gfx_v7_0_cp_compute_fini - stop the compute queues 2786 * 2787 * @adev: amdgpu_device pointer 2788 * 2789 * Stop the compute queues and tear down the driver queue 2790 * info. 2791 */ 2792 static void gfx_v7_0_cp_compute_fini(struct amdgpu_device *adev) 2793 { 2794 int i; 2795 2796 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2797 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; 2798 2799 amdgpu_bo_free_kernel(&ring->mqd_obj, NULL, NULL); 2800 } 2801 } 2802 2803 static void gfx_v7_0_mec_fini(struct amdgpu_device *adev) 2804 { 2805 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 2806 } 2807 2808 static int gfx_v7_0_mec_init(struct amdgpu_device *adev) 2809 { 2810 int r; 2811 u32 *hpd; 2812 size_t mec_hpd_size; 2813 2814 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 2815 2816 /* take ownership of the relevant compute queues */ 2817 amdgpu_gfx_compute_queue_acquire(adev); 2818 2819 /* allocate space for ALL pipes (even the ones we don't own) */ 2820 mec_hpd_size = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec 2821 * GFX7_MEC_HPD_SIZE * 2; 2822 2823 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 2824 AMDGPU_GEM_DOMAIN_VRAM, 2825 &adev->gfx.mec.hpd_eop_obj, 2826 &adev->gfx.mec.hpd_eop_gpu_addr, 2827 (void **)&hpd); 2828 if (r) { 2829 dev_warn(adev->dev, "(%d) create, pin or map of HDP EOP bo failed\n", r); 2830 gfx_v7_0_mec_fini(adev); 2831 return r; 2832 } 2833 2834 /* clear memory. Not sure if this is required or not */ 2835 memset(hpd, 0, mec_hpd_size); 2836 2837 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 2838 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 2839 2840 return 0; 2841 } 2842 2843 struct hqd_registers 2844 { 2845 u32 cp_mqd_base_addr; 2846 u32 cp_mqd_base_addr_hi; 2847 u32 cp_hqd_active; 2848 u32 cp_hqd_vmid; 2849 u32 cp_hqd_persistent_state; 2850 u32 cp_hqd_pipe_priority; 2851 u32 cp_hqd_queue_priority; 2852 u32 cp_hqd_quantum; 2853 u32 cp_hqd_pq_base; 2854 u32 cp_hqd_pq_base_hi; 2855 u32 cp_hqd_pq_rptr; 2856 u32 cp_hqd_pq_rptr_report_addr; 2857 u32 cp_hqd_pq_rptr_report_addr_hi; 2858 u32 cp_hqd_pq_wptr_poll_addr; 2859 u32 cp_hqd_pq_wptr_poll_addr_hi; 2860 u32 cp_hqd_pq_doorbell_control; 2861 u32 cp_hqd_pq_wptr; 2862 u32 cp_hqd_pq_control; 2863 u32 cp_hqd_ib_base_addr; 2864 u32 cp_hqd_ib_base_addr_hi; 2865 u32 cp_hqd_ib_rptr; 2866 u32 cp_hqd_ib_control; 2867 u32 cp_hqd_iq_timer; 2868 u32 cp_hqd_iq_rptr; 2869 u32 cp_hqd_dequeue_request; 2870 u32 cp_hqd_dma_offload; 2871 u32 cp_hqd_sema_cmd; 2872 u32 cp_hqd_msg_type; 2873 u32 cp_hqd_atomic0_preop_lo; 2874 u32 cp_hqd_atomic0_preop_hi; 2875 u32 cp_hqd_atomic1_preop_lo; 2876 u32 cp_hqd_atomic1_preop_hi; 2877 u32 cp_hqd_hq_scheduler0; 2878 u32 cp_hqd_hq_scheduler1; 2879 u32 cp_mqd_control; 2880 }; 2881 2882 static void gfx_v7_0_compute_pipe_init(struct amdgpu_device *adev, 2883 int mec, int pipe) 2884 { 2885 u64 eop_gpu_addr; 2886 u32 tmp; 2887 size_t eop_offset = (mec * adev->gfx.mec.num_pipe_per_mec + pipe) 2888 * GFX7_MEC_HPD_SIZE * 2; 2889 2890 mutex_lock(&adev->srbm_mutex); 2891 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + eop_offset; 2892 2893 cik_srbm_select(adev, mec + 1, pipe, 0, 0); 2894 2895 /* write the EOP addr */ 2896 WREG32(mmCP_HPD_EOP_BASE_ADDR, eop_gpu_addr >> 8); 2897 WREG32(mmCP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8); 2898 2899 /* set the VMID assigned */ 2900 WREG32(mmCP_HPD_EOP_VMID, 0); 2901 2902 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 2903 tmp = RREG32(mmCP_HPD_EOP_CONTROL); 2904 tmp &= ~CP_HPD_EOP_CONTROL__EOP_SIZE_MASK; 2905 tmp |= order_base_2(GFX7_MEC_HPD_SIZE / 8); 2906 WREG32(mmCP_HPD_EOP_CONTROL, tmp); 2907 2908 cik_srbm_select(adev, 0, 0, 0, 0); 2909 mutex_unlock(&adev->srbm_mutex); 2910 } 2911 2912 static int gfx_v7_0_mqd_deactivate(struct amdgpu_device *adev) 2913 { 2914 int i; 2915 2916 /* disable the queue if it's active */ 2917 if (RREG32(mmCP_HQD_ACTIVE) & 1) { 2918 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1); 2919 for (i = 0; i < adev->usec_timeout; i++) { 2920 if (!(RREG32(mmCP_HQD_ACTIVE) & 1)) 2921 break; 2922 udelay(1); 2923 } 2924 2925 if (i == adev->usec_timeout) 2926 return -ETIMEDOUT; 2927 2928 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 0); 2929 WREG32(mmCP_HQD_PQ_RPTR, 0); 2930 WREG32(mmCP_HQD_PQ_WPTR, 0); 2931 } 2932 2933 return 0; 2934 } 2935 2936 static void gfx_v7_0_mqd_init(struct amdgpu_device *adev, 2937 struct cik_mqd *mqd, 2938 uint64_t mqd_gpu_addr, 2939 struct amdgpu_ring *ring) 2940 { 2941 u64 hqd_gpu_addr; 2942 u64 wb_gpu_addr; 2943 2944 /* init the mqd struct */ 2945 memset(mqd, 0, sizeof(struct cik_mqd)); 2946 2947 mqd->header = 0xC0310800; 2948 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 2949 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 2950 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 2951 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 2952 2953 /* enable doorbell? */ 2954 mqd->cp_hqd_pq_doorbell_control = 2955 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL); 2956 if (ring->use_doorbell) 2957 mqd->cp_hqd_pq_doorbell_control |= CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK; 2958 else 2959 mqd->cp_hqd_pq_doorbell_control &= ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK; 2960 2961 /* set the pointer to the MQD */ 2962 mqd->cp_mqd_base_addr_lo = mqd_gpu_addr & 0xfffffffc; 2963 mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr); 2964 2965 /* set MQD vmid to 0 */ 2966 mqd->cp_mqd_control = RREG32(mmCP_MQD_CONTROL); 2967 mqd->cp_mqd_control &= ~CP_MQD_CONTROL__VMID_MASK; 2968 2969 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 2970 hqd_gpu_addr = ring->gpu_addr >> 8; 2971 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 2972 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 2973 2974 /* set up the HQD, this is similar to CP_RB0_CNTL */ 2975 mqd->cp_hqd_pq_control = RREG32(mmCP_HQD_PQ_CONTROL); 2976 mqd->cp_hqd_pq_control &= 2977 ~(CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK | 2978 CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK); 2979 2980 mqd->cp_hqd_pq_control |= 2981 order_base_2(ring->ring_size / 8); 2982 mqd->cp_hqd_pq_control |= 2983 (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8); 2984 #ifdef __BIG_ENDIAN 2985 mqd->cp_hqd_pq_control |= 2986 2 << CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT; 2987 #endif 2988 mqd->cp_hqd_pq_control &= 2989 ~(CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK | 2990 CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK | 2991 CP_HQD_PQ_CONTROL__PQ_VOLATILE_MASK); 2992 mqd->cp_hqd_pq_control |= 2993 CP_HQD_PQ_CONTROL__PRIV_STATE_MASK | 2994 CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK; /* assuming kernel queue control */ 2995 2996 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 2997 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 2998 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 2999 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3000 3001 /* set the wb address wether it's enabled or not */ 3002 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 3003 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 3004 mqd->cp_hqd_pq_rptr_report_addr_hi = 3005 upper_32_bits(wb_gpu_addr) & 0xffff; 3006 3007 /* enable the doorbell if requested */ 3008 if (ring->use_doorbell) { 3009 mqd->cp_hqd_pq_doorbell_control = 3010 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL); 3011 mqd->cp_hqd_pq_doorbell_control &= 3012 ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK; 3013 mqd->cp_hqd_pq_doorbell_control |= 3014 (ring->doorbell_index << 3015 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT); 3016 mqd->cp_hqd_pq_doorbell_control |= 3017 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK; 3018 mqd->cp_hqd_pq_doorbell_control &= 3019 ~(CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK | 3020 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK); 3021 3022 } else { 3023 mqd->cp_hqd_pq_doorbell_control = 0; 3024 } 3025 3026 /* read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3027 ring->wptr = 0; 3028 mqd->cp_hqd_pq_wptr = lower_32_bits(ring->wptr); 3029 mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR); 3030 3031 /* set the vmid for the queue */ 3032 mqd->cp_hqd_vmid = 0; 3033 3034 /* defaults */ 3035 mqd->cp_hqd_ib_control = RREG32(mmCP_HQD_IB_CONTROL); 3036 mqd->cp_hqd_ib_base_addr_lo = RREG32(mmCP_HQD_IB_BASE_ADDR); 3037 mqd->cp_hqd_ib_base_addr_hi = RREG32(mmCP_HQD_IB_BASE_ADDR_HI); 3038 mqd->cp_hqd_ib_rptr = RREG32(mmCP_HQD_IB_RPTR); 3039 mqd->cp_hqd_persistent_state = RREG32(mmCP_HQD_PERSISTENT_STATE); 3040 mqd->cp_hqd_sema_cmd = RREG32(mmCP_HQD_SEMA_CMD); 3041 mqd->cp_hqd_msg_type = RREG32(mmCP_HQD_MSG_TYPE); 3042 mqd->cp_hqd_atomic0_preop_lo = RREG32(mmCP_HQD_ATOMIC0_PREOP_LO); 3043 mqd->cp_hqd_atomic0_preop_hi = RREG32(mmCP_HQD_ATOMIC0_PREOP_HI); 3044 mqd->cp_hqd_atomic1_preop_lo = RREG32(mmCP_HQD_ATOMIC1_PREOP_LO); 3045 mqd->cp_hqd_atomic1_preop_hi = RREG32(mmCP_HQD_ATOMIC1_PREOP_HI); 3046 mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR); 3047 mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM); 3048 mqd->cp_hqd_pipe_priority = RREG32(mmCP_HQD_PIPE_PRIORITY); 3049 mqd->cp_hqd_queue_priority = RREG32(mmCP_HQD_QUEUE_PRIORITY); 3050 mqd->cp_hqd_iq_rptr = RREG32(mmCP_HQD_IQ_RPTR); 3051 3052 /* activate the queue */ 3053 mqd->cp_hqd_active = 1; 3054 } 3055 3056 int gfx_v7_0_mqd_commit(struct amdgpu_device *adev, struct cik_mqd *mqd) 3057 { 3058 uint32_t tmp; 3059 uint32_t mqd_reg; 3060 uint32_t *mqd_data; 3061 3062 /* HQD registers extend from mmCP_MQD_BASE_ADDR to mmCP_MQD_CONTROL */ 3063 mqd_data = &mqd->cp_mqd_base_addr_lo; 3064 3065 /* disable wptr polling */ 3066 tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL); 3067 tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0); 3068 WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp); 3069 3070 /* program all HQD registers */ 3071 for (mqd_reg = mmCP_HQD_VMID; mqd_reg <= mmCP_MQD_CONTROL; mqd_reg++) 3072 WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]); 3073 3074 /* activate the HQD */ 3075 for (mqd_reg = mmCP_MQD_BASE_ADDR; mqd_reg <= mmCP_HQD_ACTIVE; mqd_reg++) 3076 WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]); 3077 3078 return 0; 3079 } 3080 3081 static int gfx_v7_0_compute_queue_init(struct amdgpu_device *adev, int ring_id) 3082 { 3083 int r; 3084 u64 mqd_gpu_addr; 3085 struct cik_mqd *mqd; 3086 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; 3087 3088 r = amdgpu_bo_create_reserved(adev, sizeof(struct cik_mqd), PAGE_SIZE, 3089 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, 3090 &mqd_gpu_addr, (void **)&mqd); 3091 if (r) { 3092 dev_warn(adev->dev, "(%d) create MQD bo failed\n", r); 3093 return r; 3094 } 3095 3096 mutex_lock(&adev->srbm_mutex); 3097 cik_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3098 3099 gfx_v7_0_mqd_init(adev, mqd, mqd_gpu_addr, ring); 3100 gfx_v7_0_mqd_deactivate(adev); 3101 gfx_v7_0_mqd_commit(adev, mqd); 3102 3103 cik_srbm_select(adev, 0, 0, 0, 0); 3104 mutex_unlock(&adev->srbm_mutex); 3105 3106 amdgpu_bo_kunmap(ring->mqd_obj); 3107 amdgpu_bo_unreserve(ring->mqd_obj); 3108 return 0; 3109 } 3110 3111 /** 3112 * gfx_v7_0_cp_compute_resume - setup the compute queue registers 3113 * 3114 * @adev: amdgpu_device pointer 3115 * 3116 * Program the compute queues and test them to make sure they 3117 * are working. 3118 * Returns 0 for success, error for failure. 3119 */ 3120 static int gfx_v7_0_cp_compute_resume(struct amdgpu_device *adev) 3121 { 3122 int r, i, j; 3123 u32 tmp; 3124 struct amdgpu_ring *ring; 3125 3126 /* fix up chicken bits */ 3127 tmp = RREG32(mmCP_CPF_DEBUG); 3128 tmp |= (1 << 23); 3129 WREG32(mmCP_CPF_DEBUG, tmp); 3130 3131 /* init all pipes (even the ones we don't own) */ 3132 for (i = 0; i < adev->gfx.mec.num_mec; i++) 3133 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) 3134 gfx_v7_0_compute_pipe_init(adev, i, j); 3135 3136 /* init the queues */ 3137 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3138 r = gfx_v7_0_compute_queue_init(adev, i); 3139 if (r) { 3140 gfx_v7_0_cp_compute_fini(adev); 3141 return r; 3142 } 3143 } 3144 3145 gfx_v7_0_cp_compute_enable(adev, true); 3146 3147 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3148 ring = &adev->gfx.compute_ring[i]; 3149 amdgpu_ring_test_helper(ring); 3150 } 3151 3152 return 0; 3153 } 3154 3155 static void gfx_v7_0_cp_enable(struct amdgpu_device *adev, bool enable) 3156 { 3157 gfx_v7_0_cp_gfx_enable(adev, enable); 3158 gfx_v7_0_cp_compute_enable(adev, enable); 3159 } 3160 3161 static int gfx_v7_0_cp_load_microcode(struct amdgpu_device *adev) 3162 { 3163 int r; 3164 3165 r = gfx_v7_0_cp_gfx_load_microcode(adev); 3166 if (r) 3167 return r; 3168 r = gfx_v7_0_cp_compute_load_microcode(adev); 3169 if (r) 3170 return r; 3171 3172 return 0; 3173 } 3174 3175 static void gfx_v7_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 3176 bool enable) 3177 { 3178 u32 tmp = RREG32(mmCP_INT_CNTL_RING0); 3179 3180 if (enable) 3181 tmp |= (CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK | 3182 CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK); 3183 else 3184 tmp &= ~(CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK | 3185 CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK); 3186 WREG32(mmCP_INT_CNTL_RING0, tmp); 3187 } 3188 3189 static int gfx_v7_0_cp_resume(struct amdgpu_device *adev) 3190 { 3191 int r; 3192 3193 gfx_v7_0_enable_gui_idle_interrupt(adev, false); 3194 3195 r = gfx_v7_0_cp_load_microcode(adev); 3196 if (r) 3197 return r; 3198 3199 r = gfx_v7_0_cp_gfx_resume(adev); 3200 if (r) 3201 return r; 3202 r = gfx_v7_0_cp_compute_resume(adev); 3203 if (r) 3204 return r; 3205 3206 gfx_v7_0_enable_gui_idle_interrupt(adev, true); 3207 3208 return 0; 3209 } 3210 3211 /** 3212 * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP 3213 * 3214 * @ring: the ring to emmit the commands to 3215 * 3216 * Sync the command pipeline with the PFP. E.g. wait for everything 3217 * to be completed. 3218 */ 3219 static void gfx_v7_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 3220 { 3221 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 3222 uint32_t seq = ring->fence_drv.sync_seq; 3223 uint64_t addr = ring->fence_drv.gpu_addr; 3224 3225 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 3226 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */ 3227 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 3228 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */ 3229 amdgpu_ring_write(ring, addr & 0xfffffffc); 3230 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 3231 amdgpu_ring_write(ring, seq); 3232 amdgpu_ring_write(ring, 0xffffffff); 3233 amdgpu_ring_write(ring, 4); /* poll interval */ 3234 3235 if (usepfp) { 3236 /* synce CE with ME to prevent CE fetch CEIB before context switch done */ 3237 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 3238 amdgpu_ring_write(ring, 0); 3239 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 3240 amdgpu_ring_write(ring, 0); 3241 } 3242 } 3243 3244 /* 3245 * vm 3246 * VMID 0 is the physical GPU addresses as used by the kernel. 3247 * VMIDs 1-15 are used for userspace clients and are handled 3248 * by the amdgpu vm/hsa code. 3249 */ 3250 /** 3251 * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP 3252 * 3253 * @adev: amdgpu_device pointer 3254 * 3255 * Update the page table base and flush the VM TLB 3256 * using the CP (CIK). 3257 */ 3258 static void gfx_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 3259 unsigned vmid, uint64_t pd_addr) 3260 { 3261 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 3262 3263 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 3264 3265 /* wait for the invalidate to complete */ 3266 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 3267 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */ 3268 WAIT_REG_MEM_FUNCTION(0) | /* always */ 3269 WAIT_REG_MEM_ENGINE(0))); /* me */ 3270 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); 3271 amdgpu_ring_write(ring, 0); 3272 amdgpu_ring_write(ring, 0); /* ref */ 3273 amdgpu_ring_write(ring, 0); /* mask */ 3274 amdgpu_ring_write(ring, 0x20); /* poll interval */ 3275 3276 /* compute doesn't have PFP */ 3277 if (usepfp) { 3278 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 3279 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 3280 amdgpu_ring_write(ring, 0x0); 3281 3282 /* synce CE with ME to prevent CE fetch CEIB before context switch done */ 3283 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 3284 amdgpu_ring_write(ring, 0); 3285 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 3286 amdgpu_ring_write(ring, 0); 3287 } 3288 } 3289 3290 static void gfx_v7_0_ring_emit_wreg(struct amdgpu_ring *ring, 3291 uint32_t reg, uint32_t val) 3292 { 3293 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 3294 3295 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3296 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | 3297 WRITE_DATA_DST_SEL(0))); 3298 amdgpu_ring_write(ring, reg); 3299 amdgpu_ring_write(ring, 0); 3300 amdgpu_ring_write(ring, val); 3301 } 3302 3303 /* 3304 * RLC 3305 * The RLC is a multi-purpose microengine that handles a 3306 * variety of functions. 3307 */ 3308 static int gfx_v7_0_rlc_init(struct amdgpu_device *adev) 3309 { 3310 const u32 *src_ptr; 3311 u32 dws; 3312 const struct cs_section_def *cs_data; 3313 int r; 3314 3315 /* allocate rlc buffers */ 3316 if (adev->flags & AMD_IS_APU) { 3317 if (adev->asic_type == CHIP_KAVERI) { 3318 adev->gfx.rlc.reg_list = spectre_rlc_save_restore_register_list; 3319 adev->gfx.rlc.reg_list_size = 3320 (u32)ARRAY_SIZE(spectre_rlc_save_restore_register_list); 3321 } else { 3322 adev->gfx.rlc.reg_list = kalindi_rlc_save_restore_register_list; 3323 adev->gfx.rlc.reg_list_size = 3324 (u32)ARRAY_SIZE(kalindi_rlc_save_restore_register_list); 3325 } 3326 } 3327 adev->gfx.rlc.cs_data = ci_cs_data; 3328 adev->gfx.rlc.cp_table_size = ALIGN(CP_ME_TABLE_SIZE * 5 * 4, 2048); /* CP JT */ 3329 adev->gfx.rlc.cp_table_size += 64 * 1024; /* GDS */ 3330 3331 src_ptr = adev->gfx.rlc.reg_list; 3332 dws = adev->gfx.rlc.reg_list_size; 3333 dws += (5 * 16) + 48 + 48 + 64; 3334 3335 cs_data = adev->gfx.rlc.cs_data; 3336 3337 if (src_ptr) { 3338 /* init save restore block */ 3339 r = amdgpu_gfx_rlc_init_sr(adev, dws); 3340 if (r) 3341 return r; 3342 } 3343 3344 if (cs_data) { 3345 /* init clear state block */ 3346 r = amdgpu_gfx_rlc_init_csb(adev); 3347 if (r) 3348 return r; 3349 } 3350 3351 if (adev->gfx.rlc.cp_table_size) { 3352 r = amdgpu_gfx_rlc_init_cpt(adev); 3353 if (r) 3354 return r; 3355 } 3356 3357 return 0; 3358 } 3359 3360 static void gfx_v7_0_enable_lbpw(struct amdgpu_device *adev, bool enable) 3361 { 3362 u32 tmp; 3363 3364 tmp = RREG32(mmRLC_LB_CNTL); 3365 if (enable) 3366 tmp |= RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK; 3367 else 3368 tmp &= ~RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK; 3369 WREG32(mmRLC_LB_CNTL, tmp); 3370 } 3371 3372 static void gfx_v7_0_wait_for_rlc_serdes(struct amdgpu_device *adev) 3373 { 3374 u32 i, j, k; 3375 u32 mask; 3376 3377 mutex_lock(&adev->grbm_idx_mutex); 3378 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 3379 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 3380 gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff); 3381 for (k = 0; k < adev->usec_timeout; k++) { 3382 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0) 3383 break; 3384 udelay(1); 3385 } 3386 } 3387 } 3388 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 3389 mutex_unlock(&adev->grbm_idx_mutex); 3390 3391 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | 3392 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK | 3393 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK | 3394 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK; 3395 for (k = 0; k < adev->usec_timeout; k++) { 3396 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) 3397 break; 3398 udelay(1); 3399 } 3400 } 3401 3402 static void gfx_v7_0_update_rlc(struct amdgpu_device *adev, u32 rlc) 3403 { 3404 u32 tmp; 3405 3406 tmp = RREG32(mmRLC_CNTL); 3407 if (tmp != rlc) 3408 WREG32(mmRLC_CNTL, rlc); 3409 } 3410 3411 static u32 gfx_v7_0_halt_rlc(struct amdgpu_device *adev) 3412 { 3413 u32 data, orig; 3414 3415 orig = data = RREG32(mmRLC_CNTL); 3416 3417 if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) { 3418 u32 i; 3419 3420 data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK; 3421 WREG32(mmRLC_CNTL, data); 3422 3423 for (i = 0; i < adev->usec_timeout; i++) { 3424 if ((RREG32(mmRLC_GPM_STAT) & RLC_GPM_STAT__RLC_BUSY_MASK) == 0) 3425 break; 3426 udelay(1); 3427 } 3428 3429 gfx_v7_0_wait_for_rlc_serdes(adev); 3430 } 3431 3432 return orig; 3433 } 3434 3435 static bool gfx_v7_0_is_rlc_enabled(struct amdgpu_device *adev) 3436 { 3437 return true; 3438 } 3439 3440 static void gfx_v7_0_set_safe_mode(struct amdgpu_device *adev) 3441 { 3442 u32 tmp, i, mask; 3443 3444 tmp = 0x1 | (1 << 1); 3445 WREG32(mmRLC_GPR_REG2, tmp); 3446 3447 mask = RLC_GPM_STAT__GFX_POWER_STATUS_MASK | 3448 RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK; 3449 for (i = 0; i < adev->usec_timeout; i++) { 3450 if ((RREG32(mmRLC_GPM_STAT) & mask) == mask) 3451 break; 3452 udelay(1); 3453 } 3454 3455 for (i = 0; i < adev->usec_timeout; i++) { 3456 if ((RREG32(mmRLC_GPR_REG2) & 0x1) == 0) 3457 break; 3458 udelay(1); 3459 } 3460 } 3461 3462 static void gfx_v7_0_unset_safe_mode(struct amdgpu_device *adev) 3463 { 3464 u32 tmp; 3465 3466 tmp = 0x1 | (0 << 1); 3467 WREG32(mmRLC_GPR_REG2, tmp); 3468 } 3469 3470 /** 3471 * gfx_v7_0_rlc_stop - stop the RLC ME 3472 * 3473 * @adev: amdgpu_device pointer 3474 * 3475 * Halt the RLC ME (MicroEngine) (CIK). 3476 */ 3477 static void gfx_v7_0_rlc_stop(struct amdgpu_device *adev) 3478 { 3479 WREG32(mmRLC_CNTL, 0); 3480 3481 gfx_v7_0_enable_gui_idle_interrupt(adev, false); 3482 3483 gfx_v7_0_wait_for_rlc_serdes(adev); 3484 } 3485 3486 /** 3487 * gfx_v7_0_rlc_start - start the RLC ME 3488 * 3489 * @adev: amdgpu_device pointer 3490 * 3491 * Unhalt the RLC ME (MicroEngine) (CIK). 3492 */ 3493 static void gfx_v7_0_rlc_start(struct amdgpu_device *adev) 3494 { 3495 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); 3496 3497 gfx_v7_0_enable_gui_idle_interrupt(adev, true); 3498 3499 udelay(50); 3500 } 3501 3502 static void gfx_v7_0_rlc_reset(struct amdgpu_device *adev) 3503 { 3504 u32 tmp = RREG32(mmGRBM_SOFT_RESET); 3505 3506 tmp |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK; 3507 WREG32(mmGRBM_SOFT_RESET, tmp); 3508 udelay(50); 3509 tmp &= ~GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK; 3510 WREG32(mmGRBM_SOFT_RESET, tmp); 3511 udelay(50); 3512 } 3513 3514 /** 3515 * gfx_v7_0_rlc_resume - setup the RLC hw 3516 * 3517 * @adev: amdgpu_device pointer 3518 * 3519 * Initialize the RLC registers, load the ucode, 3520 * and start the RLC (CIK). 3521 * Returns 0 for success, -EINVAL if the ucode is not available. 3522 */ 3523 static int gfx_v7_0_rlc_resume(struct amdgpu_device *adev) 3524 { 3525 const struct rlc_firmware_header_v1_0 *hdr; 3526 const __le32 *fw_data; 3527 unsigned i, fw_size; 3528 u32 tmp; 3529 3530 if (!adev->gfx.rlc_fw) 3531 return -EINVAL; 3532 3533 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data; 3534 amdgpu_ucode_print_rlc_hdr(&hdr->header); 3535 adev->gfx.rlc_fw_version = le32_to_cpu(hdr->header.ucode_version); 3536 adev->gfx.rlc_feature_version = le32_to_cpu( 3537 hdr->ucode_feature_version); 3538 3539 adev->gfx.rlc.funcs->stop(adev); 3540 3541 /* disable CG */ 3542 tmp = RREG32(mmRLC_CGCG_CGLS_CTRL) & 0xfffffffc; 3543 WREG32(mmRLC_CGCG_CGLS_CTRL, tmp); 3544 3545 adev->gfx.rlc.funcs->reset(adev); 3546 3547 gfx_v7_0_init_pg(adev); 3548 3549 WREG32(mmRLC_LB_CNTR_INIT, 0); 3550 WREG32(mmRLC_LB_CNTR_MAX, 0x00008000); 3551 3552 mutex_lock(&adev->grbm_idx_mutex); 3553 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 3554 WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff); 3555 WREG32(mmRLC_LB_PARAMS, 0x00600408); 3556 WREG32(mmRLC_LB_CNTL, 0x80000004); 3557 mutex_unlock(&adev->grbm_idx_mutex); 3558 3559 WREG32(mmRLC_MC_CNTL, 0); 3560 WREG32(mmRLC_UCODE_CNTL, 0); 3561 3562 fw_data = (const __le32 *) 3563 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 3564 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 3565 WREG32(mmRLC_GPM_UCODE_ADDR, 0); 3566 for (i = 0; i < fw_size; i++) 3567 WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); 3568 WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 3569 3570 /* XXX - find out what chips support lbpw */ 3571 gfx_v7_0_enable_lbpw(adev, false); 3572 3573 if (adev->asic_type == CHIP_BONAIRE) 3574 WREG32(mmRLC_DRIVER_CPDMA_STATUS, 0); 3575 3576 adev->gfx.rlc.funcs->start(adev); 3577 3578 return 0; 3579 } 3580 3581 static void gfx_v7_0_enable_cgcg(struct amdgpu_device *adev, bool enable) 3582 { 3583 u32 data, orig, tmp, tmp2; 3584 3585 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL); 3586 3587 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 3588 gfx_v7_0_enable_gui_idle_interrupt(adev, true); 3589 3590 tmp = gfx_v7_0_halt_rlc(adev); 3591 3592 mutex_lock(&adev->grbm_idx_mutex); 3593 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 3594 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); 3595 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); 3596 tmp2 = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK | 3597 RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_0_MASK | 3598 RLC_SERDES_WR_CTRL__CGLS_ENABLE_MASK; 3599 WREG32(mmRLC_SERDES_WR_CTRL, tmp2); 3600 mutex_unlock(&adev->grbm_idx_mutex); 3601 3602 gfx_v7_0_update_rlc(adev, tmp); 3603 3604 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 3605 if (orig != data) 3606 WREG32(mmRLC_CGCG_CGLS_CTRL, data); 3607 3608 } else { 3609 gfx_v7_0_enable_gui_idle_interrupt(adev, false); 3610 3611 RREG32(mmCB_CGTT_SCLK_CTRL); 3612 RREG32(mmCB_CGTT_SCLK_CTRL); 3613 RREG32(mmCB_CGTT_SCLK_CTRL); 3614 RREG32(mmCB_CGTT_SCLK_CTRL); 3615 3616 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 3617 if (orig != data) 3618 WREG32(mmRLC_CGCG_CGLS_CTRL, data); 3619 3620 gfx_v7_0_enable_gui_idle_interrupt(adev, true); 3621 } 3622 } 3623 3624 static void gfx_v7_0_enable_mgcg(struct amdgpu_device *adev, bool enable) 3625 { 3626 u32 data, orig, tmp = 0; 3627 3628 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 3629 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 3630 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 3631 orig = data = RREG32(mmCP_MEM_SLP_CNTL); 3632 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 3633 if (orig != data) 3634 WREG32(mmCP_MEM_SLP_CNTL, data); 3635 } 3636 } 3637 3638 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); 3639 data |= 0x00000001; 3640 data &= 0xfffffffd; 3641 if (orig != data) 3642 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data); 3643 3644 tmp = gfx_v7_0_halt_rlc(adev); 3645 3646 mutex_lock(&adev->grbm_idx_mutex); 3647 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 3648 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); 3649 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); 3650 data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK | 3651 RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0_MASK; 3652 WREG32(mmRLC_SERDES_WR_CTRL, data); 3653 mutex_unlock(&adev->grbm_idx_mutex); 3654 3655 gfx_v7_0_update_rlc(adev, tmp); 3656 3657 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS) { 3658 orig = data = RREG32(mmCGTS_SM_CTRL_REG); 3659 data &= ~CGTS_SM_CTRL_REG__SM_MODE_MASK; 3660 data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT); 3661 data |= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK; 3662 data &= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK; 3663 if ((adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) && 3664 (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS_LS)) 3665 data &= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK; 3666 data &= ~CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK; 3667 data |= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK; 3668 data |= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT); 3669 if (orig != data) 3670 WREG32(mmCGTS_SM_CTRL_REG, data); 3671 } 3672 } else { 3673 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); 3674 data |= 0x00000003; 3675 if (orig != data) 3676 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data); 3677 3678 data = RREG32(mmRLC_MEM_SLP_CNTL); 3679 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 3680 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 3681 WREG32(mmRLC_MEM_SLP_CNTL, data); 3682 } 3683 3684 data = RREG32(mmCP_MEM_SLP_CNTL); 3685 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 3686 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 3687 WREG32(mmCP_MEM_SLP_CNTL, data); 3688 } 3689 3690 orig = data = RREG32(mmCGTS_SM_CTRL_REG); 3691 data |= CGTS_SM_CTRL_REG__OVERRIDE_MASK | CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK; 3692 if (orig != data) 3693 WREG32(mmCGTS_SM_CTRL_REG, data); 3694 3695 tmp = gfx_v7_0_halt_rlc(adev); 3696 3697 mutex_lock(&adev->grbm_idx_mutex); 3698 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 3699 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); 3700 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); 3701 data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK | RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1_MASK; 3702 WREG32(mmRLC_SERDES_WR_CTRL, data); 3703 mutex_unlock(&adev->grbm_idx_mutex); 3704 3705 gfx_v7_0_update_rlc(adev, tmp); 3706 } 3707 } 3708 3709 static void gfx_v7_0_update_cg(struct amdgpu_device *adev, 3710 bool enable) 3711 { 3712 gfx_v7_0_enable_gui_idle_interrupt(adev, false); 3713 /* order matters! */ 3714 if (enable) { 3715 gfx_v7_0_enable_mgcg(adev, true); 3716 gfx_v7_0_enable_cgcg(adev, true); 3717 } else { 3718 gfx_v7_0_enable_cgcg(adev, false); 3719 gfx_v7_0_enable_mgcg(adev, false); 3720 } 3721 gfx_v7_0_enable_gui_idle_interrupt(adev, true); 3722 } 3723 3724 static void gfx_v7_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev, 3725 bool enable) 3726 { 3727 u32 data, orig; 3728 3729 orig = data = RREG32(mmRLC_PG_CNTL); 3730 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS)) 3731 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK; 3732 else 3733 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK; 3734 if (orig != data) 3735 WREG32(mmRLC_PG_CNTL, data); 3736 } 3737 3738 static void gfx_v7_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev, 3739 bool enable) 3740 { 3741 u32 data, orig; 3742 3743 orig = data = RREG32(mmRLC_PG_CNTL); 3744 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS)) 3745 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK; 3746 else 3747 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK; 3748 if (orig != data) 3749 WREG32(mmRLC_PG_CNTL, data); 3750 } 3751 3752 static void gfx_v7_0_enable_cp_pg(struct amdgpu_device *adev, bool enable) 3753 { 3754 u32 data, orig; 3755 3756 orig = data = RREG32(mmRLC_PG_CNTL); 3757 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP)) 3758 data &= ~0x8000; 3759 else 3760 data |= 0x8000; 3761 if (orig != data) 3762 WREG32(mmRLC_PG_CNTL, data); 3763 } 3764 3765 static void gfx_v7_0_enable_gds_pg(struct amdgpu_device *adev, bool enable) 3766 { 3767 u32 data, orig; 3768 3769 orig = data = RREG32(mmRLC_PG_CNTL); 3770 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GDS)) 3771 data &= ~0x2000; 3772 else 3773 data |= 0x2000; 3774 if (orig != data) 3775 WREG32(mmRLC_PG_CNTL, data); 3776 } 3777 3778 static int gfx_v7_0_cp_pg_table_num(struct amdgpu_device *adev) 3779 { 3780 if (adev->asic_type == CHIP_KAVERI) 3781 return 5; 3782 else 3783 return 4; 3784 } 3785 3786 static void gfx_v7_0_enable_gfx_cgpg(struct amdgpu_device *adev, 3787 bool enable) 3788 { 3789 u32 data, orig; 3790 3791 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { 3792 orig = data = RREG32(mmRLC_PG_CNTL); 3793 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 3794 if (orig != data) 3795 WREG32(mmRLC_PG_CNTL, data); 3796 3797 orig = data = RREG32(mmRLC_AUTO_PG_CTRL); 3798 data |= RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK; 3799 if (orig != data) 3800 WREG32(mmRLC_AUTO_PG_CTRL, data); 3801 } else { 3802 orig = data = RREG32(mmRLC_PG_CNTL); 3803 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 3804 if (orig != data) 3805 WREG32(mmRLC_PG_CNTL, data); 3806 3807 orig = data = RREG32(mmRLC_AUTO_PG_CTRL); 3808 data &= ~RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK; 3809 if (orig != data) 3810 WREG32(mmRLC_AUTO_PG_CTRL, data); 3811 3812 data = RREG32(mmDB_RENDER_CONTROL); 3813 } 3814 } 3815 3816 static void gfx_v7_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, 3817 u32 bitmap) 3818 { 3819 u32 data; 3820 3821 if (!bitmap) 3822 return; 3823 3824 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 3825 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 3826 3827 WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data); 3828 } 3829 3830 static u32 gfx_v7_0_get_cu_active_bitmap(struct amdgpu_device *adev) 3831 { 3832 u32 data, mask; 3833 3834 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG); 3835 data |= RREG32(mmGC_USER_SHADER_ARRAY_CONFIG); 3836 3837 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 3838 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 3839 3840 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); 3841 3842 return (~data) & mask; 3843 } 3844 3845 static void gfx_v7_0_init_ao_cu_mask(struct amdgpu_device *adev) 3846 { 3847 u32 tmp; 3848 3849 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask); 3850 3851 tmp = RREG32(mmRLC_MAX_PG_CU); 3852 tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK; 3853 tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT); 3854 WREG32(mmRLC_MAX_PG_CU, tmp); 3855 } 3856 3857 static void gfx_v7_0_enable_gfx_static_mgpg(struct amdgpu_device *adev, 3858 bool enable) 3859 { 3860 u32 data, orig; 3861 3862 orig = data = RREG32(mmRLC_PG_CNTL); 3863 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG)) 3864 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK; 3865 else 3866 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK; 3867 if (orig != data) 3868 WREG32(mmRLC_PG_CNTL, data); 3869 } 3870 3871 static void gfx_v7_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev, 3872 bool enable) 3873 { 3874 u32 data, orig; 3875 3876 orig = data = RREG32(mmRLC_PG_CNTL); 3877 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG)) 3878 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK; 3879 else 3880 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK; 3881 if (orig != data) 3882 WREG32(mmRLC_PG_CNTL, data); 3883 } 3884 3885 #define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90 3886 #define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET 0x3D 3887 3888 static void gfx_v7_0_init_gfx_cgpg(struct amdgpu_device *adev) 3889 { 3890 u32 data, orig; 3891 u32 i; 3892 3893 if (adev->gfx.rlc.cs_data) { 3894 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET); 3895 WREG32(mmRLC_GPM_SCRATCH_DATA, upper_32_bits(adev->gfx.rlc.clear_state_gpu_addr)); 3896 WREG32(mmRLC_GPM_SCRATCH_DATA, lower_32_bits(adev->gfx.rlc.clear_state_gpu_addr)); 3897 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.clear_state_size); 3898 } else { 3899 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET); 3900 for (i = 0; i < 3; i++) 3901 WREG32(mmRLC_GPM_SCRATCH_DATA, 0); 3902 } 3903 if (adev->gfx.rlc.reg_list) { 3904 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_SAVE_AND_RESTORE_STARTING_OFFSET); 3905 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++) 3906 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.reg_list[i]); 3907 } 3908 3909 orig = data = RREG32(mmRLC_PG_CNTL); 3910 data |= RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK; 3911 if (orig != data) 3912 WREG32(mmRLC_PG_CNTL, data); 3913 3914 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); 3915 WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8); 3916 3917 data = RREG32(mmCP_RB_WPTR_POLL_CNTL); 3918 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK; 3919 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 3920 WREG32(mmCP_RB_WPTR_POLL_CNTL, data); 3921 3922 data = 0x10101010; 3923 WREG32(mmRLC_PG_DELAY, data); 3924 3925 data = RREG32(mmRLC_PG_DELAY_2); 3926 data &= ~0xff; 3927 data |= 0x3; 3928 WREG32(mmRLC_PG_DELAY_2, data); 3929 3930 data = RREG32(mmRLC_AUTO_PG_CTRL); 3931 data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK; 3932 data |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT); 3933 WREG32(mmRLC_AUTO_PG_CTRL, data); 3934 3935 } 3936 3937 static void gfx_v7_0_update_gfx_pg(struct amdgpu_device *adev, bool enable) 3938 { 3939 gfx_v7_0_enable_gfx_cgpg(adev, enable); 3940 gfx_v7_0_enable_gfx_static_mgpg(adev, enable); 3941 gfx_v7_0_enable_gfx_dynamic_mgpg(adev, enable); 3942 } 3943 3944 static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev) 3945 { 3946 u32 count = 0; 3947 const struct cs_section_def *sect = NULL; 3948 const struct cs_extent_def *ext = NULL; 3949 3950 if (adev->gfx.rlc.cs_data == NULL) 3951 return 0; 3952 3953 /* begin clear state */ 3954 count += 2; 3955 /* context control state */ 3956 count += 3; 3957 3958 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 3959 for (ext = sect->section; ext->extent != NULL; ++ext) { 3960 if (sect->id == SECT_CONTEXT) 3961 count += 2 + ext->reg_count; 3962 else 3963 return 0; 3964 } 3965 } 3966 /* pa_sc_raster_config/pa_sc_raster_config1 */ 3967 count += 4; 3968 /* end clear state */ 3969 count += 2; 3970 /* clear state */ 3971 count += 2; 3972 3973 return count; 3974 } 3975 3976 static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, 3977 volatile u32 *buffer) 3978 { 3979 u32 count = 0, i; 3980 const struct cs_section_def *sect = NULL; 3981 const struct cs_extent_def *ext = NULL; 3982 3983 if (adev->gfx.rlc.cs_data == NULL) 3984 return; 3985 if (buffer == NULL) 3986 return; 3987 3988 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 3989 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 3990 3991 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 3992 buffer[count++] = cpu_to_le32(0x80000000); 3993 buffer[count++] = cpu_to_le32(0x80000000); 3994 3995 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 3996 for (ext = sect->section; ext->extent != NULL; ++ext) { 3997 if (sect->id == SECT_CONTEXT) { 3998 buffer[count++] = 3999 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 4000 buffer[count++] = cpu_to_le32(ext->reg_index - PACKET3_SET_CONTEXT_REG_START); 4001 for (i = 0; i < ext->reg_count; i++) 4002 buffer[count++] = cpu_to_le32(ext->extent[i]); 4003 } else { 4004 return; 4005 } 4006 } 4007 } 4008 4009 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2)); 4010 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); 4011 switch (adev->asic_type) { 4012 case CHIP_BONAIRE: 4013 buffer[count++] = cpu_to_le32(0x16000012); 4014 buffer[count++] = cpu_to_le32(0x00000000); 4015 break; 4016 case CHIP_KAVERI: 4017 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */ 4018 buffer[count++] = cpu_to_le32(0x00000000); 4019 break; 4020 case CHIP_KABINI: 4021 case CHIP_MULLINS: 4022 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */ 4023 buffer[count++] = cpu_to_le32(0x00000000); 4024 break; 4025 case CHIP_HAWAII: 4026 buffer[count++] = cpu_to_le32(0x3a00161a); 4027 buffer[count++] = cpu_to_le32(0x0000002e); 4028 break; 4029 default: 4030 buffer[count++] = cpu_to_le32(0x00000000); 4031 buffer[count++] = cpu_to_le32(0x00000000); 4032 break; 4033 } 4034 4035 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 4036 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 4037 4038 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 4039 buffer[count++] = cpu_to_le32(0); 4040 } 4041 4042 static void gfx_v7_0_init_pg(struct amdgpu_device *adev) 4043 { 4044 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 4045 AMD_PG_SUPPORT_GFX_SMG | 4046 AMD_PG_SUPPORT_GFX_DMG | 4047 AMD_PG_SUPPORT_CP | 4048 AMD_PG_SUPPORT_GDS | 4049 AMD_PG_SUPPORT_RLC_SMU_HS)) { 4050 gfx_v7_0_enable_sclk_slowdown_on_pu(adev, true); 4051 gfx_v7_0_enable_sclk_slowdown_on_pd(adev, true); 4052 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) { 4053 gfx_v7_0_init_gfx_cgpg(adev); 4054 gfx_v7_0_enable_cp_pg(adev, true); 4055 gfx_v7_0_enable_gds_pg(adev, true); 4056 } 4057 gfx_v7_0_init_ao_cu_mask(adev); 4058 gfx_v7_0_update_gfx_pg(adev, true); 4059 } 4060 } 4061 4062 static void gfx_v7_0_fini_pg(struct amdgpu_device *adev) 4063 { 4064 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 4065 AMD_PG_SUPPORT_GFX_SMG | 4066 AMD_PG_SUPPORT_GFX_DMG | 4067 AMD_PG_SUPPORT_CP | 4068 AMD_PG_SUPPORT_GDS | 4069 AMD_PG_SUPPORT_RLC_SMU_HS)) { 4070 gfx_v7_0_update_gfx_pg(adev, false); 4071 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) { 4072 gfx_v7_0_enable_cp_pg(adev, false); 4073 gfx_v7_0_enable_gds_pg(adev, false); 4074 } 4075 } 4076 } 4077 4078 /** 4079 * gfx_v7_0_get_gpu_clock_counter - return GPU clock counter snapshot 4080 * 4081 * @adev: amdgpu_device pointer 4082 * 4083 * Fetches a GPU clock counter snapshot (SI). 4084 * Returns the 64 bit clock counter snapshot. 4085 */ 4086 static uint64_t gfx_v7_0_get_gpu_clock_counter(struct amdgpu_device *adev) 4087 { 4088 uint64_t clock; 4089 4090 mutex_lock(&adev->gfx.gpu_clock_mutex); 4091 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 4092 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) | 4093 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 4094 mutex_unlock(&adev->gfx.gpu_clock_mutex); 4095 return clock; 4096 } 4097 4098 static void gfx_v7_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 4099 uint32_t vmid, 4100 uint32_t gds_base, uint32_t gds_size, 4101 uint32_t gws_base, uint32_t gws_size, 4102 uint32_t oa_base, uint32_t oa_size) 4103 { 4104 /* GDS Base */ 4105 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4106 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4107 WRITE_DATA_DST_SEL(0))); 4108 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base); 4109 amdgpu_ring_write(ring, 0); 4110 amdgpu_ring_write(ring, gds_base); 4111 4112 /* GDS Size */ 4113 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4114 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4115 WRITE_DATA_DST_SEL(0))); 4116 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size); 4117 amdgpu_ring_write(ring, 0); 4118 amdgpu_ring_write(ring, gds_size); 4119 4120 /* GWS */ 4121 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4122 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4123 WRITE_DATA_DST_SEL(0))); 4124 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws); 4125 amdgpu_ring_write(ring, 0); 4126 amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 4127 4128 /* OA */ 4129 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4130 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4131 WRITE_DATA_DST_SEL(0))); 4132 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa); 4133 amdgpu_ring_write(ring, 0); 4134 amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base)); 4135 } 4136 4137 static void gfx_v7_0_ring_soft_recovery(struct amdgpu_ring *ring, unsigned vmid) 4138 { 4139 struct amdgpu_device *adev = ring->adev; 4140 uint32_t value = 0; 4141 4142 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 4143 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 4144 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 4145 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 4146 WREG32(mmSQ_CMD, value); 4147 } 4148 4149 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) 4150 { 4151 WREG32(mmSQ_IND_INDEX, 4152 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4153 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 4154 (address << SQ_IND_INDEX__INDEX__SHIFT) | 4155 (SQ_IND_INDEX__FORCE_READ_MASK)); 4156 return RREG32(mmSQ_IND_DATA); 4157 } 4158 4159 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, 4160 uint32_t wave, uint32_t thread, 4161 uint32_t regno, uint32_t num, uint32_t *out) 4162 { 4163 WREG32(mmSQ_IND_INDEX, 4164 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4165 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 4166 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 4167 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | 4168 (SQ_IND_INDEX__FORCE_READ_MASK) | 4169 (SQ_IND_INDEX__AUTO_INCR_MASK)); 4170 while (num--) 4171 *(out++) = RREG32(mmSQ_IND_DATA); 4172 } 4173 4174 static void gfx_v7_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 4175 { 4176 /* type 0 wave data */ 4177 dst[(*no_fields)++] = 0; 4178 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); 4179 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); 4180 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); 4181 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); 4182 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); 4183 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); 4184 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); 4185 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1); 4186 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC); 4187 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC); 4188 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS); 4189 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS); 4190 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO); 4191 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI); 4192 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO); 4193 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI); 4194 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0); 4195 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); 4196 } 4197 4198 static void gfx_v7_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, 4199 uint32_t wave, uint32_t start, 4200 uint32_t size, uint32_t *dst) 4201 { 4202 wave_read_regs( 4203 adev, simd, wave, 0, 4204 start + SQIND_WAVE_SGPRS_OFFSET, size, dst); 4205 } 4206 4207 static void gfx_v7_0_select_me_pipe_q(struct amdgpu_device *adev, 4208 u32 me, u32 pipe, u32 q, u32 vm) 4209 { 4210 cik_srbm_select(adev, me, pipe, q, vm); 4211 } 4212 4213 static const struct amdgpu_gfx_funcs gfx_v7_0_gfx_funcs = { 4214 .get_gpu_clock_counter = &gfx_v7_0_get_gpu_clock_counter, 4215 .select_se_sh = &gfx_v7_0_select_se_sh, 4216 .read_wave_data = &gfx_v7_0_read_wave_data, 4217 .read_wave_sgprs = &gfx_v7_0_read_wave_sgprs, 4218 .select_me_pipe_q = &gfx_v7_0_select_me_pipe_q 4219 }; 4220 4221 static const struct amdgpu_rlc_funcs gfx_v7_0_rlc_funcs = { 4222 .is_rlc_enabled = gfx_v7_0_is_rlc_enabled, 4223 .set_safe_mode = gfx_v7_0_set_safe_mode, 4224 .unset_safe_mode = gfx_v7_0_unset_safe_mode, 4225 .init = gfx_v7_0_rlc_init, 4226 .get_csb_size = gfx_v7_0_get_csb_size, 4227 .get_csb_buffer = gfx_v7_0_get_csb_buffer, 4228 .get_cp_table_num = gfx_v7_0_cp_pg_table_num, 4229 .resume = gfx_v7_0_rlc_resume, 4230 .stop = gfx_v7_0_rlc_stop, 4231 .reset = gfx_v7_0_rlc_reset, 4232 .start = gfx_v7_0_rlc_start 4233 }; 4234 4235 static int gfx_v7_0_early_init(void *handle) 4236 { 4237 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4238 4239 adev->gfx.num_gfx_rings = GFX7_NUM_GFX_RINGS; 4240 adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS; 4241 adev->gfx.funcs = &gfx_v7_0_gfx_funcs; 4242 adev->gfx.rlc.funcs = &gfx_v7_0_rlc_funcs; 4243 gfx_v7_0_set_ring_funcs(adev); 4244 gfx_v7_0_set_irq_funcs(adev); 4245 gfx_v7_0_set_gds_init(adev); 4246 4247 return 0; 4248 } 4249 4250 static int gfx_v7_0_late_init(void *handle) 4251 { 4252 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4253 int r; 4254 4255 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 4256 if (r) 4257 return r; 4258 4259 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 4260 if (r) 4261 return r; 4262 4263 return 0; 4264 } 4265 4266 static void gfx_v7_0_gpu_early_init(struct amdgpu_device *adev) 4267 { 4268 u32 gb_addr_config; 4269 u32 mc_arb_ramcfg; 4270 u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map; 4271 u32 tmp; 4272 4273 switch (adev->asic_type) { 4274 case CHIP_BONAIRE: 4275 adev->gfx.config.max_shader_engines = 2; 4276 adev->gfx.config.max_tile_pipes = 4; 4277 adev->gfx.config.max_cu_per_sh = 7; 4278 adev->gfx.config.max_sh_per_se = 1; 4279 adev->gfx.config.max_backends_per_se = 2; 4280 adev->gfx.config.max_texture_channel_caches = 4; 4281 adev->gfx.config.max_gprs = 256; 4282 adev->gfx.config.max_gs_threads = 32; 4283 adev->gfx.config.max_hw_contexts = 8; 4284 4285 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4286 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4287 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 4288 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 4289 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN; 4290 break; 4291 case CHIP_HAWAII: 4292 adev->gfx.config.max_shader_engines = 4; 4293 adev->gfx.config.max_tile_pipes = 16; 4294 adev->gfx.config.max_cu_per_sh = 11; 4295 adev->gfx.config.max_sh_per_se = 1; 4296 adev->gfx.config.max_backends_per_se = 4; 4297 adev->gfx.config.max_texture_channel_caches = 16; 4298 adev->gfx.config.max_gprs = 256; 4299 adev->gfx.config.max_gs_threads = 32; 4300 adev->gfx.config.max_hw_contexts = 8; 4301 4302 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4303 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4304 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 4305 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 4306 gb_addr_config = HAWAII_GB_ADDR_CONFIG_GOLDEN; 4307 break; 4308 case CHIP_KAVERI: 4309 adev->gfx.config.max_shader_engines = 1; 4310 adev->gfx.config.max_tile_pipes = 4; 4311 adev->gfx.config.max_cu_per_sh = 8; 4312 adev->gfx.config.max_backends_per_se = 2; 4313 adev->gfx.config.max_sh_per_se = 1; 4314 adev->gfx.config.max_texture_channel_caches = 4; 4315 adev->gfx.config.max_gprs = 256; 4316 adev->gfx.config.max_gs_threads = 16; 4317 adev->gfx.config.max_hw_contexts = 8; 4318 4319 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4320 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4321 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 4322 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 4323 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN; 4324 break; 4325 case CHIP_KABINI: 4326 case CHIP_MULLINS: 4327 default: 4328 adev->gfx.config.max_shader_engines = 1; 4329 adev->gfx.config.max_tile_pipes = 2; 4330 adev->gfx.config.max_cu_per_sh = 2; 4331 adev->gfx.config.max_sh_per_se = 1; 4332 adev->gfx.config.max_backends_per_se = 1; 4333 adev->gfx.config.max_texture_channel_caches = 2; 4334 adev->gfx.config.max_gprs = 256; 4335 adev->gfx.config.max_gs_threads = 16; 4336 adev->gfx.config.max_hw_contexts = 8; 4337 4338 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4339 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4340 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 4341 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 4342 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN; 4343 break; 4344 } 4345 4346 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG); 4347 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg; 4348 4349 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; 4350 adev->gfx.config.mem_max_burst_length_bytes = 256; 4351 if (adev->flags & AMD_IS_APU) { 4352 /* Get memory bank mapping mode. */ 4353 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING); 4354 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP); 4355 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP); 4356 4357 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING); 4358 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP); 4359 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP); 4360 4361 /* Validate settings in case only one DIMM installed. */ 4362 if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12)) 4363 dimm00_addr_map = 0; 4364 if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12)) 4365 dimm01_addr_map = 0; 4366 if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12)) 4367 dimm10_addr_map = 0; 4368 if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12)) 4369 dimm11_addr_map = 0; 4370 4371 /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */ 4372 /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */ 4373 if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11)) 4374 adev->gfx.config.mem_row_size_in_kb = 2; 4375 else 4376 adev->gfx.config.mem_row_size_in_kb = 1; 4377 } else { 4378 tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT; 4379 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; 4380 if (adev->gfx.config.mem_row_size_in_kb > 4) 4381 adev->gfx.config.mem_row_size_in_kb = 4; 4382 } 4383 /* XXX use MC settings? */ 4384 adev->gfx.config.shader_engine_tile_size = 32; 4385 adev->gfx.config.num_gpus = 1; 4386 adev->gfx.config.multi_gpu_tile_size = 64; 4387 4388 /* fix up row size */ 4389 gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK; 4390 switch (adev->gfx.config.mem_row_size_in_kb) { 4391 case 1: 4392 default: 4393 gb_addr_config |= (0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT); 4394 break; 4395 case 2: 4396 gb_addr_config |= (1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT); 4397 break; 4398 case 4: 4399 gb_addr_config |= (2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT); 4400 break; 4401 } 4402 adev->gfx.config.gb_addr_config = gb_addr_config; 4403 } 4404 4405 static int gfx_v7_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 4406 int mec, int pipe, int queue) 4407 { 4408 int r; 4409 unsigned irq_type; 4410 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; 4411 4412 /* mec0 is me1 */ 4413 ring->me = mec + 1; 4414 ring->pipe = pipe; 4415 ring->queue = queue; 4416 4417 ring->ring_obj = NULL; 4418 ring->use_doorbell = true; 4419 ring->doorbell_index = adev->doorbell_index.mec_ring0 + ring_id; 4420 snprintf(ring->name, sizeof ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 4421 4422 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 4423 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 4424 + ring->pipe; 4425 4426 /* type-2 packets are deprecated on MEC, use type-3 instead */ 4427 r = amdgpu_ring_init(adev, ring, 1024, 4428 &adev->gfx.eop_irq, irq_type); 4429 if (r) 4430 return r; 4431 4432 4433 return 0; 4434 } 4435 4436 static int gfx_v7_0_sw_init(void *handle) 4437 { 4438 struct amdgpu_ring *ring; 4439 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4440 int i, j, k, r, ring_id; 4441 4442 switch (adev->asic_type) { 4443 case CHIP_KAVERI: 4444 adev->gfx.mec.num_mec = 2; 4445 break; 4446 case CHIP_BONAIRE: 4447 case CHIP_HAWAII: 4448 case CHIP_KABINI: 4449 case CHIP_MULLINS: 4450 default: 4451 adev->gfx.mec.num_mec = 1; 4452 break; 4453 } 4454 adev->gfx.mec.num_pipe_per_mec = 4; 4455 adev->gfx.mec.num_queue_per_pipe = 8; 4456 4457 /* EOP Event */ 4458 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq); 4459 if (r) 4460 return r; 4461 4462 /* Privileged reg */ 4463 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 184, 4464 &adev->gfx.priv_reg_irq); 4465 if (r) 4466 return r; 4467 4468 /* Privileged inst */ 4469 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 185, 4470 &adev->gfx.priv_inst_irq); 4471 if (r) 4472 return r; 4473 4474 gfx_v7_0_scratch_init(adev); 4475 4476 r = gfx_v7_0_init_microcode(adev); 4477 if (r) { 4478 DRM_ERROR("Failed to load gfx firmware!\n"); 4479 return r; 4480 } 4481 4482 r = adev->gfx.rlc.funcs->init(adev); 4483 if (r) { 4484 DRM_ERROR("Failed to init rlc BOs!\n"); 4485 return r; 4486 } 4487 4488 /* allocate mec buffers */ 4489 r = gfx_v7_0_mec_init(adev); 4490 if (r) { 4491 DRM_ERROR("Failed to init MEC BOs!\n"); 4492 return r; 4493 } 4494 4495 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 4496 ring = &adev->gfx.gfx_ring[i]; 4497 ring->ring_obj = NULL; 4498 snprintf(ring->name, sizeof ring->name, "gfx"); 4499 r = amdgpu_ring_init(adev, ring, 1024, 4500 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP); 4501 if (r) 4502 return r; 4503 } 4504 4505 /* set up the compute queues - allocate horizontally across pipes */ 4506 ring_id = 0; 4507 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 4508 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 4509 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 4510 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j)) 4511 continue; 4512 4513 r = gfx_v7_0_compute_ring_init(adev, 4514 ring_id, 4515 i, k, j); 4516 if (r) 4517 return r; 4518 4519 ring_id++; 4520 } 4521 } 4522 } 4523 4524 adev->gfx.ce_ram_size = 0x8000; 4525 4526 gfx_v7_0_gpu_early_init(adev); 4527 4528 return r; 4529 } 4530 4531 static int gfx_v7_0_sw_fini(void *handle) 4532 { 4533 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4534 int i; 4535 4536 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 4537 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 4538 for (i = 0; i < adev->gfx.num_compute_rings; i++) 4539 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 4540 4541 gfx_v7_0_cp_compute_fini(adev); 4542 amdgpu_gfx_rlc_fini(adev); 4543 gfx_v7_0_mec_fini(adev); 4544 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 4545 &adev->gfx.rlc.clear_state_gpu_addr, 4546 (void **)__UNVOLATILE(&adev->gfx.rlc.cs_ptr)); 4547 if (adev->gfx.rlc.cp_table_size) { 4548 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 4549 &adev->gfx.rlc.cp_table_gpu_addr, 4550 (void **)__UNVOLATILE(&adev->gfx.rlc.cp_table_ptr)); 4551 } 4552 gfx_v7_0_free_microcode(adev); 4553 4554 return 0; 4555 } 4556 4557 static int gfx_v7_0_hw_init(void *handle) 4558 { 4559 int r; 4560 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4561 4562 gfx_v7_0_constants_init(adev); 4563 4564 /* init CSB */ 4565 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 4566 /* init rlc */ 4567 r = adev->gfx.rlc.funcs->resume(adev); 4568 if (r) 4569 return r; 4570 4571 r = gfx_v7_0_cp_resume(adev); 4572 if (r) 4573 return r; 4574 4575 return r; 4576 } 4577 4578 static int gfx_v7_0_hw_fini(void *handle) 4579 { 4580 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4581 4582 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 4583 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 4584 gfx_v7_0_cp_enable(adev, false); 4585 adev->gfx.rlc.funcs->stop(adev); 4586 gfx_v7_0_fini_pg(adev); 4587 4588 return 0; 4589 } 4590 4591 static int gfx_v7_0_suspend(void *handle) 4592 { 4593 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4594 4595 return gfx_v7_0_hw_fini(adev); 4596 } 4597 4598 static int gfx_v7_0_resume(void *handle) 4599 { 4600 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4601 4602 return gfx_v7_0_hw_init(adev); 4603 } 4604 4605 static bool gfx_v7_0_is_idle(void *handle) 4606 { 4607 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4608 4609 if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK) 4610 return false; 4611 else 4612 return true; 4613 } 4614 4615 static int gfx_v7_0_wait_for_idle(void *handle) 4616 { 4617 unsigned i; 4618 u32 tmp; 4619 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4620 4621 for (i = 0; i < adev->usec_timeout; i++) { 4622 /* read MC_STATUS */ 4623 tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK; 4624 4625 if (!tmp) 4626 return 0; 4627 udelay(1); 4628 } 4629 return -ETIMEDOUT; 4630 } 4631 4632 static int gfx_v7_0_soft_reset(void *handle) 4633 { 4634 u32 grbm_soft_reset = 0, srbm_soft_reset = 0; 4635 u32 tmp; 4636 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4637 4638 /* GRBM_STATUS */ 4639 tmp = RREG32(mmGRBM_STATUS); 4640 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 4641 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 4642 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK | 4643 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK | 4644 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK | 4645 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) 4646 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK | 4647 GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK; 4648 4649 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 4650 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK; 4651 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK; 4652 } 4653 4654 /* GRBM_STATUS2 */ 4655 tmp = RREG32(mmGRBM_STATUS2); 4656 if (tmp & GRBM_STATUS2__RLC_BUSY_MASK) 4657 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK; 4658 4659 /* SRBM_STATUS */ 4660 tmp = RREG32(mmSRBM_STATUS); 4661 if (tmp & SRBM_STATUS__GRBM_RQ_PENDING_MASK) 4662 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK; 4663 4664 if (grbm_soft_reset || srbm_soft_reset) { 4665 /* disable CG/PG */ 4666 gfx_v7_0_fini_pg(adev); 4667 gfx_v7_0_update_cg(adev, false); 4668 4669 /* stop the rlc */ 4670 adev->gfx.rlc.funcs->stop(adev); 4671 4672 /* Disable GFX parsing/prefetching */ 4673 WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK); 4674 4675 /* Disable MEC parsing/prefetching */ 4676 WREG32(mmCP_MEC_CNTL, CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK); 4677 4678 if (grbm_soft_reset) { 4679 tmp = RREG32(mmGRBM_SOFT_RESET); 4680 tmp |= grbm_soft_reset; 4681 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 4682 WREG32(mmGRBM_SOFT_RESET, tmp); 4683 tmp = RREG32(mmGRBM_SOFT_RESET); 4684 4685 udelay(50); 4686 4687 tmp &= ~grbm_soft_reset; 4688 WREG32(mmGRBM_SOFT_RESET, tmp); 4689 tmp = RREG32(mmGRBM_SOFT_RESET); 4690 } 4691 4692 if (srbm_soft_reset) { 4693 tmp = RREG32(mmSRBM_SOFT_RESET); 4694 tmp |= srbm_soft_reset; 4695 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 4696 WREG32(mmSRBM_SOFT_RESET, tmp); 4697 tmp = RREG32(mmSRBM_SOFT_RESET); 4698 4699 udelay(50); 4700 4701 tmp &= ~srbm_soft_reset; 4702 WREG32(mmSRBM_SOFT_RESET, tmp); 4703 tmp = RREG32(mmSRBM_SOFT_RESET); 4704 } 4705 /* Wait a little for things to settle down */ 4706 udelay(50); 4707 } 4708 return 0; 4709 } 4710 4711 static void gfx_v7_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 4712 enum amdgpu_interrupt_state state) 4713 { 4714 u32 cp_int_cntl; 4715 4716 switch (state) { 4717 case AMDGPU_IRQ_STATE_DISABLE: 4718 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 4719 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 4720 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 4721 break; 4722 case AMDGPU_IRQ_STATE_ENABLE: 4723 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 4724 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 4725 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 4726 break; 4727 default: 4728 break; 4729 } 4730 } 4731 4732 static void gfx_v7_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 4733 int me, int pipe, 4734 enum amdgpu_interrupt_state state) 4735 { 4736 u32 mec_int_cntl, mec_int_cntl_reg; 4737 4738 /* 4739 * amdgpu controls only the first MEC. That's why this function only 4740 * handles the setting of interrupts for this specific MEC. All other 4741 * pipes' interrupts are set by amdkfd. 4742 */ 4743 4744 if (me == 1) { 4745 switch (pipe) { 4746 case 0: 4747 mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL; 4748 break; 4749 case 1: 4750 mec_int_cntl_reg = mmCP_ME1_PIPE1_INT_CNTL; 4751 break; 4752 case 2: 4753 mec_int_cntl_reg = mmCP_ME1_PIPE2_INT_CNTL; 4754 break; 4755 case 3: 4756 mec_int_cntl_reg = mmCP_ME1_PIPE3_INT_CNTL; 4757 break; 4758 default: 4759 DRM_DEBUG("invalid pipe %d\n", pipe); 4760 return; 4761 } 4762 } else { 4763 DRM_DEBUG("invalid me %d\n", me); 4764 return; 4765 } 4766 4767 switch (state) { 4768 case AMDGPU_IRQ_STATE_DISABLE: 4769 mec_int_cntl = RREG32(mec_int_cntl_reg); 4770 mec_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 4771 WREG32(mec_int_cntl_reg, mec_int_cntl); 4772 break; 4773 case AMDGPU_IRQ_STATE_ENABLE: 4774 mec_int_cntl = RREG32(mec_int_cntl_reg); 4775 mec_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 4776 WREG32(mec_int_cntl_reg, mec_int_cntl); 4777 break; 4778 default: 4779 break; 4780 } 4781 } 4782 4783 static int gfx_v7_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 4784 struct amdgpu_irq_src *src, 4785 unsigned type, 4786 enum amdgpu_interrupt_state state) 4787 { 4788 u32 cp_int_cntl; 4789 4790 switch (state) { 4791 case AMDGPU_IRQ_STATE_DISABLE: 4792 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 4793 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK; 4794 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 4795 break; 4796 case AMDGPU_IRQ_STATE_ENABLE: 4797 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 4798 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK; 4799 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 4800 break; 4801 default: 4802 break; 4803 } 4804 4805 return 0; 4806 } 4807 4808 static int gfx_v7_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 4809 struct amdgpu_irq_src *src, 4810 unsigned type, 4811 enum amdgpu_interrupt_state state) 4812 { 4813 u32 cp_int_cntl; 4814 4815 switch (state) { 4816 case AMDGPU_IRQ_STATE_DISABLE: 4817 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 4818 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; 4819 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 4820 break; 4821 case AMDGPU_IRQ_STATE_ENABLE: 4822 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 4823 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; 4824 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 4825 break; 4826 default: 4827 break; 4828 } 4829 4830 return 0; 4831 } 4832 4833 static int gfx_v7_0_set_eop_interrupt_state(struct amdgpu_device *adev, 4834 struct amdgpu_irq_src *src, 4835 unsigned type, 4836 enum amdgpu_interrupt_state state) 4837 { 4838 switch (type) { 4839 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 4840 gfx_v7_0_set_gfx_eop_interrupt_state(adev, state); 4841 break; 4842 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 4843 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 4844 break; 4845 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 4846 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 4847 break; 4848 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 4849 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 4850 break; 4851 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 4852 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 4853 break; 4854 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 4855 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 0, state); 4856 break; 4857 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 4858 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 1, state); 4859 break; 4860 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 4861 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 2, state); 4862 break; 4863 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 4864 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 3, state); 4865 break; 4866 default: 4867 break; 4868 } 4869 return 0; 4870 } 4871 4872 static int gfx_v7_0_eop_irq(struct amdgpu_device *adev, 4873 struct amdgpu_irq_src *source, 4874 struct amdgpu_iv_entry *entry) 4875 { 4876 u8 me_id, pipe_id; 4877 struct amdgpu_ring *ring; 4878 int i; 4879 4880 DRM_DEBUG("IH: CP EOP\n"); 4881 me_id = (entry->ring_id & 0x0c) >> 2; 4882 pipe_id = (entry->ring_id & 0x03) >> 0; 4883 switch (me_id) { 4884 case 0: 4885 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 4886 break; 4887 case 1: 4888 case 2: 4889 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4890 ring = &adev->gfx.compute_ring[i]; 4891 if ((ring->me == me_id) && (ring->pipe == pipe_id)) 4892 amdgpu_fence_process(ring); 4893 } 4894 break; 4895 } 4896 return 0; 4897 } 4898 4899 static void gfx_v7_0_fault(struct amdgpu_device *adev, 4900 struct amdgpu_iv_entry *entry) 4901 { 4902 struct amdgpu_ring *ring; 4903 u8 me_id, pipe_id; 4904 int i; 4905 4906 me_id = (entry->ring_id & 0x0c) >> 2; 4907 pipe_id = (entry->ring_id & 0x03) >> 0; 4908 switch (me_id) { 4909 case 0: 4910 drm_sched_fault(&adev->gfx.gfx_ring[0].sched); 4911 break; 4912 case 1: 4913 case 2: 4914 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4915 ring = &adev->gfx.compute_ring[i]; 4916 if ((ring->me == me_id) && (ring->pipe == pipe_id)) 4917 drm_sched_fault(&ring->sched); 4918 } 4919 break; 4920 } 4921 } 4922 4923 static int gfx_v7_0_priv_reg_irq(struct amdgpu_device *adev, 4924 struct amdgpu_irq_src *source, 4925 struct amdgpu_iv_entry *entry) 4926 { 4927 DRM_ERROR("Illegal register access in command stream\n"); 4928 gfx_v7_0_fault(adev, entry); 4929 return 0; 4930 } 4931 4932 static int gfx_v7_0_priv_inst_irq(struct amdgpu_device *adev, 4933 struct amdgpu_irq_src *source, 4934 struct amdgpu_iv_entry *entry) 4935 { 4936 DRM_ERROR("Illegal instruction in command stream\n"); 4937 // XXX soft reset the gfx block only 4938 gfx_v7_0_fault(adev, entry); 4939 return 0; 4940 } 4941 4942 static int gfx_v7_0_set_clockgating_state(void *handle, 4943 enum amd_clockgating_state state) 4944 { 4945 bool gate = false; 4946 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4947 4948 if (state == AMD_CG_STATE_GATE) 4949 gate = true; 4950 4951 gfx_v7_0_enable_gui_idle_interrupt(adev, false); 4952 /* order matters! */ 4953 if (gate) { 4954 gfx_v7_0_enable_mgcg(adev, true); 4955 gfx_v7_0_enable_cgcg(adev, true); 4956 } else { 4957 gfx_v7_0_enable_cgcg(adev, false); 4958 gfx_v7_0_enable_mgcg(adev, false); 4959 } 4960 gfx_v7_0_enable_gui_idle_interrupt(adev, true); 4961 4962 return 0; 4963 } 4964 4965 static int gfx_v7_0_set_powergating_state(void *handle, 4966 enum amd_powergating_state state) 4967 { 4968 bool gate = false; 4969 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4970 4971 if (state == AMD_PG_STATE_GATE) 4972 gate = true; 4973 4974 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 4975 AMD_PG_SUPPORT_GFX_SMG | 4976 AMD_PG_SUPPORT_GFX_DMG | 4977 AMD_PG_SUPPORT_CP | 4978 AMD_PG_SUPPORT_GDS | 4979 AMD_PG_SUPPORT_RLC_SMU_HS)) { 4980 gfx_v7_0_update_gfx_pg(adev, gate); 4981 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) { 4982 gfx_v7_0_enable_cp_pg(adev, gate); 4983 gfx_v7_0_enable_gds_pg(adev, gate); 4984 } 4985 } 4986 4987 return 0; 4988 } 4989 4990 static const struct amd_ip_funcs gfx_v7_0_ip_funcs = { 4991 .name = "gfx_v7_0", 4992 .early_init = gfx_v7_0_early_init, 4993 .late_init = gfx_v7_0_late_init, 4994 .sw_init = gfx_v7_0_sw_init, 4995 .sw_fini = gfx_v7_0_sw_fini, 4996 .hw_init = gfx_v7_0_hw_init, 4997 .hw_fini = gfx_v7_0_hw_fini, 4998 .suspend = gfx_v7_0_suspend, 4999 .resume = gfx_v7_0_resume, 5000 .is_idle = gfx_v7_0_is_idle, 5001 .wait_for_idle = gfx_v7_0_wait_for_idle, 5002 .soft_reset = gfx_v7_0_soft_reset, 5003 .set_clockgating_state = gfx_v7_0_set_clockgating_state, 5004 .set_powergating_state = gfx_v7_0_set_powergating_state, 5005 }; 5006 5007 static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = { 5008 .type = AMDGPU_RING_TYPE_GFX, 5009 .align_mask = 0xff, 5010 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5011 .support_64bit_ptrs = false, 5012 .get_rptr = gfx_v7_0_ring_get_rptr, 5013 .get_wptr = gfx_v7_0_ring_get_wptr_gfx, 5014 .set_wptr = gfx_v7_0_ring_set_wptr_gfx, 5015 .emit_frame_size = 5016 20 + /* gfx_v7_0_ring_emit_gds_switch */ 5017 7 + /* gfx_v7_0_ring_emit_hdp_flush */ 5018 5 + /* hdp invalidate */ 5019 12 + 12 + 12 + /* gfx_v7_0_ring_emit_fence_gfx x3 for user fence, vm fence */ 5020 7 + 4 + /* gfx_v7_0_ring_emit_pipeline_sync */ 5021 CIK_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + 6 + /* gfx_v7_0_ring_emit_vm_flush */ 5022 3 + 4, /* gfx_v7_ring_emit_cntxcntl including vgt flush*/ 5023 .emit_ib_size = 4, /* gfx_v7_0_ring_emit_ib_gfx */ 5024 .emit_ib = gfx_v7_0_ring_emit_ib_gfx, 5025 .emit_fence = gfx_v7_0_ring_emit_fence_gfx, 5026 .emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync, 5027 .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush, 5028 .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch, 5029 .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush, 5030 .test_ring = gfx_v7_0_ring_test_ring, 5031 .test_ib = gfx_v7_0_ring_test_ib, 5032 .insert_nop = amdgpu_ring_insert_nop, 5033 .pad_ib = amdgpu_ring_generic_pad_ib, 5034 .emit_cntxcntl = gfx_v7_ring_emit_cntxcntl, 5035 .emit_wreg = gfx_v7_0_ring_emit_wreg, 5036 .soft_recovery = gfx_v7_0_ring_soft_recovery, 5037 }; 5038 5039 static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = { 5040 .type = AMDGPU_RING_TYPE_COMPUTE, 5041 .align_mask = 0xff, 5042 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5043 .support_64bit_ptrs = false, 5044 .get_rptr = gfx_v7_0_ring_get_rptr, 5045 .get_wptr = gfx_v7_0_ring_get_wptr_compute, 5046 .set_wptr = gfx_v7_0_ring_set_wptr_compute, 5047 .emit_frame_size = 5048 20 + /* gfx_v7_0_ring_emit_gds_switch */ 5049 7 + /* gfx_v7_0_ring_emit_hdp_flush */ 5050 5 + /* hdp invalidate */ 5051 7 + /* gfx_v7_0_ring_emit_pipeline_sync */ 5052 CIK_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* gfx_v7_0_ring_emit_vm_flush */ 5053 7 + 7 + 7, /* gfx_v7_0_ring_emit_fence_compute x3 for user fence, vm fence */ 5054 .emit_ib_size = 7, /* gfx_v7_0_ring_emit_ib_compute */ 5055 .emit_ib = gfx_v7_0_ring_emit_ib_compute, 5056 .emit_fence = gfx_v7_0_ring_emit_fence_compute, 5057 .emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync, 5058 .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush, 5059 .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch, 5060 .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush, 5061 .test_ring = gfx_v7_0_ring_test_ring, 5062 .test_ib = gfx_v7_0_ring_test_ib, 5063 .insert_nop = amdgpu_ring_insert_nop, 5064 .pad_ib = amdgpu_ring_generic_pad_ib, 5065 .emit_wreg = gfx_v7_0_ring_emit_wreg, 5066 }; 5067 5068 static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev) 5069 { 5070 int i; 5071 5072 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 5073 adev->gfx.gfx_ring[i].funcs = &gfx_v7_0_ring_funcs_gfx; 5074 for (i = 0; i < adev->gfx.num_compute_rings; i++) 5075 adev->gfx.compute_ring[i].funcs = &gfx_v7_0_ring_funcs_compute; 5076 } 5077 5078 static const struct amdgpu_irq_src_funcs gfx_v7_0_eop_irq_funcs = { 5079 .set = gfx_v7_0_set_eop_interrupt_state, 5080 .process = gfx_v7_0_eop_irq, 5081 }; 5082 5083 static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_reg_irq_funcs = { 5084 .set = gfx_v7_0_set_priv_reg_fault_state, 5085 .process = gfx_v7_0_priv_reg_irq, 5086 }; 5087 5088 static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_inst_irq_funcs = { 5089 .set = gfx_v7_0_set_priv_inst_fault_state, 5090 .process = gfx_v7_0_priv_inst_irq, 5091 }; 5092 5093 static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev) 5094 { 5095 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 5096 adev->gfx.eop_irq.funcs = &gfx_v7_0_eop_irq_funcs; 5097 5098 adev->gfx.priv_reg_irq.num_types = 1; 5099 adev->gfx.priv_reg_irq.funcs = &gfx_v7_0_priv_reg_irq_funcs; 5100 5101 adev->gfx.priv_inst_irq.num_types = 1; 5102 adev->gfx.priv_inst_irq.funcs = &gfx_v7_0_priv_inst_irq_funcs; 5103 } 5104 5105 static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev) 5106 { 5107 /* init asci gds info */ 5108 adev->gds.gds_size = RREG32(mmGDS_VMID0_SIZE); 5109 adev->gds.gws_size = 64; 5110 adev->gds.oa_size = 16; 5111 adev->gds.gds_compute_max_wave_id = RREG32(mmGDS_COMPUTE_MAX_WAVE_ID); 5112 } 5113 5114 5115 static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev) 5116 { 5117 int i, j, k, counter, active_cu_number = 0; 5118 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 5119 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; 5120 unsigned disable_masks[4 * 2]; 5121 u32 ao_cu_num; 5122 5123 if (adev->flags & AMD_IS_APU) 5124 ao_cu_num = 2; 5125 else 5126 ao_cu_num = adev->gfx.config.max_cu_per_sh; 5127 5128 memset(cu_info, 0, sizeof(*cu_info)); 5129 5130 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2); 5131 5132 mutex_lock(&adev->grbm_idx_mutex); 5133 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 5134 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 5135 mask = 1; 5136 ao_bitmap = 0; 5137 counter = 0; 5138 gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff); 5139 if (i < 4 && j < 2) 5140 gfx_v7_0_set_user_cu_inactive_bitmap( 5141 adev, disable_masks[i * 2 + j]); 5142 bitmap = gfx_v7_0_get_cu_active_bitmap(adev); 5143 cu_info->bitmap[i][j] = bitmap; 5144 5145 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { 5146 if (bitmap & mask) { 5147 if (counter < ao_cu_num) 5148 ao_bitmap |= mask; 5149 counter ++; 5150 } 5151 mask <<= 1; 5152 } 5153 active_cu_number += counter; 5154 if (i < 2 && j < 2) 5155 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 5156 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 5157 } 5158 } 5159 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 5160 mutex_unlock(&adev->grbm_idx_mutex); 5161 5162 cu_info->number = active_cu_number; 5163 cu_info->ao_cu_mask = ao_cu_mask; 5164 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 5165 cu_info->max_waves_per_simd = 10; 5166 cu_info->max_scratch_slots_per_cu = 32; 5167 cu_info->wave_front_size = 64; 5168 cu_info->lds_size = 64; 5169 } 5170 5171 const struct amdgpu_ip_block_version gfx_v7_0_ip_block = 5172 { 5173 .type = AMD_IP_BLOCK_TYPE_GFX, 5174 .major = 7, 5175 .minor = 0, 5176 .rev = 0, 5177 .funcs = &gfx_v7_0_ip_funcs, 5178 }; 5179 5180 const struct amdgpu_ip_block_version gfx_v7_1_ip_block = 5181 { 5182 .type = AMD_IP_BLOCK_TYPE_GFX, 5183 .major = 7, 5184 .minor = 1, 5185 .rev = 0, 5186 .funcs = &gfx_v7_0_ip_funcs, 5187 }; 5188 5189 const struct amdgpu_ip_block_version gfx_v7_2_ip_block = 5190 { 5191 .type = AMD_IP_BLOCK_TYPE_GFX, 5192 .major = 7, 5193 .minor = 2, 5194 .rev = 0, 5195 .funcs = &gfx_v7_0_ip_funcs, 5196 }; 5197 5198 const struct amdgpu_ip_block_version gfx_v7_3_ip_block = 5199 { 5200 .type = AMD_IP_BLOCK_TYPE_GFX, 5201 .major = 7, 5202 .minor = 3, 5203 .rev = 0, 5204 .funcs = &gfx_v7_0_ip_funcs, 5205 }; 5206
Indexes created Sat Sep 20 22:09:52 GMT 2025