1 /* $NetBSD: amdgpu_amdkfd_gfx_v8.c,v 1.4 2021/12/18 23:44:58 riastradh Exp $ */ 2 3 /* 4 * Copyright 2014 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <sys/cdefs.h> 26 __KERNEL_RCSID(0, "$NetBSD: amdgpu_amdkfd_gfx_v8.c,v 1.4 2021/12/18 23:44:58 riastradh Exp $"); 27 28 #include <linux/mmu_context.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_amdkfd.h" 32 #include "gfx_v8_0.h" 33 #include "gca/gfx_8_0_sh_mask.h" 34 #include "gca/gfx_8_0_d.h" 35 #include "gca/gfx_8_0_enum.h" 36 #include "oss/oss_3_0_sh_mask.h" 37 #include "oss/oss_3_0_d.h" 38 #include "gmc/gmc_8_1_sh_mask.h" 39 #include "gmc/gmc_8_1_d.h" 40 #include "vi_structs.h" 41 #include "vid.h" 42 43 enum hqd_dequeue_request_type { 44 NO_ACTION = 0, 45 DRAIN_PIPE, 46 RESET_WAVES 47 }; 48 49 /* Because of REG_GET_FIELD() being used, we put this function in the 50 * asic specific file. 51 */ 52 static int get_tile_config(struct kgd_dev *kgd, 53 struct tile_config *config) 54 { 55 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 56 57 config->gb_addr_config = adev->gfx.config.gb_addr_config; 58 config->num_banks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg, 59 MC_ARB_RAMCFG, NOOFBANK); 60 config->num_ranks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg, 61 MC_ARB_RAMCFG, NOOFRANKS); 62 63 config->tile_config_ptr = adev->gfx.config.tile_mode_array; 64 config->num_tile_configs = 65 ARRAY_SIZE(adev->gfx.config.tile_mode_array); 66 config->macro_tile_config_ptr = 67 adev->gfx.config.macrotile_mode_array; 68 config->num_macro_tile_configs = 69 ARRAY_SIZE(adev->gfx.config.macrotile_mode_array); 70 71 return 0; 72 } 73 74 static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd) 75 { 76 return (struct amdgpu_device *)kgd; 77 } 78 79 static void lock_srbm(struct kgd_dev *kgd, uint32_t mec, uint32_t pipe, 80 uint32_t queue, uint32_t vmid) 81 { 82 struct amdgpu_device *adev = get_amdgpu_device(kgd); 83 uint32_t value = PIPEID(pipe) | MEID(mec) | VMID(vmid) | QUEUEID(queue); 84 85 mutex_lock(&adev->srbm_mutex); 86 WREG32(mmSRBM_GFX_CNTL, value); 87 } 88 89 static void unlock_srbm(struct kgd_dev *kgd) 90 { 91 struct amdgpu_device *adev = get_amdgpu_device(kgd); 92 93 WREG32(mmSRBM_GFX_CNTL, 0); 94 mutex_unlock(&adev->srbm_mutex); 95 } 96 97 static void acquire_queue(struct kgd_dev *kgd, uint32_t pipe_id, 98 uint32_t queue_id) 99 { 100 struct amdgpu_device *adev = get_amdgpu_device(kgd); 101 102 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; 103 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); 104 105 lock_srbm(kgd, mec, pipe, queue_id, 0); 106 } 107 108 static void release_queue(struct kgd_dev *kgd) 109 { 110 unlock_srbm(kgd); 111 } 112 113 static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid, 114 uint32_t sh_mem_config, 115 uint32_t sh_mem_ape1_base, 116 uint32_t sh_mem_ape1_limit, 117 uint32_t sh_mem_bases) 118 { 119 struct amdgpu_device *adev = get_amdgpu_device(kgd); 120 121 lock_srbm(kgd, 0, 0, 0, vmid); 122 123 WREG32(mmSH_MEM_CONFIG, sh_mem_config); 124 WREG32(mmSH_MEM_APE1_BASE, sh_mem_ape1_base); 125 WREG32(mmSH_MEM_APE1_LIMIT, sh_mem_ape1_limit); 126 WREG32(mmSH_MEM_BASES, sh_mem_bases); 127 128 unlock_srbm(kgd); 129 } 130 131 static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid, 132 unsigned int vmid) 133 { 134 struct amdgpu_device *adev = get_amdgpu_device(kgd); 135 136 /* 137 * We have to assume that there is no outstanding mapping. 138 * The ATC_VMID_PASID_MAPPING_UPDATE_STATUS bit could be 0 because 139 * a mapping is in progress or because a mapping finished 140 * and the SW cleared it. 141 * So the protocol is to always wait & clear. 142 */ 143 uint32_t pasid_mapping = (pasid == 0) ? 0 : (uint32_t)pasid | 144 ATC_VMID0_PASID_MAPPING__VALID_MASK; 145 146 WREG32(mmATC_VMID0_PASID_MAPPING + vmid, pasid_mapping); 147 148 while (!(RREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS) & (1U << vmid))) 149 cpu_relax(); 150 WREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS, 1U << vmid); 151 152 /* Mapping vmid to pasid also for IH block */ 153 WREG32(mmIH_VMID_0_LUT + vmid, pasid_mapping); 154 155 return 0; 156 } 157 158 static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id) 159 { 160 struct amdgpu_device *adev = get_amdgpu_device(kgd); 161 uint32_t mec; 162 uint32_t pipe; 163 164 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; 165 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); 166 167 lock_srbm(kgd, mec, pipe, 0, 0); 168 169 WREG32(mmCPC_INT_CNTL, CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK | 170 CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK); 171 172 unlock_srbm(kgd); 173 174 return 0; 175 } 176 177 static inline uint32_t get_sdma_rlc_reg_offset(struct vi_sdma_mqd *m) 178 { 179 uint32_t retval; 180 181 retval = m->sdma_engine_id * SDMA1_REGISTER_OFFSET + 182 m->sdma_queue_id * KFD_VI_SDMA_QUEUE_OFFSET; 183 184 pr_debug("RLC register offset for SDMA%d RLC%d: 0x%x\n", 185 m->sdma_engine_id, m->sdma_queue_id, retval); 186 187 return retval; 188 } 189 190 static inline struct vi_mqd *get_mqd(void *mqd) 191 { 192 return (struct vi_mqd *)mqd; 193 } 194 195 static inline struct vi_sdma_mqd *get_sdma_mqd(void *mqd) 196 { 197 return (struct vi_sdma_mqd *)mqd; 198 } 199 200 static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, 201 uint32_t queue_id, uint32_t __user *wptr, 202 uint32_t wptr_shift, uint32_t wptr_mask, 203 struct mm_struct *mm) 204 { 205 struct amdgpu_device *adev = get_amdgpu_device(kgd); 206 struct vi_mqd *m; 207 uint32_t *mqd_hqd; 208 uint32_t reg, wptr_val, data; 209 bool valid_wptr = false; 210 211 m = get_mqd(mqd); 212 213 acquire_queue(kgd, pipe_id, queue_id); 214 215 /* HIQ is set during driver init period with vmid set to 0*/ 216 if (m->cp_hqd_vmid == 0) { 217 uint32_t value, mec, pipe; 218 219 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; 220 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); 221 222 pr_debug("kfd: set HIQ, mec:%d, pipe:%d, queue:%d.\n", 223 mec, pipe, queue_id); 224 value = RREG32(mmRLC_CP_SCHEDULERS); 225 value = REG_SET_FIELD(value, RLC_CP_SCHEDULERS, scheduler1, 226 ((mec << 5) | (pipe << 3) | queue_id | 0x80)); 227 WREG32(mmRLC_CP_SCHEDULERS, value); 228 } 229 230 /* HQD registers extend from CP_MQD_BASE_ADDR to CP_HQD_EOP_WPTR_MEM. */ 231 mqd_hqd = &m->cp_mqd_base_addr_lo; 232 233 for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_HQD_EOP_CONTROL; reg++) 234 WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]); 235 236 /* Tonga errata: EOP RPTR/WPTR should be left unmodified. 237 * This is safe since EOP RPTR==WPTR for any inactive HQD 238 * on ASICs that do not support context-save. 239 * EOP writes/reads can start anywhere in the ring. 240 */ 241 if (get_amdgpu_device(kgd)->asic_type != CHIP_TONGA) { 242 WREG32(mmCP_HQD_EOP_RPTR, m->cp_hqd_eop_rptr); 243 WREG32(mmCP_HQD_EOP_WPTR, m->cp_hqd_eop_wptr); 244 WREG32(mmCP_HQD_EOP_WPTR_MEM, m->cp_hqd_eop_wptr_mem); 245 } 246 247 for (reg = mmCP_HQD_EOP_EVENTS; reg <= mmCP_HQD_ERROR; reg++) 248 WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]); 249 250 /* Copy userspace write pointer value to register. 251 * Activate doorbell logic to monitor subsequent changes. 252 */ 253 data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control, 254 CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1); 255 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, data); 256 257 /* read_user_ptr may take the mm->mmap_sem. 258 * release srbm_mutex to avoid circular dependency between 259 * srbm_mutex->mm_sem->reservation_ww_class_mutex->srbm_mutex. 260 */ 261 release_queue(kgd); 262 valid_wptr = read_user_wptr(mm, wptr, wptr_val); 263 acquire_queue(kgd, pipe_id, queue_id); 264 if (valid_wptr) 265 WREG32(mmCP_HQD_PQ_WPTR, (wptr_val << wptr_shift) & wptr_mask); 266 267 data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1); 268 WREG32(mmCP_HQD_ACTIVE, data); 269 270 release_queue(kgd); 271 272 return 0; 273 } 274 275 static int kgd_hqd_dump(struct kgd_dev *kgd, 276 uint32_t pipe_id, uint32_t queue_id, 277 uint32_t (**dump)[2], uint32_t *n_regs) 278 { 279 struct amdgpu_device *adev = get_amdgpu_device(kgd); 280 uint32_t i = 0, reg; 281 #define HQD_N_REGS (54+4) 282 #define DUMP_REG(addr) do { \ 283 if (WARN_ON_ONCE(i >= HQD_N_REGS)) \ 284 break; \ 285 (*dump)[i][0] = (addr) << 2; \ 286 (*dump)[i++][1] = RREG32(addr); \ 287 } while (0) 288 289 *dump = kmalloc_array(HQD_N_REGS * 2, sizeof(uint32_t), GFP_KERNEL); 290 if (*dump == NULL) 291 return -ENOMEM; 292 293 acquire_queue(kgd, pipe_id, queue_id); 294 295 DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE0); 296 DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE1); 297 DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE2); 298 DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE3); 299 300 for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_HQD_EOP_DONES; reg++) 301 DUMP_REG(reg); 302 303 release_queue(kgd); 304 305 WARN_ON_ONCE(i != HQD_N_REGS); 306 *n_regs = i; 307 308 return 0; 309 } 310 311 static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd, 312 uint32_t __user *wptr, struct mm_struct *mm) 313 { 314 struct amdgpu_device *adev = get_amdgpu_device(kgd); 315 struct vi_sdma_mqd *m; 316 unsigned long end_jiffies; 317 uint32_t sdma_rlc_reg_offset; 318 uint32_t data; 319 320 m = get_sdma_mqd(mqd); 321 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(m); 322 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, 323 m->sdmax_rlcx_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)); 324 325 end_jiffies = msecs_to_jiffies(2000) + jiffies; 326 while (true) { 327 data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS); 328 if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK) 329 break; 330 if (time_after(jiffies, end_jiffies)) { 331 pr_err("SDMA RLC not idle in %s\n", __func__); 332 return -ETIME; 333 } 334 usleep_range(500, 1000); 335 } 336 337 data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL, 338 ENABLE, 1); 339 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data); 340 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR, 341 m->sdmax_rlcx_rb_rptr); 342 343 if (read_user_wptr(mm, wptr, data)) 344 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, data); 345 else 346 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, 347 m->sdmax_rlcx_rb_rptr); 348 349 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_VIRTUAL_ADDR, 350 m->sdmax_rlcx_virtual_addr); 351 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base); 352 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE_HI, 353 m->sdmax_rlcx_rb_base_hi); 354 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_LO, 355 m->sdmax_rlcx_rb_rptr_addr_lo); 356 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_HI, 357 m->sdmax_rlcx_rb_rptr_addr_hi); 358 359 data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL, 360 RB_ENABLE, 1); 361 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, data); 362 363 return 0; 364 } 365 366 static int kgd_hqd_sdma_dump(struct kgd_dev *kgd, 367 uint32_t engine_id, uint32_t queue_id, 368 uint32_t (**dump)[2], uint32_t *n_regs) 369 { 370 struct amdgpu_device *adev = get_amdgpu_device(kgd); 371 uint32_t sdma_offset = engine_id * SDMA1_REGISTER_OFFSET + 372 queue_id * KFD_VI_SDMA_QUEUE_OFFSET; 373 uint32_t i = 0, reg; 374 #undef HQD_N_REGS 375 #define HQD_N_REGS (19+4+2+3+7) 376 377 *dump = kmalloc_array(HQD_N_REGS * 2, sizeof(uint32_t), GFP_KERNEL); 378 if (*dump == NULL) 379 return -ENOMEM; 380 381 for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++) 382 DUMP_REG(sdma_offset + reg); 383 for (reg = mmSDMA0_RLC0_VIRTUAL_ADDR; reg <= mmSDMA0_RLC0_WATERMARK; 384 reg++) 385 DUMP_REG(sdma_offset + reg); 386 for (reg = mmSDMA0_RLC0_CSA_ADDR_LO; reg <= mmSDMA0_RLC0_CSA_ADDR_HI; 387 reg++) 388 DUMP_REG(sdma_offset + reg); 389 for (reg = mmSDMA0_RLC0_IB_SUB_REMAIN; reg <= mmSDMA0_RLC0_DUMMY_REG; 390 reg++) 391 DUMP_REG(sdma_offset + reg); 392 for (reg = mmSDMA0_RLC0_MIDCMD_DATA0; reg <= mmSDMA0_RLC0_MIDCMD_CNTL; 393 reg++) 394 DUMP_REG(sdma_offset + reg); 395 396 WARN_ON_ONCE(i != HQD_N_REGS); 397 *n_regs = i; 398 399 return 0; 400 } 401 402 static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address, 403 uint32_t pipe_id, uint32_t queue_id) 404 { 405 struct amdgpu_device *adev = get_amdgpu_device(kgd); 406 uint32_t act; 407 bool retval = false; 408 uint32_t low, high; 409 410 acquire_queue(kgd, pipe_id, queue_id); 411 act = RREG32(mmCP_HQD_ACTIVE); 412 if (act) { 413 low = lower_32_bits(queue_address >> 8); 414 high = upper_32_bits(queue_address >> 8); 415 416 if (low == RREG32(mmCP_HQD_PQ_BASE) && 417 high == RREG32(mmCP_HQD_PQ_BASE_HI)) 418 retval = true; 419 } 420 release_queue(kgd); 421 return retval; 422 } 423 424 static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd) 425 { 426 struct amdgpu_device *adev = get_amdgpu_device(kgd); 427 struct vi_sdma_mqd *m; 428 uint32_t sdma_rlc_reg_offset; 429 uint32_t sdma_rlc_rb_cntl; 430 431 m = get_sdma_mqd(mqd); 432 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(m); 433 434 sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL); 435 436 if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK) 437 return true; 438 439 return false; 440 } 441 442 static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd, 443 enum kfd_preempt_type reset_type, 444 unsigned int utimeout, uint32_t pipe_id, 445 uint32_t queue_id) 446 { 447 struct amdgpu_device *adev = get_amdgpu_device(kgd); 448 uint32_t temp; 449 enum hqd_dequeue_request_type type; 450 unsigned long flags, end_jiffies; 451 int retry; 452 struct vi_mqd *m = get_mqd(mqd); 453 454 if (adev->in_gpu_reset) 455 return -EIO; 456 457 acquire_queue(kgd, pipe_id, queue_id); 458 459 if (m->cp_hqd_vmid == 0) 460 WREG32_FIELD(RLC_CP_SCHEDULERS, scheduler1, 0); 461 462 switch (reset_type) { 463 case KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN: 464 type = DRAIN_PIPE; 465 break; 466 case KFD_PREEMPT_TYPE_WAVEFRONT_RESET: 467 type = RESET_WAVES; 468 break; 469 default: 470 type = DRAIN_PIPE; 471 break; 472 } 473 474 /* Workaround: If IQ timer is active and the wait time is close to or 475 * equal to 0, dequeueing is not safe. Wait until either the wait time 476 * is larger or timer is cleared. Also, ensure that IQ_REQ_PEND is 477 * cleared before continuing. Also, ensure wait times are set to at 478 * least 0x3. 479 */ 480 local_irq_save(flags); 481 preempt_disable(); 482 retry = 5000; /* wait for 500 usecs at maximum */ 483 while (true) { 484 temp = RREG32(mmCP_HQD_IQ_TIMER); 485 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, PROCESSING_IQ)) { 486 pr_debug("HW is processing IQ\n"); 487 goto loop; 488 } 489 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, ACTIVE)) { 490 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, RETRY_TYPE) 491 == 3) /* SEM-rearm is safe */ 492 break; 493 /* Wait time 3 is safe for CP, but our MMIO read/write 494 * time is close to 1 microsecond, so check for 10 to 495 * leave more buffer room 496 */ 497 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, WAIT_TIME) 498 >= 10) 499 break; 500 pr_debug("IQ timer is active\n"); 501 } else 502 break; 503 loop: 504 if (!retry) { 505 pr_err("CP HQD IQ timer status time out\n"); 506 break; 507 } 508 ndelay(100); 509 --retry; 510 } 511 retry = 1000; 512 while (true) { 513 temp = RREG32(mmCP_HQD_DEQUEUE_REQUEST); 514 if (!(temp & CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK)) 515 break; 516 pr_debug("Dequeue request is pending\n"); 517 518 if (!retry) { 519 pr_err("CP HQD dequeue request time out\n"); 520 break; 521 } 522 ndelay(100); 523 --retry; 524 } 525 local_irq_restore(flags); 526 preempt_enable(); 527 528 WREG32(mmCP_HQD_DEQUEUE_REQUEST, type); 529 530 end_jiffies = (utimeout * HZ / 1000) + jiffies; 531 while (true) { 532 temp = RREG32(mmCP_HQD_ACTIVE); 533 if (!(temp & CP_HQD_ACTIVE__ACTIVE_MASK)) 534 break; 535 if (time_after(jiffies, end_jiffies)) { 536 pr_err("cp queue preemption time out.\n"); 537 release_queue(kgd); 538 return -ETIME; 539 } 540 usleep_range(500, 1000); 541 } 542 543 release_queue(kgd); 544 return 0; 545 } 546 547 static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd, 548 unsigned int utimeout) 549 { 550 struct amdgpu_device *adev = get_amdgpu_device(kgd); 551 struct vi_sdma_mqd *m; 552 uint32_t sdma_rlc_reg_offset; 553 uint32_t temp; 554 unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies; 555 556 m = get_sdma_mqd(mqd); 557 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(m); 558 559 temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL); 560 temp = temp & ~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK; 561 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, temp); 562 563 while (true) { 564 temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS); 565 if (temp & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK) 566 break; 567 if (time_after(jiffies, end_jiffies)) { 568 pr_err("SDMA RLC not idle in %s\n", __func__); 569 return -ETIME; 570 } 571 usleep_range(500, 1000); 572 } 573 574 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, 0); 575 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, 576 RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL) | 577 SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK); 578 579 m->sdmax_rlcx_rb_rptr = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR); 580 581 return 0; 582 } 583 584 static bool get_atc_vmid_pasid_mapping_info(struct kgd_dev *kgd, 585 uint8_t vmid, uint16_t *p_pasid) 586 { 587 uint32_t value; 588 struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 589 590 value = RREG32(mmATC_VMID0_PASID_MAPPING + vmid); 591 *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK; 592 593 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK); 594 } 595 596 static int kgd_address_watch_disable(struct kgd_dev *kgd) 597 { 598 return 0; 599 } 600 601 static int kgd_address_watch_execute(struct kgd_dev *kgd, 602 unsigned int watch_point_id, 603 uint32_t cntl_val, 604 uint32_t addr_hi, 605 uint32_t addr_lo) 606 { 607 return 0; 608 } 609 610 static int kgd_wave_control_execute(struct kgd_dev *kgd, 611 uint32_t gfx_index_val, 612 uint32_t sq_cmd) 613 { 614 struct amdgpu_device *adev = get_amdgpu_device(kgd); 615 uint32_t data = 0; 616 617 mutex_lock(&adev->grbm_idx_mutex); 618 619 WREG32(mmGRBM_GFX_INDEX, gfx_index_val); 620 WREG32(mmSQ_CMD, sq_cmd); 621 622 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 623 INSTANCE_BROADCAST_WRITES, 1); 624 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 625 SH_BROADCAST_WRITES, 1); 626 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 627 SE_BROADCAST_WRITES, 1); 628 629 WREG32(mmGRBM_GFX_INDEX, data); 630 mutex_unlock(&adev->grbm_idx_mutex); 631 632 return 0; 633 } 634 635 static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd, 636 unsigned int watch_point_id, 637 unsigned int reg_offset) 638 { 639 return 0; 640 } 641 642 static void set_scratch_backing_va(struct kgd_dev *kgd, 643 uint64_t va, uint32_t vmid) 644 { 645 struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 646 647 lock_srbm(kgd, 0, 0, 0, vmid); 648 WREG32(mmSH_HIDDEN_PRIVATE_BASE_VMID, va); 649 unlock_srbm(kgd); 650 } 651 652 static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid, 653 uint64_t page_table_base) 654 { 655 struct amdgpu_device *adev = get_amdgpu_device(kgd); 656 657 if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) { 658 pr_err("trying to set page table base for wrong VMID\n"); 659 return; 660 } 661 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8, 662 lower_32_bits(page_table_base)); 663 } 664 665 const struct kfd2kgd_calls gfx_v8_kfd2kgd = { 666 .program_sh_mem_settings = kgd_program_sh_mem_settings, 667 .set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping, 668 .init_interrupts = kgd_init_interrupts, 669 .hqd_load = kgd_hqd_load, 670 .hqd_sdma_load = kgd_hqd_sdma_load, 671 .hqd_dump = kgd_hqd_dump, 672 .hqd_sdma_dump = kgd_hqd_sdma_dump, 673 .hqd_is_occupied = kgd_hqd_is_occupied, 674 .hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied, 675 .hqd_destroy = kgd_hqd_destroy, 676 .hqd_sdma_destroy = kgd_hqd_sdma_destroy, 677 .address_watch_disable = kgd_address_watch_disable, 678 .address_watch_execute = kgd_address_watch_execute, 679 .wave_control_execute = kgd_wave_control_execute, 680 .address_watch_get_offset = kgd_address_watch_get_offset, 681 .get_atc_vmid_pasid_mapping_info = 682 get_atc_vmid_pasid_mapping_info, 683 .set_scratch_backing_va = set_scratch_backing_va, 684 .get_tile_config = get_tile_config, 685 .set_vm_context_page_table_base = set_vm_context_page_table_base, 686 }; 687
Indexes created Fri Sep 26 20:09:58 GMT 2025