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      1 /*	$NetBSD: nouveau_nvkm_subdev_acr_gm200.c,v 1.3 2021/12/19 10:51:58 riastradh Exp $	*/
      2 
      3 /*
      4  * Copyright 2019 Red Hat Inc.
      5  *
      6  * Permission is hereby granted, free of charge, to any person obtaining a
      7  * copy of this software and associated documentation files (the "Software"),
      8  * to deal in the Software without restriction, including without limitation
      9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
     10  * and/or sell copies of the Software, and to permit persons to whom the
     11  * Software is furnished to do so, subject to the following conditions:
     12  *
     13  * The above copyright notice and this permission notice shall be included in
     14  * all copies or substantial portions of the Software.
     15  *
     16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     22  * OTHER DEALINGS IN THE SOFTWARE.
     23  */
     24 #include <sys/cdefs.h>
     25 __KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_subdev_acr_gm200.c,v 1.3 2021/12/19 10:51:58 riastradh Exp $");
     26 
     27 #include "priv.h"
     28 
     29 #include <core/falcon.h>
     30 #include <core/firmware.h>
     31 #include <core/memory.h>
     32 #include <subdev/mc.h>
     33 #include <subdev/mmu.h>
     34 #include <subdev/pmu.h>
     35 #include <subdev/timer.h>
     36 
     37 #include <nvfw/acr.h>
     38 #include <nvfw/flcn.h>
     39 
     40 #include <linux/nbsd-namespace.h>
     41 
     42 int
     43 gm200_acr_init(struct nvkm_acr *acr)
     44 {
     45 	return nvkm_acr_hsf_boot(acr, "load");
     46 }
     47 
     48 void
     49 gm200_acr_wpr_check(struct nvkm_acr *acr, u64 *start, u64 *limit)
     50 {
     51 	struct nvkm_device *device = acr->subdev.device;
     52 
     53 	nvkm_wr32(device, 0x100cd4, 2);
     54 	*start = (u64)(nvkm_rd32(device, 0x100cd4) & 0xffffff00) << 8;
     55 	nvkm_wr32(device, 0x100cd4, 3);
     56 	*limit = (u64)(nvkm_rd32(device, 0x100cd4) & 0xffffff00) << 8;
     57 	*limit = *limit + 0x20000;
     58 }
     59 
     60 void
     61 gm200_acr_wpr_patch(struct nvkm_acr *acr, s64 adjust)
     62 {
     63 	struct nvkm_subdev *subdev = &acr->subdev;
     64 	struct wpr_header hdr;
     65 	struct lsb_header lsb;
     66 	struct nvkm_acr_lsf *lsfw;
     67 	u32 offset = 0;
     68 
     69 	do {
     70 		nvkm_robj(acr->wpr, offset, &hdr, sizeof(hdr));
     71 		wpr_header_dump(subdev, &hdr);
     72 
     73 		list_for_each_entry(lsfw, &acr->lsfw, head) {
     74 			if (lsfw->id != hdr.falcon_id)
     75 				continue;
     76 
     77 			nvkm_robj(acr->wpr, hdr.lsb_offset, &lsb, sizeof(lsb));
     78 			lsb_header_dump(subdev, &lsb);
     79 
     80 			lsfw->func->bld_patch(acr, lsb.tail.bl_data_off, adjust);
     81 			break;
     82 		}
     83 		offset += sizeof(hdr);
     84 	} while (hdr.falcon_id != WPR_HEADER_V0_FALCON_ID_INVALID);
     85 }
     86 
     87 void
     88 gm200_acr_wpr_build_lsb_tail(struct nvkm_acr_lsfw *lsfw,
     89 			     struct lsb_header_tail *hdr)
     90 {
     91 	hdr->ucode_off = lsfw->offset.img;
     92 	hdr->ucode_size = lsfw->ucode_size;
     93 	hdr->data_size = lsfw->data_size;
     94 	hdr->bl_code_size = lsfw->bootloader_size;
     95 	hdr->bl_imem_off = lsfw->bootloader_imem_offset;
     96 	hdr->bl_data_off = lsfw->offset.bld;
     97 	hdr->bl_data_size = lsfw->bl_data_size;
     98 	hdr->app_code_off = lsfw->app_start_offset +
     99 			   lsfw->app_resident_code_offset;
    100 	hdr->app_code_size = lsfw->app_resident_code_size;
    101 	hdr->app_data_off = lsfw->app_start_offset +
    102 			   lsfw->app_resident_data_offset;
    103 	hdr->app_data_size = lsfw->app_resident_data_size;
    104 	hdr->flags = lsfw->func->flags;
    105 }
    106 
    107 static int
    108 gm200_acr_wpr_build_lsb(struct nvkm_acr *acr, struct nvkm_acr_lsfw *lsfw)
    109 {
    110 	struct lsb_header hdr;
    111 
    112 	if (WARN_ON(lsfw->sig->size != sizeof(hdr.signature)))
    113 		return -EINVAL;
    114 
    115 	memcpy(&hdr.signature, lsfw->sig->data, lsfw->sig->size);
    116 	gm200_acr_wpr_build_lsb_tail(lsfw, &hdr.tail);
    117 
    118 	nvkm_wobj(acr->wpr, lsfw->offset.lsb, &hdr, sizeof(hdr));
    119 	return 0;
    120 }
    121 
    122 int
    123 gm200_acr_wpr_build(struct nvkm_acr *acr, struct nvkm_acr_lsf *rtos)
    124 {
    125 	struct nvkm_acr_lsfw *lsfw;
    126 	u32 offset = 0;
    127 	int ret;
    128 
    129 	/* Fill per-LSF structures. */
    130 	list_for_each_entry(lsfw, &acr->lsfw, head) {
    131 		struct wpr_header hdr = {
    132 			.falcon_id = lsfw->id,
    133 			.lsb_offset = lsfw->offset.lsb,
    134 			.bootstrap_owner = NVKM_ACR_LSF_PMU,
    135 			.lazy_bootstrap = rtos && lsfw->id != rtos->id,
    136 			.status = WPR_HEADER_V0_STATUS_COPY,
    137 		};
    138 
    139 		/* Write WPR header. */
    140 		nvkm_wobj(acr->wpr, offset, &hdr, sizeof(hdr));
    141 		offset += sizeof(hdr);
    142 
    143 		/* Write LSB header. */
    144 		ret = gm200_acr_wpr_build_lsb(acr, lsfw);
    145 		if (ret)
    146 			return ret;
    147 
    148 		/* Write ucode image. */
    149 		nvkm_wobj(acr->wpr, lsfw->offset.img,
    150 				    lsfw->img.data,
    151 				    lsfw->img.size);
    152 
    153 		/* Write bootloader data. */
    154 		lsfw->func->bld_write(acr, lsfw->offset.bld, lsfw);
    155 	}
    156 
    157 	/* Finalise WPR. */
    158 	nvkm_wo32(acr->wpr, offset, WPR_HEADER_V0_FALCON_ID_INVALID);
    159 	return 0;
    160 }
    161 
    162 static int
    163 gm200_acr_wpr_alloc(struct nvkm_acr *acr, u32 wpr_size)
    164 {
    165 	int ret = nvkm_memory_new(acr->subdev.device, NVKM_MEM_TARGET_INST,
    166 				  ALIGN(wpr_size, 0x40000), 0x40000, true,
    167 				  &acr->wpr);
    168 	if (ret)
    169 		return ret;
    170 
    171 	acr->wpr_start = nvkm_memory_addr(acr->wpr);
    172 	acr->wpr_end = acr->wpr_start + nvkm_memory_size(acr->wpr);
    173 	return 0;
    174 }
    175 
    176 u32
    177 gm200_acr_wpr_layout(struct nvkm_acr *acr)
    178 {
    179 	struct nvkm_acr_lsfw *lsfw;
    180 	u32 wpr = 0;
    181 
    182 	wpr += 11 /* MAX_LSF */ * sizeof(struct wpr_header);
    183 
    184 	list_for_each_entry(lsfw, &acr->lsfw, head) {
    185 		wpr  = ALIGN(wpr, 256);
    186 		lsfw->offset.lsb = wpr;
    187 		wpr += sizeof(struct lsb_header);
    188 
    189 		wpr  = ALIGN(wpr, 4096);
    190 		lsfw->offset.img = wpr;
    191 		wpr += lsfw->img.size;
    192 
    193 		wpr  = ALIGN(wpr, 256);
    194 		lsfw->offset.bld = wpr;
    195 		lsfw->bl_data_size = ALIGN(lsfw->func->bld_size, 256);
    196 		wpr += lsfw->bl_data_size;
    197 	}
    198 
    199 	return wpr;
    200 }
    201 
    202 int
    203 gm200_acr_wpr_parse(struct nvkm_acr *acr)
    204 {
    205 	const struct wpr_header *hdr = (void *)acr->wpr_fw->data;
    206 
    207 	while (hdr->falcon_id != WPR_HEADER_V0_FALCON_ID_INVALID) {
    208 		wpr_header_dump(&acr->subdev, hdr);
    209 		if (!nvkm_acr_lsfw_add(NULL, acr, NULL, (hdr++)->falcon_id))
    210 			return -ENOMEM;
    211 	}
    212 
    213 	return 0;
    214 }
    215 
    216 void
    217 gm200_acr_hsfw_bld(struct nvkm_acr *acr, struct nvkm_acr_hsf *hsf)
    218 {
    219 	struct flcn_bl_dmem_desc_v1 hsdesc = {
    220 		.ctx_dma = FALCON_DMAIDX_VIRT,
    221 		.code_dma_base = hsf->vma->addr,
    222 		.non_sec_code_off = hsf->non_sec_addr,
    223 		.non_sec_code_size = hsf->non_sec_size,
    224 		.sec_code_off = hsf->sec_addr,
    225 		.sec_code_size = hsf->sec_size,
    226 		.code_entry_point = 0,
    227 		.data_dma_base = hsf->vma->addr + hsf->data_addr,
    228 		.data_size = hsf->data_size,
    229 	};
    230 
    231 	flcn_bl_dmem_desc_v1_dump(&acr->subdev, &hsdesc);
    232 
    233 	nvkm_falcon_load_dmem(hsf->falcon, &hsdesc, 0, sizeof(hsdesc), 0);
    234 }
    235 
    236 int
    237 gm200_acr_hsfw_boot(struct nvkm_acr *acr, struct nvkm_acr_hsf *hsf,
    238 		    u32 intr_clear, u32 mbox0_ok)
    239 {
    240 	struct nvkm_subdev *subdev = &acr->subdev;
    241 	struct nvkm_device *device = subdev->device;
    242 	struct nvkm_falcon *falcon = hsf->falcon;
    243 	u32 mbox0, mbox1;
    244 	int ret;
    245 
    246 	/* Reset falcon. */
    247 	nvkm_falcon_reset(falcon);
    248 	nvkm_falcon_bind_context(falcon, acr->inst);
    249 
    250 	/* Load bootloader into IMEM. */
    251 	nvkm_falcon_load_imem(falcon, hsf->imem,
    252 				      falcon->code.limit - hsf->imem_size,
    253 				      hsf->imem_size,
    254 				      hsf->imem_tag,
    255 				      0, false);
    256 
    257 	/* Load bootloader data into DMEM. */
    258 	hsf->func->bld(acr, hsf);
    259 
    260 	/* Boot the falcon. */
    261 	nvkm_mc_intr_mask(device, falcon->owner->index, false);
    262 
    263 	nvkm_falcon_wr32(falcon, 0x040, 0xdeada5a5);
    264 	nvkm_falcon_set_start_addr(falcon, hsf->imem_tag << 8);
    265 	nvkm_falcon_start(falcon);
    266 	ret = nvkm_falcon_wait_for_halt(falcon, 100);
    267 	if (ret)
    268 		return ret;
    269 
    270 	/* Check for successful completion. */
    271 	mbox0 = nvkm_falcon_rd32(falcon, 0x040);
    272 	mbox1 = nvkm_falcon_rd32(falcon, 0x044);
    273 	nvkm_debug(subdev, "mailbox %08x %08x\n", mbox0, mbox1);
    274 	if (mbox0 && mbox0 != mbox0_ok)
    275 		return -EIO;
    276 
    277 	nvkm_falcon_clear_interrupt(falcon, intr_clear);
    278 	nvkm_mc_intr_mask(device, falcon->owner->index, true);
    279 	return ret;
    280 }
    281 
    282 int
    283 gm200_acr_hsfw_load(struct nvkm_acr *acr, struct nvkm_acr_hsfw *hsfw,
    284 		    struct nvkm_falcon *falcon)
    285 {
    286 	struct nvkm_subdev *subdev = &acr->subdev;
    287 	struct nvkm_acr_hsf *hsf;
    288 	int ret;
    289 
    290 	/* Patch the appropriate signature (production/debug) into the FW
    291 	 * image, as determined by the mode the falcon is in.
    292 	 */
    293 	ret = nvkm_falcon_get(falcon, subdev);
    294 	if (ret)
    295 		return ret;
    296 
    297 	if (hsfw->sig.patch_loc) {
    298 		if (!falcon->debug) {
    299 			nvkm_debug(subdev, "patching production signature\n");
    300 			memcpy(hsfw->image + hsfw->sig.patch_loc,
    301 			       hsfw->sig.prod.data,
    302 			       hsfw->sig.prod.size);
    303 		} else {
    304 			nvkm_debug(subdev, "patching debug signature\n");
    305 			memcpy(hsfw->image + hsfw->sig.patch_loc,
    306 			       hsfw->sig.dbg.data,
    307 			       hsfw->sig.dbg.size);
    308 		}
    309 	}
    310 
    311 	nvkm_falcon_put(falcon, subdev);
    312 
    313 	if (!(hsf = kzalloc(sizeof(*hsf), GFP_KERNEL)))
    314 		return -ENOMEM;
    315 	hsf->func = hsfw->func;
    316 	hsf->name = hsfw->name;
    317 	list_add_tail(&hsf->head, &acr->hsf);
    318 
    319 	hsf->imem_size = hsfw->imem_size;
    320 	hsf->imem_tag = hsfw->imem_tag;
    321 	hsf->imem = kmemdup(hsfw->imem, hsfw->imem_size, GFP_KERNEL);
    322 	if (!hsf->imem)
    323 		return -ENOMEM;
    324 
    325 	hsf->non_sec_addr = hsfw->non_sec_addr;
    326 	hsf->non_sec_size = hsfw->non_sec_size;
    327 	hsf->sec_addr = hsfw->sec_addr;
    328 	hsf->sec_size = hsfw->sec_size;
    329 	hsf->data_addr = hsfw->data_addr;
    330 	hsf->data_size = hsfw->data_size;
    331 
    332 	/* Make the FW image accessible to the HS bootloader. */
    333 	ret = nvkm_memory_new(subdev->device, NVKM_MEM_TARGET_INST,
    334 			      hsfw->image_size, 0x1000, false, &hsf->ucode);
    335 	if (ret)
    336 		return ret;
    337 
    338 	nvkm_kmap(hsf->ucode);
    339 	nvkm_wobj(hsf->ucode, 0, hsfw->image, hsfw->image_size);
    340 	nvkm_done(hsf->ucode);
    341 
    342 	ret = nvkm_vmm_get(acr->vmm, 12, nvkm_memory_size(hsf->ucode),
    343 			   &hsf->vma);
    344 	if (ret)
    345 		return ret;
    346 
    347 	ret = nvkm_memory_map(hsf->ucode, 0, acr->vmm, hsf->vma, NULL, 0);
    348 	if (ret)
    349 		return ret;
    350 
    351 	hsf->falcon = falcon;
    352 	return 0;
    353 }
    354 
    355 int
    356 gm200_acr_unload_boot(struct nvkm_acr *acr, struct nvkm_acr_hsf *hsf)
    357 {
    358 	return gm200_acr_hsfw_boot(acr, hsf, 0, 0x1d);
    359 }
    360 
    361 int
    362 gm200_acr_unload_load(struct nvkm_acr *acr, struct nvkm_acr_hsfw *hsfw)
    363 {
    364 	return gm200_acr_hsfw_load(acr, hsfw, &acr->subdev.device->pmu->falcon);
    365 }
    366 
    367 const struct nvkm_acr_hsf_func
    368 gm200_acr_unload_0 = {
    369 	.load = gm200_acr_unload_load,
    370 	.boot = gm200_acr_unload_boot,
    371 	.bld = gm200_acr_hsfw_bld,
    372 };
    373 
    374 MODULE_FIRMWARE("nvidia/gm200/acr/ucode_unload.bin");
    375 MODULE_FIRMWARE("nvidia/gm204/acr/ucode_unload.bin");
    376 MODULE_FIRMWARE("nvidia/gm206/acr/ucode_unload.bin");
    377 MODULE_FIRMWARE("nvidia/gp100/acr/ucode_unload.bin");
    378 
    379 static const struct nvkm_acr_hsf_fwif
    380 gm200_acr_unload_fwif[] = {
    381 	{ 0, nvkm_acr_hsfw_load, &gm200_acr_unload_0 },
    382 	{}
    383 };
    384 
    385 int
    386 gm200_acr_load_boot(struct nvkm_acr *acr, struct nvkm_acr_hsf *hsf)
    387 {
    388 	return gm200_acr_hsfw_boot(acr, hsf, 0x10, 0);
    389 }
    390 
    391 static int
    392 gm200_acr_load_load(struct nvkm_acr *acr, struct nvkm_acr_hsfw *hsfw)
    393 {
    394 	struct flcn_acr_desc *desc = (void *)&hsfw->image[hsfw->data_addr];
    395 
    396 	desc->wpr_region_id = 1;
    397 	desc->regions.no_regions = 2;
    398 	desc->regions.region_props[0].start_addr = acr->wpr_start >> 8;
    399 	desc->regions.region_props[0].end_addr = acr->wpr_end >> 8;
    400 	desc->regions.region_props[0].region_id = 1;
    401 	desc->regions.region_props[0].read_mask = 0xf;
    402 	desc->regions.region_props[0].write_mask = 0xc;
    403 	desc->regions.region_props[0].client_mask = 0x2;
    404 	flcn_acr_desc_dump(&acr->subdev, desc);
    405 
    406 	return gm200_acr_hsfw_load(acr, hsfw, &acr->subdev.device->pmu->falcon);
    407 }
    408 
    409 static const struct nvkm_acr_hsf_func
    410 gm200_acr_load_0 = {
    411 	.load = gm200_acr_load_load,
    412 	.boot = gm200_acr_load_boot,
    413 	.bld = gm200_acr_hsfw_bld,
    414 };
    415 
    416 MODULE_FIRMWARE("nvidia/gm200/acr/bl.bin");
    417 MODULE_FIRMWARE("nvidia/gm200/acr/ucode_load.bin");
    418 
    419 MODULE_FIRMWARE("nvidia/gm204/acr/bl.bin");
    420 MODULE_FIRMWARE("nvidia/gm204/acr/ucode_load.bin");
    421 
    422 MODULE_FIRMWARE("nvidia/gm206/acr/bl.bin");
    423 MODULE_FIRMWARE("nvidia/gm206/acr/ucode_load.bin");
    424 
    425 MODULE_FIRMWARE("nvidia/gp100/acr/bl.bin");
    426 MODULE_FIRMWARE("nvidia/gp100/acr/ucode_load.bin");
    427 
    428 static const struct nvkm_acr_hsf_fwif
    429 gm200_acr_load_fwif[] = {
    430 	{ 0, nvkm_acr_hsfw_load, &gm200_acr_load_0 },
    431 	{}
    432 };
    433 
    434 static const struct nvkm_acr_func
    435 gm200_acr = {
    436 	.load = gm200_acr_load_fwif,
    437 	.unload = gm200_acr_unload_fwif,
    438 	.wpr_parse = gm200_acr_wpr_parse,
    439 	.wpr_layout = gm200_acr_wpr_layout,
    440 	.wpr_alloc = gm200_acr_wpr_alloc,
    441 	.wpr_build = gm200_acr_wpr_build,
    442 	.wpr_patch = gm200_acr_wpr_patch,
    443 	.wpr_check = gm200_acr_wpr_check,
    444 	.init = gm200_acr_init,
    445 };
    446 
    447 static int
    448 gm200_acr_load(struct nvkm_acr *acr, int ver, const struct nvkm_acr_fwif *fwif)
    449 {
    450 	struct nvkm_subdev *subdev = &acr->subdev;
    451 	const struct nvkm_acr_hsf_fwif *hsfwif;
    452 
    453 	hsfwif = nvkm_firmware_load(subdev, fwif->func->load, "AcrLoad",
    454 				    acr, "acr/bl", "acr/ucode_load", "load");
    455 	if (IS_ERR(hsfwif))
    456 		return PTR_ERR(hsfwif);
    457 
    458 	hsfwif = nvkm_firmware_load(subdev, fwif->func->unload, "AcrUnload",
    459 				    acr, "acr/bl", "acr/ucode_unload",
    460 				    "unload");
    461 	if (IS_ERR(hsfwif))
    462 		return PTR_ERR(hsfwif);
    463 
    464 	return 0;
    465 }
    466 
    467 static const struct nvkm_acr_fwif
    468 gm200_acr_fwif[] = {
    469 	{ 0, gm200_acr_load, &gm200_acr },
    470 	{}
    471 };
    472 
    473 int
    474 gm200_acr_new(struct nvkm_device *device, int index, struct nvkm_acr **pacr)
    475 {
    476 	return nvkm_acr_new_(gm200_acr_fwif, device, index, pacr);
    477 }
    478