1 /* $NetBSD: nouveau_nvkm_engine_gr_gm200.c,v 1.2 2021/12/18 23:45:36 riastradh Exp $ */ 2 3 /* 4 * Copyright 2015 Red Hat Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Ben Skeggs <bskeggs (at) redhat.com> 25 */ 26 #include <sys/cdefs.h> 27 __KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_engine_gr_gm200.c,v 1.2 2021/12/18 23:45:36 riastradh Exp $"); 28 29 #include "gf100.h" 30 #include "ctxgf100.h" 31 32 #include <core/firmware.h> 33 #include <subdev/acr.h> 34 #include <subdev/secboot.h> 35 36 #include <nvfw/flcn.h> 37 38 #include <nvif/class.h> 39 40 /******************************************************************************* 41 * PGRAPH engine/subdev functions 42 ******************************************************************************/ 43 44 static void 45 gm200_gr_acr_bld_patch(struct nvkm_acr *acr, u32 bld, s64 adjust) 46 { 47 struct flcn_bl_dmem_desc_v1 hdr; 48 nvkm_robj(acr->wpr, bld, &hdr, sizeof(hdr)); 49 hdr.code_dma_base = hdr.code_dma_base + adjust; 50 hdr.data_dma_base = hdr.data_dma_base + adjust; 51 nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr)); 52 flcn_bl_dmem_desc_v1_dump(&acr->subdev, &hdr); 53 } 54 55 static void 56 gm200_gr_acr_bld_write(struct nvkm_acr *acr, u32 bld, 57 struct nvkm_acr_lsfw *lsfw) 58 { 59 const u64 base = lsfw->offset.img + lsfw->app_start_offset; 60 const u64 code = base + lsfw->app_resident_code_offset; 61 const u64 data = base + lsfw->app_resident_data_offset; 62 const struct flcn_bl_dmem_desc_v1 hdr = { 63 .ctx_dma = FALCON_DMAIDX_UCODE, 64 .code_dma_base = code, 65 .non_sec_code_off = lsfw->app_resident_code_offset, 66 .non_sec_code_size = lsfw->app_resident_code_size, 67 .code_entry_point = lsfw->app_imem_entry, 68 .data_dma_base = data, 69 .data_size = lsfw->app_resident_data_size, 70 }; 71 72 nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr)); 73 } 74 75 const struct nvkm_acr_lsf_func 76 gm200_gr_gpccs_acr = { 77 .flags = NVKM_ACR_LSF_FORCE_PRIV_LOAD, 78 .bld_size = sizeof(struct flcn_bl_dmem_desc_v1), 79 .bld_write = gm200_gr_acr_bld_write, 80 .bld_patch = gm200_gr_acr_bld_patch, 81 }; 82 83 const struct nvkm_acr_lsf_func 84 gm200_gr_fecs_acr = { 85 .bld_size = sizeof(struct flcn_bl_dmem_desc_v1), 86 .bld_write = gm200_gr_acr_bld_write, 87 .bld_patch = gm200_gr_acr_bld_patch, 88 }; 89 90 int 91 gm200_gr_rops(struct gf100_gr *gr) 92 { 93 return nvkm_rd32(gr->base.engine.subdev.device, 0x12006c); 94 } 95 96 void 97 gm200_gr_init_ds_hww_esr_2(struct gf100_gr *gr) 98 { 99 struct nvkm_device *device = gr->base.engine.subdev.device; 100 nvkm_wr32(device, 0x405848, 0xc0000000); 101 nvkm_mask(device, 0x40584c, 0x00000001, 0x00000001); 102 } 103 104 void 105 gm200_gr_init_num_active_ltcs(struct gf100_gr *gr) 106 { 107 struct nvkm_device *device = gr->base.engine.subdev.device; 108 nvkm_wr32(device, GPC_BCAST(0x08ac), nvkm_rd32(device, 0x100800)); 109 nvkm_wr32(device, GPC_BCAST(0x033c), nvkm_rd32(device, 0x100804)); 110 } 111 112 void 113 gm200_gr_init_gpc_mmu(struct gf100_gr *gr) 114 { 115 struct nvkm_device *device = gr->base.engine.subdev.device; 116 117 nvkm_wr32(device, 0x418880, nvkm_rd32(device, 0x100c80) & 0xf0001fff); 118 nvkm_wr32(device, 0x418890, 0x00000000); 119 nvkm_wr32(device, 0x418894, 0x00000000); 120 121 nvkm_wr32(device, 0x4188b4, nvkm_rd32(device, 0x100cc8)); 122 nvkm_wr32(device, 0x4188b8, nvkm_rd32(device, 0x100ccc)); 123 nvkm_wr32(device, 0x4188b0, nvkm_rd32(device, 0x100cc4)); 124 } 125 126 static void 127 gm200_gr_init_rop_active_fbps(struct gf100_gr *gr) 128 { 129 struct nvkm_device *device = gr->base.engine.subdev.device; 130 const u32 fbp_count = nvkm_rd32(device, 0x12006c); 131 nvkm_mask(device, 0x408850, 0x0000000f, fbp_count); /* zrop */ 132 nvkm_mask(device, 0x408958, 0x0000000f, fbp_count); /* crop */ 133 } 134 135 static u8 136 gm200_gr_tile_map_6_24[] = { 137 0, 1, 2, 3, 4, 5, 3, 4, 5, 0, 1, 2, 0, 1, 2, 3, 4, 5, 3, 4, 5, 0, 1, 2, 138 }; 139 140 static u8 141 gm200_gr_tile_map_4_16[] = { 142 0, 1, 2, 3, 2, 3, 0, 1, 3, 0, 1, 2, 1, 2, 3, 0, 143 }; 144 145 static u8 146 gm200_gr_tile_map_2_8[] = { 147 0, 1, 1, 0, 0, 1, 1, 0, 148 }; 149 150 void 151 gm200_gr_oneinit_sm_id(struct gf100_gr *gr) 152 { 153 /*XXX: There's a different algorithm here I've not yet figured out. */ 154 gf100_gr_oneinit_sm_id(gr); 155 } 156 157 void 158 gm200_gr_oneinit_tiles(struct gf100_gr *gr) 159 { 160 /*XXX: Not sure what this is about. The algorithm from NVGPU 161 * seems to work for all boards I tried from earlier (and 162 * later) GPUs except in these specific configurations. 163 * 164 * Let's just hardcode them for now. 165 */ 166 if (gr->gpc_nr == 2 && gr->tpc_total == 8) { 167 memcpy(gr->tile, gm200_gr_tile_map_2_8, gr->tpc_total); 168 gr->screen_tile_row_offset = 1; 169 } else 170 if (gr->gpc_nr == 4 && gr->tpc_total == 16) { 171 memcpy(gr->tile, gm200_gr_tile_map_4_16, gr->tpc_total); 172 gr->screen_tile_row_offset = 4; 173 } else 174 if (gr->gpc_nr == 6 && gr->tpc_total == 24) { 175 memcpy(gr->tile, gm200_gr_tile_map_6_24, gr->tpc_total); 176 gr->screen_tile_row_offset = 5; 177 } else { 178 gf100_gr_oneinit_tiles(gr); 179 } 180 } 181 182 static const struct gf100_gr_func 183 gm200_gr = { 184 .oneinit_tiles = gm200_gr_oneinit_tiles, 185 .oneinit_sm_id = gm200_gr_oneinit_sm_id, 186 .init = gf100_gr_init, 187 .init_gpc_mmu = gm200_gr_init_gpc_mmu, 188 .init_bios = gm107_gr_init_bios, 189 .init_vsc_stream_master = gk104_gr_init_vsc_stream_master, 190 .init_zcull = gf117_gr_init_zcull, 191 .init_num_active_ltcs = gm200_gr_init_num_active_ltcs, 192 .init_rop_active_fbps = gm200_gr_init_rop_active_fbps, 193 .init_fecs_exceptions = gf100_gr_init_fecs_exceptions, 194 .init_ds_hww_esr_2 = gm200_gr_init_ds_hww_esr_2, 195 .init_sked_hww_esr = gk104_gr_init_sked_hww_esr, 196 .init_419cc0 = gf100_gr_init_419cc0, 197 .init_ppc_exceptions = gk104_gr_init_ppc_exceptions, 198 .init_tex_hww_esr = gf100_gr_init_tex_hww_esr, 199 .init_504430 = gm107_gr_init_504430, 200 .init_shader_exceptions = gm107_gr_init_shader_exceptions, 201 .init_400054 = gm107_gr_init_400054, 202 .trap_mp = gf100_gr_trap_mp, 203 .rops = gm200_gr_rops, 204 .tpc_nr = 4, 205 .ppc_nr = 2, 206 .grctx = &gm200_grctx, 207 .zbc = &gf100_gr_zbc, 208 .sclass = { 209 { -1, -1, FERMI_TWOD_A }, 210 { -1, -1, KEPLER_INLINE_TO_MEMORY_B }, 211 { -1, -1, MAXWELL_B, &gf100_fermi }, 212 { -1, -1, MAXWELL_COMPUTE_B }, 213 {} 214 } 215 }; 216 217 int 218 gm200_gr_load(struct gf100_gr *gr, int ver, const struct gf100_gr_fwif *fwif) 219 { 220 int ret; 221 222 ret = nvkm_acr_lsfw_load_bl_inst_data_sig(&gr->base.engine.subdev, 223 &gr->fecs.falcon, 224 NVKM_ACR_LSF_FECS, 225 "gr/fecs_", ver, fwif->fecs); 226 if (ret) 227 return ret; 228 229 ret = nvkm_acr_lsfw_load_bl_inst_data_sig(&gr->base.engine.subdev, 230 &gr->gpccs.falcon, 231 NVKM_ACR_LSF_GPCCS, 232 "gr/gpccs_", ver, 233 fwif->gpccs); 234 if (ret) 235 return ret; 236 237 gr->firmware = true; 238 239 return gk20a_gr_load_sw(gr, "gr/", ver); 240 } 241 242 MODULE_FIRMWARE("nvidia/gm200/gr/fecs_bl.bin"); 243 MODULE_FIRMWARE("nvidia/gm200/gr/fecs_inst.bin"); 244 MODULE_FIRMWARE("nvidia/gm200/gr/fecs_data.bin"); 245 MODULE_FIRMWARE("nvidia/gm200/gr/fecs_sig.bin"); 246 MODULE_FIRMWARE("nvidia/gm200/gr/gpccs_bl.bin"); 247 MODULE_FIRMWARE("nvidia/gm200/gr/gpccs_inst.bin"); 248 MODULE_FIRMWARE("nvidia/gm200/gr/gpccs_data.bin"); 249 MODULE_FIRMWARE("nvidia/gm200/gr/gpccs_sig.bin"); 250 MODULE_FIRMWARE("nvidia/gm200/gr/sw_ctx.bin"); 251 MODULE_FIRMWARE("nvidia/gm200/gr/sw_nonctx.bin"); 252 MODULE_FIRMWARE("nvidia/gm200/gr/sw_bundle_init.bin"); 253 MODULE_FIRMWARE("nvidia/gm200/gr/sw_method_init.bin"); 254 255 MODULE_FIRMWARE("nvidia/gm204/gr/fecs_bl.bin"); 256 MODULE_FIRMWARE("nvidia/gm204/gr/fecs_inst.bin"); 257 MODULE_FIRMWARE("nvidia/gm204/gr/fecs_data.bin"); 258 MODULE_FIRMWARE("nvidia/gm204/gr/fecs_sig.bin"); 259 MODULE_FIRMWARE("nvidia/gm204/gr/gpccs_bl.bin"); 260 MODULE_FIRMWARE("nvidia/gm204/gr/gpccs_inst.bin"); 261 MODULE_FIRMWARE("nvidia/gm204/gr/gpccs_data.bin"); 262 MODULE_FIRMWARE("nvidia/gm204/gr/gpccs_sig.bin"); 263 MODULE_FIRMWARE("nvidia/gm204/gr/sw_ctx.bin"); 264 MODULE_FIRMWARE("nvidia/gm204/gr/sw_nonctx.bin"); 265 MODULE_FIRMWARE("nvidia/gm204/gr/sw_bundle_init.bin"); 266 MODULE_FIRMWARE("nvidia/gm204/gr/sw_method_init.bin"); 267 268 MODULE_FIRMWARE("nvidia/gm206/gr/fecs_bl.bin"); 269 MODULE_FIRMWARE("nvidia/gm206/gr/fecs_inst.bin"); 270 MODULE_FIRMWARE("nvidia/gm206/gr/fecs_data.bin"); 271 MODULE_FIRMWARE("nvidia/gm206/gr/fecs_sig.bin"); 272 MODULE_FIRMWARE("nvidia/gm206/gr/gpccs_bl.bin"); 273 MODULE_FIRMWARE("nvidia/gm206/gr/gpccs_inst.bin"); 274 MODULE_FIRMWARE("nvidia/gm206/gr/gpccs_data.bin"); 275 MODULE_FIRMWARE("nvidia/gm206/gr/gpccs_sig.bin"); 276 MODULE_FIRMWARE("nvidia/gm206/gr/sw_ctx.bin"); 277 MODULE_FIRMWARE("nvidia/gm206/gr/sw_nonctx.bin"); 278 MODULE_FIRMWARE("nvidia/gm206/gr/sw_bundle_init.bin"); 279 MODULE_FIRMWARE("nvidia/gm206/gr/sw_method_init.bin"); 280 281 static const struct gf100_gr_fwif 282 gm200_gr_fwif[] = { 283 { 0, gm200_gr_load, &gm200_gr, &gm200_gr_fecs_acr, &gm200_gr_gpccs_acr }, 284 {} 285 }; 286 287 int 288 gm200_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) 289 { 290 return gf100_gr_new_(gm200_gr_fwif, device, index, pgr); 291 } 292
Indexes created Sun Sep 28 07:09:56 GMT 2025