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      1 /*	$NetBSD: nouveau_nvkm_engine_gr_ctxgm200.c,v 1.2 2021/12/18 23:45:36 riastradh Exp $	*/
      2 
      3 /*
      4  * Copyright 2015 Red Hat Inc.
      5  *
      6  * Permission is hereby granted, free of charge, to any person obtaining a
      7  * copy of this software and associated documentation files (the "Software"),
      8  * to deal in the Software without restriction, including without limitation
      9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
     10  * and/or sell copies of the Software, and to permit persons to whom the
     11  * Software is furnished to do so, subject to the following conditions:
     12  *
     13  * The above copyright notice and this permission notice shall be included in
     14  * all copies or substantial portions of the Software.
     15  *
     16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     22  * OTHER DEALINGS IN THE SOFTWARE.
     23  *
     24  * Authors: Ben Skeggs <bskeggs (at) redhat.com>
     25  */
     26 #include <sys/cdefs.h>
     27 __KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_engine_gr_ctxgm200.c,v 1.2 2021/12/18 23:45:36 riastradh Exp $");
     28 
     29 #include "ctxgf100.h"
     30 
     31 /*******************************************************************************
     32  * PGRAPH context implementation
     33  ******************************************************************************/
     34 
     35 void
     36 gm200_grctx_generate_r419a3c(struct gf100_gr *gr)
     37 {
     38 	struct nvkm_device *device = gr->base.engine.subdev.device;
     39 	nvkm_mask(device, 0x419a3c, 0x00000014, 0x00000000);
     40 }
     41 
     42 static void
     43 gm200_grctx_generate_r418e94(struct gf100_gr *gr)
     44 {
     45 	struct nvkm_device *device = gr->base.engine.subdev.device;
     46 	nvkm_mask(device, 0x418e94, 0xffffffff, 0xc4230000);
     47 	nvkm_mask(device, 0x418e4c, 0xffffffff, 0x70000000);
     48 }
     49 
     50 void
     51 gm200_grctx_generate_smid_config(struct gf100_gr *gr)
     52 {
     53 	struct nvkm_device *device = gr->base.engine.subdev.device;
     54 	const u32 dist_nr = DIV_ROUND_UP(gr->tpc_total, 4);
     55 	u32 dist[TPC_MAX / 4] = {};
     56 	u32 gpcs[GPC_MAX] = {};
     57 	u8  sm, i;
     58 
     59 	for (sm = 0; sm < gr->sm_nr; sm++) {
     60 		const u8 gpc = gr->sm[sm].gpc;
     61 		const u8 tpc = gr->sm[sm].tpc;
     62 		dist[sm / 4] |= ((gpc << 4) | tpc) << ((sm % 4) * 8);
     63 		gpcs[gpc] |= sm << (tpc * 8);
     64 	}
     65 
     66 	for (i = 0; i < dist_nr; i++)
     67 		nvkm_wr32(device, 0x405b60 + (i * 4), dist[i]);
     68 	for (i = 0; i < gr->gpc_nr; i++)
     69 		nvkm_wr32(device, 0x405ba0 + (i * 4), gpcs[i]);
     70 }
     71 
     72 void
     73 gm200_grctx_generate_tpc_mask(struct gf100_gr *gr)
     74 {
     75 	u32 tmp, i;
     76 	for (tmp = 0, i = 0; i < gr->gpc_nr; i++)
     77 		tmp |= ((1 << gr->tpc_nr[i]) - 1) << (i * gr->func->tpc_nr);
     78 	nvkm_wr32(gr->base.engine.subdev.device, 0x4041c4, tmp);
     79 }
     80 
     81 void
     82 gm200_grctx_generate_r406500(struct gf100_gr *gr)
     83 {
     84 	nvkm_wr32(gr->base.engine.subdev.device, 0x406500, 0x00000000);
     85 }
     86 
     87 void
     88 gm200_grctx_generate_dist_skip_table(struct gf100_gr *gr)
     89 {
     90 	struct nvkm_device *device = gr->base.engine.subdev.device;
     91 	u32 data[8] = {};
     92 	int gpc, ppc, i;
     93 
     94 	for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
     95 		for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++) {
     96 			u8 ppc_tpcs = gr->ppc_tpc_nr[gpc][ppc];
     97 			u8 ppc_tpcm = gr->ppc_tpc_mask[gpc][ppc];
     98 			while (ppc_tpcs-- > gr->ppc_tpc_min)
     99 				ppc_tpcm &= ppc_tpcm - 1;
    100 			ppc_tpcm ^= gr->ppc_tpc_mask[gpc][ppc];
    101 			((u8 *)data)[gpc] |= ppc_tpcm;
    102 		}
    103 	}
    104 
    105 	for (i = 0; i < ARRAY_SIZE(data); i++)
    106 		nvkm_wr32(device, 0x4064d0 + (i * 0x04), data[i]);
    107 }
    108 
    109 const struct gf100_grctx_func
    110 gm200_grctx = {
    111 	.main  = gf100_grctx_generate_main,
    112 	.unkn  = gk104_grctx_generate_unkn,
    113 	.bundle = gm107_grctx_generate_bundle,
    114 	.bundle_size = 0x3000,
    115 	.bundle_min_gpm_fifo_depth = 0x180,
    116 	.bundle_token_limit = 0x780,
    117 	.pagepool = gm107_grctx_generate_pagepool,
    118 	.pagepool_size = 0x20000,
    119 	.attrib = gm107_grctx_generate_attrib,
    120 	.attrib_nr_max = 0x600,
    121 	.attrib_nr = 0x400,
    122 	.alpha_nr_max = 0x1800,
    123 	.alpha_nr = 0x1000,
    124 	.sm_id = gm107_grctx_generate_sm_id,
    125 	.rop_mapping = gf117_grctx_generate_rop_mapping,
    126 	.dist_skip_table = gm200_grctx_generate_dist_skip_table,
    127 	.r406500 = gm200_grctx_generate_r406500,
    128 	.gpc_tpc_nr = gk104_grctx_generate_gpc_tpc_nr,
    129 	.tpc_mask = gm200_grctx_generate_tpc_mask,
    130 	.smid_config = gm200_grctx_generate_smid_config,
    131 	.r418e94 = gm200_grctx_generate_r418e94,
    132 	.r419a3c = gm200_grctx_generate_r419a3c,
    133 };
    134