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      1 /*	$NetBSD: nouveau_nvkm_engine_gr_ctxgm20b.c,v 1.3 2021/12/18 23:45:36 riastradh Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
      5  *
      6  * Permission is hereby granted, free of charge, to any person obtaining a
      7  * copy of this software and associated documentation files (the "Software"),
      8  * to deal in the Software without restriction, including without limitation
      9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
     10  * and/or sell copies of the Software, and to permit persons to whom the
     11  * Software is furnished to do so, subject to the following conditions:
     12  *
     13  * The above copyright notice and this permission notice shall be included in
     14  * all copies or substantial portions of the Software.
     15  *
     16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
     20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
     21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
     22  * DEALINGS IN THE SOFTWARE.
     23  */
     24 #include <sys/cdefs.h>
     25 __KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_engine_gr_ctxgm20b.c,v 1.3 2021/12/18 23:45:36 riastradh Exp $");
     26 
     27 #include "ctxgf100.h"
     28 
     29 static void
     30 gm20b_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
     31 {
     32 	struct nvkm_device *device = gr->base.engine.subdev.device;
     33 	const struct gf100_grctx_func *grctx = gr->func->grctx;
     34 	u32 idle_timeout;
     35 	int i, tmp;
     36 
     37 	gf100_gr_mmio(gr, gr->sw_ctx);
     38 
     39 	gf100_gr_wait_idle(gr);
     40 
     41 	idle_timeout = nvkm_mask(device, 0x404154, 0xffffffff, 0x00000000);
     42 
     43 	grctx->attrib(info);
     44 
     45 	grctx->unkn(gr);
     46 
     47 	gf100_grctx_generate_floorsweep(gr);
     48 
     49 	for (i = 0; i < 8; i++)
     50 		nvkm_wr32(device, 0x4064d0 + (i * 0x04), 0x00000000);
     51 
     52 	nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr);
     53 
     54 	nvkm_wr32(device, 0x408908, nvkm_rd32(device, 0x410108) | 0x80000000);
     55 
     56 	for (tmp = 0, i = 0; i < gr->gpc_nr; i++)
     57 		tmp |= ((1 << gr->tpc_nr[i]) - 1) << (i * 4);
     58 	nvkm_wr32(device, 0x4041c4, tmp);
     59 
     60 	gm200_grctx_generate_smid_config(gr);
     61 
     62 	gf100_gr_wait_idle(gr);
     63 
     64 	nvkm_wr32(device, 0x404154, idle_timeout);
     65 	gf100_gr_wait_idle(gr);
     66 
     67 	gf100_gr_mthd(gr, gr->method);
     68 	gf100_gr_wait_idle(gr);
     69 
     70 	gf100_gr_icmd(gr, gr->bundle);
     71 	grctx->pagepool(info);
     72 	grctx->bundle(info);
     73 }
     74 
     75 const struct gf100_grctx_func
     76 gm20b_grctx = {
     77 	.main  = gm20b_grctx_generate_main,
     78 	.unkn  = gk104_grctx_generate_unkn,
     79 	.bundle = gm107_grctx_generate_bundle,
     80 	.bundle_size = 0x1800,
     81 	.bundle_min_gpm_fifo_depth = 0x182,
     82 	.bundle_token_limit = 0x1c0,
     83 	.pagepool = gm107_grctx_generate_pagepool,
     84 	.pagepool_size = 0x8000,
     85 	.attrib = gm107_grctx_generate_attrib,
     86 	.attrib_nr_max = 0x600,
     87 	.attrib_nr = 0x400,
     88 	.alpha_nr_max = 0xc00,
     89 	.alpha_nr = 0x800,
     90 	.sm_id = gm107_grctx_generate_sm_id,
     91 	.rop_mapping = gf117_grctx_generate_rop_mapping,
     92 };
     93