1 /* $NetBSD: nouveau_nvkm_subdev_acr_gp102.c,v 1.3 2021/12/19 10:51:58 riastradh Exp $ */ 2 3 /* 4 * Copyright 2019 Red Hat Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_subdev_acr_gp102.c,v 1.3 2021/12/19 10:51:58 riastradh Exp $"); 26 27 #include "priv.h" 28 29 #include <core/firmware.h> 30 #include <core/memory.h> 31 #include <subdev/mmu.h> 32 #include <engine/sec2.h> 33 34 #include <nvfw/acr.h> 35 #include <nvfw/flcn.h> 36 37 #include <linux/nbsd-namespace.h> 38 39 void 40 gp102_acr_wpr_patch(struct nvkm_acr *acr, s64 adjust) 41 { 42 struct wpr_header_v1 hdr; 43 struct lsb_header_v1 lsb; 44 struct nvkm_acr_lsfw *lsfw; 45 u32 offset = 0; 46 47 do { 48 nvkm_robj(acr->wpr, offset, &hdr, sizeof(hdr)); 49 wpr_header_v1_dump(&acr->subdev, &hdr); 50 51 list_for_each_entry(lsfw, &acr->lsfw, head) { 52 if (lsfw->id != hdr.falcon_id) 53 continue; 54 55 nvkm_robj(acr->wpr, hdr.lsb_offset, &lsb, sizeof(lsb)); 56 lsb_header_v1_dump(&acr->subdev, &lsb); 57 58 lsfw->func->bld_patch(acr, lsb.tail.bl_data_off, adjust); 59 break; 60 } 61 62 offset += sizeof(hdr); 63 } while (hdr.falcon_id != WPR_HEADER_V1_FALCON_ID_INVALID); 64 } 65 66 int 67 gp102_acr_wpr_build_lsb(struct nvkm_acr *acr, struct nvkm_acr_lsfw *lsfw) 68 { 69 struct lsb_header_v1 hdr; 70 71 if (WARN_ON(lsfw->sig->size != sizeof(hdr.signature))) 72 return -EINVAL; 73 74 memcpy(&hdr.signature, lsfw->sig->data, lsfw->sig->size); 75 gm200_acr_wpr_build_lsb_tail(lsfw, &hdr.tail); 76 77 nvkm_wobj(acr->wpr, lsfw->offset.lsb, &hdr, sizeof(hdr)); 78 return 0; 79 } 80 81 int 82 gp102_acr_wpr_build(struct nvkm_acr *acr, struct nvkm_acr_lsf *rtos) 83 { 84 struct nvkm_acr_lsfw *lsfw; 85 u32 offset = 0; 86 int ret; 87 88 /* Fill per-LSF structures. */ 89 list_for_each_entry(lsfw, &acr->lsfw, head) { 90 struct lsf_signature_v1 *sig = (void *)lsfw->sig->data; 91 struct wpr_header_v1 hdr = { 92 .falcon_id = lsfw->id, 93 .lsb_offset = lsfw->offset.lsb, 94 .bootstrap_owner = NVKM_ACR_LSF_SEC2, 95 .lazy_bootstrap = rtos && lsfw->id != rtos->id, 96 .bin_version = sig->version, 97 .status = WPR_HEADER_V1_STATUS_COPY, 98 }; 99 100 /* Write WPR header. */ 101 nvkm_wobj(acr->wpr, offset, &hdr, sizeof(hdr)); 102 offset += sizeof(hdr); 103 104 /* Write LSB header. */ 105 ret = gp102_acr_wpr_build_lsb(acr, lsfw); 106 if (ret) 107 return ret; 108 109 /* Write ucode image. */ 110 nvkm_wobj(acr->wpr, lsfw->offset.img, 111 lsfw->img.data, 112 lsfw->img.size); 113 114 /* Write bootloader data. */ 115 lsfw->func->bld_write(acr, lsfw->offset.bld, lsfw); 116 } 117 118 /* Finalise WPR. */ 119 nvkm_wo32(acr->wpr, offset, WPR_HEADER_V1_FALCON_ID_INVALID); 120 return 0; 121 } 122 123 int 124 gp102_acr_wpr_alloc(struct nvkm_acr *acr, u32 wpr_size) 125 { 126 int ret = nvkm_memory_new(acr->subdev.device, NVKM_MEM_TARGET_INST, 127 ALIGN(wpr_size, 0x40000) << 1, 0x40000, true, 128 &acr->wpr); 129 if (ret) 130 return ret; 131 132 acr->shadow_start = nvkm_memory_addr(acr->wpr); 133 acr->wpr_start = acr->shadow_start + (nvkm_memory_size(acr->wpr) >> 1); 134 acr->wpr_end = acr->wpr_start + (nvkm_memory_size(acr->wpr) >> 1); 135 return 0; 136 } 137 138 u32 139 gp102_acr_wpr_layout(struct nvkm_acr *acr) 140 { 141 struct nvkm_acr_lsfw *lsfw; 142 u32 wpr = 0; 143 144 wpr += 11 /* MAX_LSF */ * sizeof(struct wpr_header_v1); 145 wpr = ALIGN(wpr, 256); 146 147 wpr += 0x100; /* Shared sub-WPR headers. */ 148 149 list_for_each_entry(lsfw, &acr->lsfw, head) { 150 wpr = ALIGN(wpr, 256); 151 lsfw->offset.lsb = wpr; 152 wpr += sizeof(struct lsb_header_v1); 153 154 wpr = ALIGN(wpr, 4096); 155 lsfw->offset.img = wpr; 156 wpr += lsfw->img.size; 157 158 wpr = ALIGN(wpr, 256); 159 lsfw->offset.bld = wpr; 160 lsfw->bl_data_size = ALIGN(lsfw->func->bld_size, 256); 161 wpr += lsfw->bl_data_size; 162 } 163 164 return wpr; 165 } 166 167 int 168 gp102_acr_wpr_parse(struct nvkm_acr *acr) 169 { 170 const struct wpr_header_v1 *hdr = (void *)acr->wpr_fw->data; 171 172 while (hdr->falcon_id != WPR_HEADER_V1_FALCON_ID_INVALID) { 173 wpr_header_v1_dump(&acr->subdev, hdr); 174 if (!nvkm_acr_lsfw_add(NULL, acr, NULL, (hdr++)->falcon_id)) 175 return -ENOMEM; 176 } 177 178 return 0; 179 } 180 181 MODULE_FIRMWARE("nvidia/gp102/acr/unload_bl.bin"); 182 MODULE_FIRMWARE("nvidia/gp102/acr/ucode_unload.bin"); 183 184 MODULE_FIRMWARE("nvidia/gp104/acr/unload_bl.bin"); 185 MODULE_FIRMWARE("nvidia/gp104/acr/ucode_unload.bin"); 186 187 MODULE_FIRMWARE("nvidia/gp106/acr/unload_bl.bin"); 188 MODULE_FIRMWARE("nvidia/gp106/acr/ucode_unload.bin"); 189 190 MODULE_FIRMWARE("nvidia/gp107/acr/unload_bl.bin"); 191 MODULE_FIRMWARE("nvidia/gp107/acr/ucode_unload.bin"); 192 193 static const struct nvkm_acr_hsf_fwif 194 gp102_acr_unload_fwif[] = { 195 { 0, nvkm_acr_hsfw_load, &gm200_acr_unload_0 }, 196 {} 197 }; 198 199 int 200 gp102_acr_load_load(struct nvkm_acr *acr, struct nvkm_acr_hsfw *hsfw) 201 { 202 struct flcn_acr_desc_v1 *desc = (void *)&hsfw->image[hsfw->data_addr]; 203 204 desc->wpr_region_id = 1; 205 desc->regions.no_regions = 2; 206 desc->regions.region_props[0].start_addr = acr->wpr_start >> 8; 207 desc->regions.region_props[0].end_addr = acr->wpr_end >> 8; 208 desc->regions.region_props[0].region_id = 1; 209 desc->regions.region_props[0].read_mask = 0xf; 210 desc->regions.region_props[0].write_mask = 0xc; 211 desc->regions.region_props[0].client_mask = 0x2; 212 desc->regions.region_props[0].shadow_mem_start_addr = 213 acr->shadow_start >> 8; 214 flcn_acr_desc_v1_dump(&acr->subdev, desc); 215 216 return gm200_acr_hsfw_load(acr, hsfw, 217 &acr->subdev.device->sec2->falcon); 218 } 219 220 static const struct nvkm_acr_hsf_func 221 gp102_acr_load_0 = { 222 .load = gp102_acr_load_load, 223 .boot = gm200_acr_load_boot, 224 .bld = gm200_acr_hsfw_bld, 225 }; 226 227 MODULE_FIRMWARE("nvidia/gp102/acr/bl.bin"); 228 MODULE_FIRMWARE("nvidia/gp102/acr/ucode_load.bin"); 229 230 MODULE_FIRMWARE("nvidia/gp104/acr/bl.bin"); 231 MODULE_FIRMWARE("nvidia/gp104/acr/ucode_load.bin"); 232 233 MODULE_FIRMWARE("nvidia/gp106/acr/bl.bin"); 234 MODULE_FIRMWARE("nvidia/gp106/acr/ucode_load.bin"); 235 236 MODULE_FIRMWARE("nvidia/gp107/acr/bl.bin"); 237 MODULE_FIRMWARE("nvidia/gp107/acr/ucode_load.bin"); 238 239 static const struct nvkm_acr_hsf_fwif 240 gp102_acr_load_fwif[] = { 241 { 0, nvkm_acr_hsfw_load, &gp102_acr_load_0 }, 242 {} 243 }; 244 245 static const struct nvkm_acr_func 246 gp102_acr = { 247 .load = gp102_acr_load_fwif, 248 .unload = gp102_acr_unload_fwif, 249 .wpr_parse = gp102_acr_wpr_parse, 250 .wpr_layout = gp102_acr_wpr_layout, 251 .wpr_alloc = gp102_acr_wpr_alloc, 252 .wpr_build = gp102_acr_wpr_build, 253 .wpr_patch = gp102_acr_wpr_patch, 254 .wpr_check = gm200_acr_wpr_check, 255 .init = gm200_acr_init, 256 }; 257 258 int 259 gp102_acr_load(struct nvkm_acr *acr, int ver, const struct nvkm_acr_fwif *fwif) 260 { 261 struct nvkm_subdev *subdev = &acr->subdev; 262 const struct nvkm_acr_hsf_fwif *hsfwif; 263 264 hsfwif = nvkm_firmware_load(subdev, fwif->func->load, "AcrLoad", 265 acr, "acr/bl", "acr/ucode_load", "load"); 266 if (IS_ERR(hsfwif)) 267 return PTR_ERR(hsfwif); 268 269 hsfwif = nvkm_firmware_load(subdev, fwif->func->unload, "AcrUnload", 270 acr, "acr/unload_bl", "acr/ucode_unload", 271 "unload"); 272 if (IS_ERR(hsfwif)) 273 return PTR_ERR(hsfwif); 274 275 return 0; 276 } 277 278 static const struct nvkm_acr_fwif 279 gp102_acr_fwif[] = { 280 { 0, gp102_acr_load, &gp102_acr }, 281 {} 282 }; 283 284 int 285 gp102_acr_new(struct nvkm_device *device, int index, struct nvkm_acr **pacr) 286 { 287 return nvkm_acr_new_(gp102_acr_fwif, device, index, pacr); 288 } 289
Indexes created Wed Sep 24 05:09:52 GMT 2025