1 /* $NetBSD: nouveau_nvkm_engine_gr_gp102.c,v 1.2 2021/12/18 23:45:36 riastradh Exp $ */ 2 3 /* 4 * Copyright 2016 Red Hat Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Ben Skeggs <bskeggs (at) redhat.com> 25 */ 26 #include <sys/cdefs.h> 27 __KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_engine_gr_gp102.c,v 1.2 2021/12/18 23:45:36 riastradh Exp $"); 28 29 #include "gf100.h" 30 #include "ctxgf100.h" 31 32 #include <nvif/class.h> 33 34 static void 35 gp102_gr_zbc_clear_stencil(struct gf100_gr *gr, int zbc) 36 { 37 struct nvkm_device *device = gr->base.engine.subdev.device; 38 const int znum = zbc - 1; 39 const u32 zoff = znum * 4; 40 41 if (gr->zbc_stencil[zbc].format) 42 nvkm_wr32(device, 0x41815c + zoff, gr->zbc_stencil[zbc].ds); 43 nvkm_mask(device, 0x418198 + ((znum / 4) * 4), 44 0x0000007f << ((znum % 4) * 7), 45 gr->zbc_stencil[zbc].format << ((znum % 4) * 7)); 46 } 47 48 static int 49 gp102_gr_zbc_stencil_get(struct gf100_gr *gr, int format, 50 const u32 ds, const u32 l2) 51 { 52 struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc; 53 int zbc = -ENOSPC, i; 54 55 for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) { 56 if (gr->zbc_stencil[i].format) { 57 if (gr->zbc_stencil[i].format != format) 58 continue; 59 if (gr->zbc_stencil[i].ds != ds) 60 continue; 61 if (gr->zbc_stencil[i].l2 != l2) { 62 WARN_ON(1); 63 return -EINVAL; 64 } 65 return i; 66 } else { 67 zbc = (zbc < 0) ? i : zbc; 68 } 69 } 70 71 if (zbc < 0) 72 return zbc; 73 74 gr->zbc_stencil[zbc].format = format; 75 gr->zbc_stencil[zbc].ds = ds; 76 gr->zbc_stencil[zbc].l2 = l2; 77 nvkm_ltc_zbc_stencil_get(ltc, zbc, l2); 78 gr->func->zbc->clear_stencil(gr, zbc); 79 return zbc; 80 } 81 82 const struct gf100_gr_func_zbc 83 gp102_gr_zbc = { 84 .clear_color = gp100_gr_zbc_clear_color, 85 .clear_depth = gp100_gr_zbc_clear_depth, 86 .stencil_get = gp102_gr_zbc_stencil_get, 87 .clear_stencil = gp102_gr_zbc_clear_stencil, 88 }; 89 90 void 91 gp102_gr_init_swdx_pes_mask(struct gf100_gr *gr) 92 { 93 struct nvkm_device *device = gr->base.engine.subdev.device; 94 u32 mask = 0, data, gpc; 95 96 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { 97 data = nvkm_rd32(device, GPC_UNIT(gpc, 0x0c50)) & 0x0000000f; 98 mask |= data << (gpc * 4); 99 } 100 101 nvkm_wr32(device, 0x4181d0, mask); 102 } 103 104 static const struct gf100_gr_func 105 gp102_gr = { 106 .oneinit_tiles = gm200_gr_oneinit_tiles, 107 .oneinit_sm_id = gm200_gr_oneinit_sm_id, 108 .init = gf100_gr_init, 109 .init_gpc_mmu = gm200_gr_init_gpc_mmu, 110 .init_vsc_stream_master = gk104_gr_init_vsc_stream_master, 111 .init_zcull = gf117_gr_init_zcull, 112 .init_num_active_ltcs = gm200_gr_init_num_active_ltcs, 113 .init_rop_active_fbps = gp100_gr_init_rop_active_fbps, 114 .init_swdx_pes_mask = gp102_gr_init_swdx_pes_mask, 115 .init_fecs_exceptions = gp100_gr_init_fecs_exceptions, 116 .init_ds_hww_esr_2 = gm200_gr_init_ds_hww_esr_2, 117 .init_sked_hww_esr = gk104_gr_init_sked_hww_esr, 118 .init_419cc0 = gf100_gr_init_419cc0, 119 .init_ppc_exceptions = gk104_gr_init_ppc_exceptions, 120 .init_tex_hww_esr = gf100_gr_init_tex_hww_esr, 121 .init_504430 = gm107_gr_init_504430, 122 .init_shader_exceptions = gp100_gr_init_shader_exceptions, 123 .trap_mp = gf100_gr_trap_mp, 124 .rops = gm200_gr_rops, 125 .gpc_nr = 6, 126 .tpc_nr = 5, 127 .ppc_nr = 3, 128 .grctx = &gp102_grctx, 129 .zbc = &gp102_gr_zbc, 130 .sclass = { 131 { -1, -1, FERMI_TWOD_A }, 132 { -1, -1, KEPLER_INLINE_TO_MEMORY_B }, 133 { -1, -1, PASCAL_B, &gf100_fermi }, 134 { -1, -1, PASCAL_COMPUTE_B }, 135 {} 136 } 137 }; 138 139 MODULE_FIRMWARE("nvidia/gp102/gr/fecs_bl.bin"); 140 MODULE_FIRMWARE("nvidia/gp102/gr/fecs_inst.bin"); 141 MODULE_FIRMWARE("nvidia/gp102/gr/fecs_data.bin"); 142 MODULE_FIRMWARE("nvidia/gp102/gr/fecs_sig.bin"); 143 MODULE_FIRMWARE("nvidia/gp102/gr/gpccs_bl.bin"); 144 MODULE_FIRMWARE("nvidia/gp102/gr/gpccs_inst.bin"); 145 MODULE_FIRMWARE("nvidia/gp102/gr/gpccs_data.bin"); 146 MODULE_FIRMWARE("nvidia/gp102/gr/gpccs_sig.bin"); 147 MODULE_FIRMWARE("nvidia/gp102/gr/sw_ctx.bin"); 148 MODULE_FIRMWARE("nvidia/gp102/gr/sw_nonctx.bin"); 149 MODULE_FIRMWARE("nvidia/gp102/gr/sw_bundle_init.bin"); 150 MODULE_FIRMWARE("nvidia/gp102/gr/sw_method_init.bin"); 151 152 static const struct gf100_gr_fwif 153 gp102_gr_fwif[] = { 154 { 0, gm200_gr_load, &gp102_gr, &gm200_gr_fecs_acr, &gm200_gr_gpccs_acr }, 155 {} 156 }; 157 158 int 159 gp102_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) 160 { 161 return gf100_gr_new_(gp102_gr_fwif, device, index, pgr); 162 } 163
Indexes created Wed Sep 24 15:09:51 GMT 2025