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      1 /*	$NetBSD: nouveau_nvkm_engine_gr_ctxgp102.c,v 1.2 2021/12/18 23:45:36 riastradh Exp $	*/
      2 
      3 /*
      4  * Copyright 2016 Red Hat Inc.
      5  *
      6  * Permission is hereby granted, free of charge, to any person obtaining a
      7  * copy of this software and associated documentation files (the "Software"),
      8  * to deal in the Software without restriction, including without limitation
      9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
     10  * and/or sell copies of the Software, and to permit persons to whom the
     11  * Software is furnished to do so, subject to the following conditions:
     12  *
     13  * The above copyright notice and this permission notice shall be included in
     14  * all copies or substantial portions of the Software.
     15  *
     16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     22  * OTHER DEALINGS IN THE SOFTWARE.
     23  *
     24  * Authors: Ben Skeggs <bskeggs (at) redhat.com>
     25  */
     26 #include <sys/cdefs.h>
     27 __KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_engine_gr_ctxgp102.c,v 1.2 2021/12/18 23:45:36 riastradh Exp $");
     28 
     29 #include "ctxgf100.h"
     30 
     31 #include <subdev/fb.h>
     32 
     33 /*******************************************************************************
     34  * PGRAPH context implementation
     35  ******************************************************************************/
     36 
     37 static void
     38 gp102_grctx_generate_r408840(struct gf100_gr *gr)
     39 {
     40 	struct nvkm_device *device = gr->base.engine.subdev.device;
     41 	nvkm_mask(device, 0x408840, 0x00000003, 0x00000000);
     42 }
     43 
     44 void
     45 gp102_grctx_generate_attrib(struct gf100_grctx *info)
     46 {
     47 	struct gf100_gr *gr = info->gr;
     48 	const struct gf100_grctx_func *grctx = gr->func->grctx;
     49 	const u32  alpha = grctx->alpha_nr;
     50 	const u32 attrib = grctx->attrib_nr;
     51 	const u32   gfxp = grctx->gfxp_nr;
     52 	const int s = 12;
     53 	const int max_batches = 0xffff;
     54 	u32 size = grctx->alpha_nr_max * gr->tpc_total;
     55 	u32 ao = 0;
     56 	u32 bo = ao + size;
     57 	int gpc, ppc, b, n = 0;
     58 
     59 	for (gpc = 0; gpc < gr->gpc_nr; gpc++)
     60 		size += grctx->gfxp_nr * gr->ppc_nr[gpc] * gr->ppc_tpc_max;
     61 	size = ((size * 0x20) + 128) & ~127;
     62 	b = mmio_vram(info, size, (1 << s), false);
     63 
     64 	mmio_refn(info, 0x418810, 0x80000000, s, b);
     65 	mmio_refn(info, 0x419848, 0x10000000, s, b);
     66 	mmio_refn(info, 0x419c2c, 0x10000000, s, b);
     67 	mmio_refn(info, 0x419b00, 0x00000000, s, b);
     68 	mmio_wr32(info, 0x419b04, 0x80000000 | size >> 7);
     69 	mmio_wr32(info, 0x405830, attrib);
     70 	mmio_wr32(info, 0x40585c, alpha);
     71 	mmio_wr32(info, 0x4064c4, ((alpha / 4) << 16) | max_batches);
     72 
     73 	for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
     74 		for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++, n++) {
     75 			const u32 as =  alpha * gr->ppc_tpc_nr[gpc][ppc];
     76 			const u32 bs = attrib * gr->ppc_tpc_max;
     77 			const u32 gs =   gfxp * gr->ppc_tpc_max;
     78 			const u32 u = 0x418ea0 + (n * 0x04);
     79 			const u32 o = PPC_UNIT(gpc, ppc, 0);
     80 			const u32 p = GPC_UNIT(gpc, 0xc44 + (ppc * 4));
     81 			if (!(gr->ppc_mask[gpc] & (1 << ppc)))
     82 				continue;
     83 			mmio_wr32(info, o + 0xc0, gs);
     84 			mmio_wr32(info, p, bs);
     85 			mmio_wr32(info, o + 0xf4, bo);
     86 			mmio_wr32(info, o + 0xf0, bs);
     87 			bo += gs;
     88 			mmio_wr32(info, o + 0xe4, as);
     89 			mmio_wr32(info, o + 0xf8, ao);
     90 			ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc];
     91 			mmio_wr32(info, u, bs);
     92 		}
     93 	}
     94 
     95 	mmio_wr32(info, 0x4181e4, 0x00000100);
     96 	mmio_wr32(info, 0x41befc, 0x00000100);
     97 }
     98 
     99 const struct gf100_grctx_func
    100 gp102_grctx = {
    101 	.main = gf100_grctx_generate_main,
    102 	.unkn = gk104_grctx_generate_unkn,
    103 	.bundle = gm107_grctx_generate_bundle,
    104 	.bundle_size = 0x3000,
    105 	.bundle_min_gpm_fifo_depth = 0x180,
    106 	.bundle_token_limit = 0x900,
    107 	.pagepool = gp100_grctx_generate_pagepool,
    108 	.pagepool_size = 0x20000,
    109 	.attrib = gp102_grctx_generate_attrib,
    110 	.attrib_nr_max = 0x4b0,
    111 	.attrib_nr = 0x320,
    112 	.alpha_nr_max = 0xc00,
    113 	.alpha_nr = 0x800,
    114 	.gfxp_nr = 0xba8,
    115 	.sm_id = gm107_grctx_generate_sm_id,
    116 	.rop_mapping = gf117_grctx_generate_rop_mapping,
    117 	.dist_skip_table = gm200_grctx_generate_dist_skip_table,
    118 	.r406500 = gm200_grctx_generate_r406500,
    119 	.gpc_tpc_nr = gk104_grctx_generate_gpc_tpc_nr,
    120 	.tpc_mask = gm200_grctx_generate_tpc_mask,
    121 	.smid_config = gp100_grctx_generate_smid_config,
    122 	.r419a3c = gm200_grctx_generate_r419a3c,
    123 	.r408840 = gp102_grctx_generate_r408840,
    124 };
    125