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      1 /*	$NetBSD: nouveau_nvkm_engine_gr_gp108.c,v 1.2 2021/12/18 23:45:36 riastradh Exp $	*/
      2 
      3 /*
      4  * Copyright 2019 Red Hat Inc.
      5  *
      6  * Permission is hereby granted, free of charge, to any person obtaining a
      7  * copy of this software and associated documentation files (the "Software"),
      8  * to deal in the Software without restriction, including without limitation
      9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
     10  * and/or sell copies of the Software, and to permit persons to whom the
     11  * Software is furnished to do so, subject to the following conditions:
     12  *
     13  * The above copyright notice and this permission notice shall be included in
     14  * all copies or substantial portions of the Software.
     15  *
     16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     22  * OTHER DEALINGS IN THE SOFTWARE.
     23  */
     24 #include <sys/cdefs.h>
     25 __KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_engine_gr_gp108.c,v 1.2 2021/12/18 23:45:36 riastradh Exp $");
     26 
     27 #include "gf100.h"
     28 
     29 #include <subdev/acr.h>
     30 
     31 #include <nvfw/flcn.h>
     32 
     33 static void
     34 gp108_gr_acr_bld_patch(struct nvkm_acr *acr, u32 bld, s64 adjust)
     35 {
     36 	struct flcn_bl_dmem_desc_v2 hdr;
     37 	nvkm_robj(acr->wpr, bld, &hdr, sizeof(hdr));
     38 	hdr.code_dma_base = hdr.code_dma_base + adjust;
     39 	hdr.data_dma_base = hdr.data_dma_base + adjust;
     40 	nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr));
     41 	flcn_bl_dmem_desc_v2_dump(&acr->subdev, &hdr);
     42 }
     43 
     44 static void
     45 gp108_gr_acr_bld_write(struct nvkm_acr *acr, u32 bld,
     46 		       struct nvkm_acr_lsfw *lsfw)
     47 {
     48 	const u64 base = lsfw->offset.img + lsfw->app_start_offset;
     49 	const u64 code = base + lsfw->app_resident_code_offset;
     50 	const u64 data = base + lsfw->app_resident_data_offset;
     51 	const struct flcn_bl_dmem_desc_v2 hdr = {
     52 		.ctx_dma = FALCON_DMAIDX_UCODE,
     53 		.code_dma_base = code,
     54 		.non_sec_code_off = lsfw->app_resident_code_offset,
     55 		.non_sec_code_size = lsfw->app_resident_code_size,
     56 		.code_entry_point = lsfw->app_imem_entry,
     57 		.data_dma_base = data,
     58 		.data_size = lsfw->app_resident_data_size,
     59 	};
     60 
     61 	nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr));
     62 }
     63 
     64 const struct nvkm_acr_lsf_func
     65 gp108_gr_gpccs_acr = {
     66 	.flags = NVKM_ACR_LSF_FORCE_PRIV_LOAD,
     67 	.bld_size = sizeof(struct flcn_bl_dmem_desc_v2),
     68 	.bld_write = gp108_gr_acr_bld_write,
     69 	.bld_patch = gp108_gr_acr_bld_patch,
     70 };
     71 
     72 const struct nvkm_acr_lsf_func
     73 gp108_gr_fecs_acr = {
     74 	.bld_size = sizeof(struct flcn_bl_dmem_desc_v2),
     75 	.bld_write = gp108_gr_acr_bld_write,
     76 	.bld_patch = gp108_gr_acr_bld_patch,
     77 };
     78 
     79 MODULE_FIRMWARE("nvidia/gp108/gr/fecs_bl.bin");
     80 MODULE_FIRMWARE("nvidia/gp108/gr/fecs_inst.bin");
     81 MODULE_FIRMWARE("nvidia/gp108/gr/fecs_data.bin");
     82 MODULE_FIRMWARE("nvidia/gp108/gr/fecs_sig.bin");
     83 MODULE_FIRMWARE("nvidia/gp108/gr/gpccs_bl.bin");
     84 MODULE_FIRMWARE("nvidia/gp108/gr/gpccs_inst.bin");
     85 MODULE_FIRMWARE("nvidia/gp108/gr/gpccs_data.bin");
     86 MODULE_FIRMWARE("nvidia/gp108/gr/gpccs_sig.bin");
     87 MODULE_FIRMWARE("nvidia/gp108/gr/sw_ctx.bin");
     88 MODULE_FIRMWARE("nvidia/gp108/gr/sw_nonctx.bin");
     89 MODULE_FIRMWARE("nvidia/gp108/gr/sw_bundle_init.bin");
     90 MODULE_FIRMWARE("nvidia/gp108/gr/sw_method_init.bin");
     91 
     92 static const struct gf100_gr_fwif
     93 gp108_gr_fwif[] = {
     94 	{ 0, gm200_gr_load, &gp107_gr, &gp108_gr_fecs_acr, &gp108_gr_gpccs_acr },
     95 	{}
     96 };
     97 
     98 int
     99 gp108_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
    100 {
    101 	return gf100_gr_new_(gp108_gr_fwif, device, index, pgr);
    102 }
    103