1 /* $NetBSD: amdgpu_amdkfd.c,v 1.6 2021/12/19 10:59:01 riastradh Exp $ */ 2 3 /* 4 * Copyright 2014 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <sys/cdefs.h> 26 __KERNEL_RCSID(0, "$NetBSD: amdgpu_amdkfd.c,v 1.6 2021/12/19 10:59:01 riastradh Exp $"); 27 28 #include "amdgpu_amdkfd.h" 29 #include "amd_shared.h" 30 31 #include "amdgpu.h" 32 #include "amdgpu_gfx.h" 33 #include "amdgpu_dma_buf.h" 34 #include <linux/module.h> 35 #include <linux/dma-buf.h> 36 #include "amdgpu_xgmi.h" 37 38 static const unsigned int compute_vmid_bitmap = 0xFF00; 39 40 /* Total memory size in system memory and all GPU VRAM. Used to 41 * estimate worst case amount of memory to reserve for page tables 42 */ 43 uint64_t amdgpu_amdkfd_total_mem_size; 44 45 int amdgpu_amdkfd_init(void) 46 { 47 struct sysinfo si; 48 int ret; 49 50 si_meminfo(&si); 51 amdgpu_amdkfd_total_mem_size = si.totalram - si.totalhigh; 52 amdgpu_amdkfd_total_mem_size *= si.mem_unit; 53 54 #ifdef CONFIG_HSA_AMD 55 ret = kgd2kfd_init(); 56 amdgpu_amdkfd_gpuvm_init_mem_limits(); 57 #else 58 ret = -ENOENT; 59 #endif 60 61 return ret; 62 } 63 64 void amdgpu_amdkfd_fini(void) 65 { 66 kgd2kfd_exit(); 67 } 68 69 void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev) 70 { 71 bool vf = amdgpu_sriov_vf(adev); 72 73 adev->kfd.dev = kgd2kfd_probe((struct kgd_dev *)adev, 74 adev->pdev, adev->asic_type, vf); 75 76 if (adev->kfd.dev) 77 amdgpu_amdkfd_total_mem_size += adev->gmc.real_vram_size; 78 } 79 80 /** 81 * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to 82 * setup amdkfd 83 * 84 * @adev: amdgpu_device pointer 85 * @aperture_base: output returning doorbell aperture base physical address 86 * @aperture_size: output returning doorbell aperture size in bytes 87 * @start_offset: output returning # of doorbell bytes reserved for amdgpu. 88 * 89 * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up, 90 * takes doorbells required for its own rings and reports the setup to amdkfd. 91 * amdgpu reserved doorbells are at the start of the doorbell aperture. 92 */ 93 static void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, 94 phys_addr_t *aperture_base, 95 size_t *aperture_size, 96 size_t *start_offset) 97 { 98 /* 99 * The first num_doorbells are used by amdgpu. 100 * amdkfd takes whatever's left in the aperture. 101 */ 102 if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) { 103 *aperture_base = adev->doorbell.base; 104 *aperture_size = adev->doorbell.size; 105 *start_offset = adev->doorbell.num_doorbells * sizeof(u32); 106 } else { 107 *aperture_base = 0; 108 *aperture_size = 0; 109 *start_offset = 0; 110 } 111 } 112 113 void amdgpu_amdkfd_device_init(struct amdgpu_device *adev) 114 { 115 int i; 116 int last_valid_bit; 117 118 if (adev->kfd.dev) { 119 struct kgd2kfd_shared_resources gpu_resources = { 120 .compute_vmid_bitmap = compute_vmid_bitmap, 121 .num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec, 122 .num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe, 123 .gpuvm_size = min(adev->vm_manager.max_pfn 124 << AMDGPU_GPU_PAGE_SHIFT, 125 AMDGPU_GMC_HOLE_START), 126 .drm_render_minor = adev->ddev->render->index, 127 .sdma_doorbell_idx = adev->doorbell_index.sdma_engine, 128 129 }; 130 131 /* this is going to have a few of the MSBs set that we need to 132 * clear 133 */ 134 bitmap_complement(gpu_resources.queue_bitmap, 135 adev->gfx.mec.queue_bitmap, 136 KGD_MAX_QUEUES); 137 138 /* According to linux/bitmap.h we shouldn't use bitmap_clear if 139 * nbits is not compile time constant 140 */ 141 last_valid_bit = 1 /* only first MEC can have compute queues */ 142 * adev->gfx.mec.num_pipe_per_mec 143 * adev->gfx.mec.num_queue_per_pipe; 144 for (i = last_valid_bit; i < KGD_MAX_QUEUES; ++i) 145 clear_bit(i, gpu_resources.queue_bitmap); 146 147 amdgpu_doorbell_get_kfd_info(adev, 148 &gpu_resources.doorbell_physical_address, 149 &gpu_resources.doorbell_aperture_size, 150 &gpu_resources.doorbell_start_offset); 151 152 /* Since SOC15, BIF starts to statically use the 153 * lower 12 bits of doorbell addresses for routing 154 * based on settings in registers like 155 * SDMA0_DOORBELL_RANGE etc.. 156 * In order to route a doorbell to CP engine, the lower 157 * 12 bits of its address has to be outside the range 158 * set for SDMA, VCN, and IH blocks. 159 */ 160 if (adev->asic_type >= CHIP_VEGA10) { 161 gpu_resources.non_cp_doorbells_start = 162 adev->doorbell_index.first_non_cp; 163 gpu_resources.non_cp_doorbells_end = 164 adev->doorbell_index.last_non_cp; 165 } 166 167 kgd2kfd_device_init(adev->kfd.dev, adev->ddev, &gpu_resources); 168 } 169 } 170 171 void amdgpu_amdkfd_device_fini(struct amdgpu_device *adev) 172 { 173 if (adev->kfd.dev) { 174 kgd2kfd_device_exit(adev->kfd.dev); 175 adev->kfd.dev = NULL; 176 } 177 } 178 179 void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev, 180 const void *ih_ring_entry) 181 { 182 if (adev->kfd.dev) 183 kgd2kfd_interrupt(adev->kfd.dev, ih_ring_entry); 184 } 185 186 void amdgpu_amdkfd_suspend(struct amdgpu_device *adev) 187 { 188 if (adev->kfd.dev) 189 kgd2kfd_suspend(adev->kfd.dev); 190 } 191 192 int amdgpu_amdkfd_resume(struct amdgpu_device *adev) 193 { 194 int r = 0; 195 196 if (adev->kfd.dev) 197 r = kgd2kfd_resume(adev->kfd.dev); 198 199 return r; 200 } 201 202 int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev) 203 { 204 int r = 0; 205 206 if (adev->kfd.dev) 207 r = kgd2kfd_pre_reset(adev->kfd.dev); 208 209 return r; 210 } 211 212 int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev) 213 { 214 int r = 0; 215 216 if (adev->kfd.dev) 217 r = kgd2kfd_post_reset(adev->kfd.dev); 218 219 return r; 220 } 221 222 void amdgpu_amdkfd_gpu_reset(struct kgd_dev *kgd) 223 { 224 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 225 226 if (amdgpu_device_should_recover_gpu(adev)) 227 amdgpu_device_gpu_recover(adev, NULL); 228 } 229 230 int amdgpu_amdkfd_alloc_gtt_mem(struct kgd_dev *kgd, size_t size, 231 void **mem_obj, uint64_t *gpu_addr, 232 void **cpu_ptr, bool mqd_gfx9) 233 { 234 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 235 struct amdgpu_bo *bo = NULL; 236 struct amdgpu_bo_param bp; 237 int r; 238 void *cpu_ptr_tmp = NULL; 239 240 memset(&bp, 0, sizeof(bp)); 241 bp.size = size; 242 bp.byte_align = PAGE_SIZE; 243 bp.domain = AMDGPU_GEM_DOMAIN_GTT; 244 bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC; 245 bp.type = ttm_bo_type_kernel; 246 bp.resv = NULL; 247 248 if (mqd_gfx9) 249 bp.flags |= AMDGPU_GEM_CREATE_MQD_GFX9; 250 251 r = amdgpu_bo_create(adev, &bp, &bo); 252 if (r) { 253 dev_err(adev->dev, 254 "failed to allocate BO for amdkfd (%d)\n", r); 255 return r; 256 } 257 258 /* map the buffer */ 259 r = amdgpu_bo_reserve(bo, true); 260 if (r) { 261 dev_err(adev->dev, "(%d) failed to reserve bo for amdkfd\n", r); 262 goto allocate_mem_reserve_bo_failed; 263 } 264 265 r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT); 266 if (r) { 267 dev_err(adev->dev, "(%d) failed to pin bo for amdkfd\n", r); 268 goto allocate_mem_pin_bo_failed; 269 } 270 271 r = amdgpu_ttm_alloc_gart(&bo->tbo); 272 if (r) { 273 dev_err(adev->dev, "%p bind failed\n", bo); 274 goto allocate_mem_kmap_bo_failed; 275 } 276 277 r = amdgpu_bo_kmap(bo, &cpu_ptr_tmp); 278 if (r) { 279 dev_err(adev->dev, 280 "(%d) failed to map bo to kernel for amdkfd\n", r); 281 goto allocate_mem_kmap_bo_failed; 282 } 283 284 *mem_obj = bo; 285 *gpu_addr = amdgpu_bo_gpu_offset(bo); 286 *cpu_ptr = cpu_ptr_tmp; 287 288 amdgpu_bo_unreserve(bo); 289 290 return 0; 291 292 allocate_mem_kmap_bo_failed: 293 amdgpu_bo_unpin(bo); 294 allocate_mem_pin_bo_failed: 295 amdgpu_bo_unreserve(bo); 296 allocate_mem_reserve_bo_failed: 297 amdgpu_bo_unref(&bo); 298 299 return r; 300 } 301 302 void amdgpu_amdkfd_free_gtt_mem(struct kgd_dev *kgd, void *mem_obj) 303 { 304 struct amdgpu_bo *bo = (struct amdgpu_bo *) mem_obj; 305 306 amdgpu_bo_reserve(bo, true); 307 amdgpu_bo_kunmap(bo); 308 amdgpu_bo_unpin(bo); 309 amdgpu_bo_unreserve(bo); 310 amdgpu_bo_unref(&(bo)); 311 } 312 313 int amdgpu_amdkfd_alloc_gws(struct kgd_dev *kgd, size_t size, 314 void **mem_obj) 315 { 316 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 317 struct amdgpu_bo *bo = NULL; 318 struct amdgpu_bo_param bp; 319 int r; 320 321 memset(&bp, 0, sizeof(bp)); 322 bp.size = size; 323 bp.byte_align = 1; 324 bp.domain = AMDGPU_GEM_DOMAIN_GWS; 325 bp.flags = AMDGPU_GEM_CREATE_NO_CPU_ACCESS; 326 bp.type = ttm_bo_type_device; 327 bp.resv = NULL; 328 329 r = amdgpu_bo_create(adev, &bp, &bo); 330 if (r) { 331 dev_err(adev->dev, 332 "failed to allocate gws BO for amdkfd (%d)\n", r); 333 return r; 334 } 335 336 *mem_obj = bo; 337 return 0; 338 } 339 340 void amdgpu_amdkfd_free_gws(struct kgd_dev *kgd, void *mem_obj) 341 { 342 struct amdgpu_bo *bo = (struct amdgpu_bo *)mem_obj; 343 344 amdgpu_bo_unref(&bo); 345 } 346 347 uint32_t amdgpu_amdkfd_get_fw_version(struct kgd_dev *kgd, 348 enum kgd_engine_type type) 349 { 350 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 351 352 switch (type) { 353 case KGD_ENGINE_PFP: 354 return adev->gfx.pfp_fw_version; 355 356 case KGD_ENGINE_ME: 357 return adev->gfx.me_fw_version; 358 359 case KGD_ENGINE_CE: 360 return adev->gfx.ce_fw_version; 361 362 case KGD_ENGINE_MEC1: 363 return adev->gfx.mec_fw_version; 364 365 case KGD_ENGINE_MEC2: 366 return adev->gfx.mec2_fw_version; 367 368 case KGD_ENGINE_RLC: 369 return adev->gfx.rlc_fw_version; 370 371 case KGD_ENGINE_SDMA1: 372 return adev->sdma.instance[0].fw_version; 373 374 case KGD_ENGINE_SDMA2: 375 return adev->sdma.instance[1].fw_version; 376 377 default: 378 return 0; 379 } 380 381 return 0; 382 } 383 384 void amdgpu_amdkfd_get_local_mem_info(struct kgd_dev *kgd, 385 struct kfd_local_mem_info *mem_info) 386 { 387 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 388 #ifdef __NetBSD__ 389 uint64_t address_mask = ~(uint64_t)0; /* XXX */ 390 #else 391 uint64_t address_mask = adev->dev->dma_mask ? ~*adev->dev->dma_mask : 392 ~((1ULL << 32) - 1); 393 #endif 394 resource_size_t aper_limit = adev->gmc.aper_base + adev->gmc.aper_size; 395 396 memset(mem_info, 0, sizeof(*mem_info)); 397 if (!(adev->gmc.aper_base & address_mask || aper_limit & address_mask)) { 398 mem_info->local_mem_size_public = adev->gmc.visible_vram_size; 399 mem_info->local_mem_size_private = adev->gmc.real_vram_size - 400 adev->gmc.visible_vram_size; 401 } else { 402 mem_info->local_mem_size_public = 0; 403 mem_info->local_mem_size_private = adev->gmc.real_vram_size; 404 } 405 mem_info->vram_width = adev->gmc.vram_width; 406 407 pr_debug("Address base: %pap limit %pap public 0x%"PRIx64" private 0x%"PRIx64"\n", 408 &adev->gmc.aper_base, &aper_limit, 409 mem_info->local_mem_size_public, 410 mem_info->local_mem_size_private); 411 412 if (amdgpu_sriov_vf(adev)) 413 mem_info->mem_clk_max = adev->clock.default_mclk / 100; 414 else if (adev->powerplay.pp_funcs) { 415 if (amdgpu_emu_mode == 1) 416 mem_info->mem_clk_max = 0; 417 else 418 mem_info->mem_clk_max = amdgpu_dpm_get_mclk(adev, false) / 100; 419 } else 420 mem_info->mem_clk_max = 100; 421 } 422 423 uint64_t amdgpu_amdkfd_get_gpu_clock_counter(struct kgd_dev *kgd) 424 { 425 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 426 427 if (adev->gfx.funcs->get_gpu_clock_counter) 428 return adev->gfx.funcs->get_gpu_clock_counter(adev); 429 return 0; 430 } 431 432 uint32_t amdgpu_amdkfd_get_max_engine_clock_in_mhz(struct kgd_dev *kgd) 433 { 434 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 435 436 /* the sclk is in quantas of 10kHz */ 437 if (amdgpu_sriov_vf(adev)) 438 return adev->clock.default_sclk / 100; 439 else if (adev->powerplay.pp_funcs) 440 return amdgpu_dpm_get_sclk(adev, false) / 100; 441 else 442 return 100; 443 } 444 445 void amdgpu_amdkfd_get_cu_info(struct kgd_dev *kgd, struct kfd_cu_info *cu_info) 446 { 447 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 448 struct amdgpu_cu_info acu_info = adev->gfx.cu_info; 449 450 memset(cu_info, 0, sizeof(*cu_info)); 451 if (sizeof(cu_info->cu_bitmap) != sizeof(acu_info.bitmap)) 452 return; 453 454 cu_info->cu_active_number = acu_info.number; 455 cu_info->cu_ao_mask = acu_info.ao_cu_mask; 456 memcpy(&cu_info->cu_bitmap[0], &acu_info.bitmap[0], 457 sizeof(acu_info.bitmap)); 458 cu_info->num_shader_engines = adev->gfx.config.max_shader_engines; 459 cu_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; 460 cu_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh; 461 cu_info->simd_per_cu = acu_info.simd_per_cu; 462 cu_info->max_waves_per_simd = acu_info.max_waves_per_simd; 463 cu_info->wave_front_size = acu_info.wave_front_size; 464 cu_info->max_scratch_slots_per_cu = acu_info.max_scratch_slots_per_cu; 465 cu_info->lds_size = acu_info.lds_size; 466 } 467 468 int amdgpu_amdkfd_get_dmabuf_info(struct kgd_dev *kgd, int dma_buf_fd, 469 struct kgd_dev **dma_buf_kgd, 470 uint64_t *bo_size, void *metadata_buffer, 471 size_t buffer_size, uint32_t *metadata_size, 472 uint32_t *flags) 473 { 474 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 475 struct dma_buf *dma_buf; 476 struct drm_gem_object *obj; 477 struct amdgpu_bo *bo; 478 uint64_t metadata_flags; 479 int r = -EINVAL; 480 481 dma_buf = dma_buf_get(dma_buf_fd); 482 if (IS_ERR(dma_buf)) 483 return PTR_ERR(dma_buf); 484 485 if (dma_buf->ops != &amdgpu_dmabuf_ops) 486 /* Can't handle non-graphics buffers */ 487 goto out_put; 488 489 obj = dma_buf->priv; 490 if (obj->dev->driver != adev->ddev->driver) 491 /* Can't handle buffers from different drivers */ 492 goto out_put; 493 494 adev = obj->dev->dev_private; 495 bo = gem_to_amdgpu_bo(obj); 496 if (!(bo->preferred_domains & (AMDGPU_GEM_DOMAIN_VRAM | 497 AMDGPU_GEM_DOMAIN_GTT))) 498 /* Only VRAM and GTT BOs are supported */ 499 goto out_put; 500 501 r = 0; 502 if (dma_buf_kgd) 503 *dma_buf_kgd = (struct kgd_dev *)adev; 504 if (bo_size) 505 *bo_size = amdgpu_bo_size(bo); 506 if (metadata_size) 507 *metadata_size = bo->metadata_size; 508 if (metadata_buffer) 509 r = amdgpu_bo_get_metadata(bo, metadata_buffer, buffer_size, 510 metadata_size, &metadata_flags); 511 if (flags) { 512 *flags = (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ? 513 ALLOC_MEM_FLAGS_VRAM : ALLOC_MEM_FLAGS_GTT; 514 515 if (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) 516 *flags |= ALLOC_MEM_FLAGS_PUBLIC; 517 } 518 519 out_put: 520 dma_buf_put(dma_buf); 521 return r; 522 } 523 524 uint64_t amdgpu_amdkfd_get_vram_usage(struct kgd_dev *kgd) 525 { 526 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 527 528 return amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); 529 } 530 531 uint64_t amdgpu_amdkfd_get_hive_id(struct kgd_dev *kgd) 532 { 533 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 534 535 return adev->gmc.xgmi.hive_id; 536 } 537 uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct kgd_dev *dst, struct kgd_dev *src) 538 { 539 struct amdgpu_device *peer_adev = (struct amdgpu_device *)src; 540 struct amdgpu_device *adev = (struct amdgpu_device *)dst; 541 int ret = amdgpu_xgmi_get_hops_count(adev, peer_adev); 542 543 if (ret < 0) { 544 DRM_ERROR("amdgpu: failed to get xgmi hops count between node %d and %d. ret = %d\n", 545 adev->gmc.xgmi.physical_node_id, 546 peer_adev->gmc.xgmi.physical_node_id, ret); 547 ret = 0; 548 } 549 return (uint8_t)ret; 550 } 551 552 uint64_t amdgpu_amdkfd_get_mmio_remap_phys_addr(struct kgd_dev *kgd) 553 { 554 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 555 556 return adev->rmmio_remap.bus_addr; 557 } 558 559 uint32_t amdgpu_amdkfd_get_num_gws(struct kgd_dev *kgd) 560 { 561 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 562 563 return adev->gds.gws_size; 564 } 565 566 int amdgpu_amdkfd_submit_ib(struct kgd_dev *kgd, enum kgd_engine_type engine, 567 uint32_t vmid, uint64_t gpu_addr, 568 uint32_t *ib_cmd, uint32_t ib_len) 569 { 570 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 571 struct amdgpu_job *job; 572 struct amdgpu_ib *ib; 573 struct amdgpu_ring *ring; 574 struct dma_fence *f = NULL; 575 int ret; 576 577 switch (engine) { 578 case KGD_ENGINE_MEC1: 579 ring = &adev->gfx.compute_ring[0]; 580 break; 581 case KGD_ENGINE_SDMA1: 582 ring = &adev->sdma.instance[0].ring; 583 break; 584 case KGD_ENGINE_SDMA2: 585 ring = &adev->sdma.instance[1].ring; 586 break; 587 default: 588 pr_err("Invalid engine in IB submission: %d\n", engine); 589 ret = -EINVAL; 590 goto err; 591 } 592 593 ret = amdgpu_job_alloc(adev, 1, &job, NULL); 594 if (ret) 595 goto err; 596 597 ib = &job->ibs[0]; 598 memset(ib, 0, sizeof(struct amdgpu_ib)); 599 600 ib->gpu_addr = gpu_addr; 601 ib->ptr = ib_cmd; 602 ib->length_dw = ib_len; 603 /* This works for NO_HWS. TODO: need to handle without knowing VMID */ 604 job->vmid = vmid; 605 606 ret = amdgpu_ib_schedule(ring, 1, ib, job, &f); 607 if (ret) { 608 DRM_ERROR("amdgpu: failed to schedule IB.\n"); 609 goto err_ib_sched; 610 } 611 612 ret = dma_fence_wait(f, false); 613 614 err_ib_sched: 615 dma_fence_put(f); 616 amdgpu_job_free(job); 617 err: 618 return ret; 619 } 620 621 void amdgpu_amdkfd_set_compute_idle(struct kgd_dev *kgd, bool idle) 622 { 623 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 624 625 amdgpu_dpm_switch_power_profile(adev, 626 PP_SMC_POWER_PROFILE_COMPUTE, 627 !idle); 628 } 629 630 bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid) 631 { 632 if (adev->kfd.dev) { 633 if ((1 << vmid) & compute_vmid_bitmap) 634 return true; 635 } 636 637 return false; 638 } 639 640 int amdgpu_amdkfd_flush_gpu_tlb_vmid(struct kgd_dev *kgd, uint16_t vmid) 641 { 642 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 643 644 if (adev->family == AMDGPU_FAMILY_AI) { 645 int i; 646 647 for (i = 0; i < adev->num_vmhubs; i++) 648 amdgpu_gmc_flush_gpu_tlb(adev, vmid, i, 0); 649 } else { 650 amdgpu_gmc_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB_0, 0); 651 } 652 653 return 0; 654 } 655 656 int amdgpu_amdkfd_flush_gpu_tlb_pasid(struct kgd_dev *kgd, uint16_t pasid) 657 { 658 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 659 uint32_t flush_type = 0; 660 bool all_hub = false; 661 662 if (adev->gmc.xgmi.num_physical_nodes && 663 adev->asic_type == CHIP_VEGA20) 664 flush_type = 2; 665 666 if (adev->family == AMDGPU_FAMILY_AI) 667 all_hub = true; 668 669 return amdgpu_gmc_flush_gpu_tlb_pasid(adev, pasid, flush_type, all_hub); 670 } 671 672 bool amdgpu_amdkfd_have_atomics_support(struct kgd_dev *kgd) 673 { 674 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 675 676 return adev->have_atomics_support; 677 } 678 679 #ifndef CONFIG_HSA_AMD 680 bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm) 681 { 682 return false; 683 } 684 685 void amdgpu_amdkfd_unreserve_memory_limit(struct amdgpu_bo *bo) 686 { 687 } 688 689 void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev, 690 struct amdgpu_vm *vm) 691 { 692 } 693 694 struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f) 695 { 696 return NULL; 697 } 698 699 int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, struct mm_struct *mm) 700 { 701 return 0; 702 } 703 704 struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd, struct pci_dev *pdev, 705 unsigned int asic_type, bool vf) 706 { 707 return NULL; 708 } 709 710 bool kgd2kfd_device_init(struct kfd_dev *kfd, 711 struct drm_device *ddev, 712 const struct kgd2kfd_shared_resources *gpu_resources) 713 { 714 return false; 715 } 716 717 void kgd2kfd_device_exit(struct kfd_dev *kfd) 718 { 719 } 720 721 void kgd2kfd_exit(void) 722 { 723 } 724 725 void kgd2kfd_suspend(struct kfd_dev *kfd) 726 { 727 } 728 729 int kgd2kfd_resume(struct kfd_dev *kfd) 730 { 731 return 0; 732 } 733 734 int kgd2kfd_pre_reset(struct kfd_dev *kfd) 735 { 736 return 0; 737 } 738 739 int kgd2kfd_post_reset(struct kfd_dev *kfd) 740 { 741 return 0; 742 } 743 744 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry) 745 { 746 } 747 748 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd) 749 { 750 } 751 #endif 752
Indexes created Sat Sep 20 22:09:52 GMT 2025