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      1 /*	$NetBSD: nouveau_nvkm_engine_ce_gt215.c,v 1.3 2021/12/18 23:45:34 riastradh Exp $	*/
      2 
      3 /*
      4  * Copyright 2012 Red Hat Inc.
      5  *
      6  * Permission is hereby granted, free of charge, to any person obtaining a
      7  * copy of this software and associated documentation files (the "Software"),
      8  * to deal in the Software without restriction, including without limitation
      9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
     10  * and/or sell copies of the Software, and to permit persons to whom the
     11  * Software is furnished to do so, subject to the following conditions:
     12  *
     13  * The above copyright notice and this permission notice shall be included in
     14  * all copies or substantial portions of the Software.
     15  *
     16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     22  * OTHER DEALINGS IN THE SOFTWARE.
     23  *
     24  * Authors: Ben Skeggs
     25  */
     26 #include <sys/cdefs.h>
     27 __KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_engine_ce_gt215.c,v 1.3 2021/12/18 23:45:34 riastradh Exp $");
     28 
     29 #include "priv.h"
     30 #include "fuc/gt215.fuc3.h"
     31 
     32 #include <core/client.h>
     33 #include <core/enum.h>
     34 #include <core/gpuobj.h>
     35 #include <engine/fifo.h>
     36 
     37 #include <nvif/class.h>
     38 
     39 static const struct nvkm_enum
     40 gt215_ce_isr_error_name[] = {
     41 	{ 0x0001, "ILLEGAL_MTHD" },
     42 	{ 0x0002, "INVALID_ENUM" },
     43 	{ 0x0003, "INVALID_BITFIELD" },
     44 	{}
     45 };
     46 
     47 void
     48 gt215_ce_intr(struct nvkm_falcon *ce, struct nvkm_fifo_chan *chan)
     49 {
     50 	struct nvkm_subdev *subdev = &ce->engine.subdev;
     51 	struct nvkm_device *device = subdev->device;
     52 	const u32 base = (subdev->index - NVKM_ENGINE_CE0) * 0x1000;
     53 	u32 ssta = nvkm_rd32(device, 0x104040 + base) & 0x0000ffff;
     54 	u32 addr = nvkm_rd32(device, 0x104040 + base) >> 16;
     55 	u32 mthd = (addr & 0x07ff) << 2;
     56 	u32 subc = (addr & 0x3800) >> 11;
     57 	u32 data = nvkm_rd32(device, 0x104044 + base);
     58 	const struct nvkm_enum *en =
     59 		nvkm_enum_find(gt215_ce_isr_error_name, ssta);
     60 
     61 	nvkm_error(subdev, "DISPATCH_ERROR %04x [%s] ch %d [%010"PRIx64" %s] "
     62 			   "subc %d mthd %04x data %08x\n", ssta,
     63 		   en ? en->name : "", chan ? chan->chid : -1,
     64 		   chan ? chan->inst->addr : 0,
     65 		   chan ? chan->object.client->name : "unknown",
     66 		   subc, mthd, data);
     67 }
     68 
     69 static const struct nvkm_falcon_func
     70 gt215_ce = {
     71 	.code.data = gt215_ce_code,
     72 	.code.size = sizeof(gt215_ce_code),
     73 	.data.data = gt215_ce_data,
     74 	.data.size = sizeof(gt215_ce_data),
     75 	.intr = gt215_ce_intr,
     76 	.sclass = {
     77 		{ -1, -1, GT212_DMA },
     78 		{}
     79 	}
     80 };
     81 
     82 int
     83 gt215_ce_new(struct nvkm_device *device, int index,
     84 	     struct nvkm_engine **pengine)
     85 {
     86 	return nvkm_falcon_new_(&gt215_ce, device, index,
     87 				(device->chipset != 0xaf), 0x104000, pengine);
     88 }
     89