1 /* $NetBSD: gt.c,v 1.35 2023/12/20 06:36:03 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Soren S. Jorvang. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions, and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: gt.c,v 1.35 2023/12/20 06:36:03 thorpej Exp $"); 30 31 #include "opt_pci.h" 32 #include "pci.h" 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/conf.h> 37 #include <sys/device.h> 38 #include <sys/file.h> 39 #include <sys/intr.h> 40 #include <sys/ioctl.h> 41 #include <sys/kernel.h> 42 #include <sys/proc.h> 43 #include <sys/select.h> 44 #include <sys/syslog.h> 45 #include <sys/systm.h> 46 #include <sys/tty.h> 47 #include <sys/uio.h> 48 49 #include <machine/autoconf.h> 50 51 #include <mips/cache.h> 52 53 #include <dev/pci/pcivar.h> 54 #ifdef PCI_NETBSD_CONFIGURE 55 #include <dev/pci/pciconf.h> 56 #endif 57 58 #include <cobalt/dev/gtvar.h> 59 #include <cobalt/dev/gtreg.h> 60 61 struct gt_softc { 62 device_t sc_dev; 63 64 bus_space_tag_t sc_bst; 65 bus_space_handle_t sc_bsh; 66 struct cobalt_pci_chipset sc_pc; 67 }; 68 69 static int gt_match(device_t, cfdata_t, void *); 70 static void gt_attach(device_t, device_t, void *); 71 static int gt_print(void *aux, const char *pnp); 72 73 static void gt_timer_init(struct gt_softc *sc); 74 #if 0 /* unused */ 75 static void gt_timer0_init(void *); 76 static long gt_timer0_read(void *); 77 #endif 78 79 struct mips_bus_space gt_iot; 80 struct mips_bus_space gt_memt; 81 82 CFATTACH_DECL_NEW(gt, sizeof(struct gt_softc), 83 gt_match, gt_attach, NULL, NULL); 84 85 #define PCI_IO_START 0x00001000 86 #define PCI_IO_END 0x01ffffff 87 #define PCI_IO_SIZE ((PCI_IO_END - PCI_IO_START) + 1) 88 89 #define PCI_MEM_START 0x12000000 90 #define PCI_MEM_END 0x13ffffff 91 #define PCI_MEM_SIZE ((PCI_MEM_END - PCI_MEM_START) + 1) 92 93 static int 94 gt_match(device_t parent, cfdata_t cf, void *aux) 95 { 96 97 return 1; 98 } 99 100 #define GT_REG_REGION 0x1000 101 102 static void 103 gt_attach(device_t parent, device_t self, void *aux) 104 { 105 struct gt_softc *sc = device_private(self); 106 struct mainbus_attach_args *ma = aux; 107 #if NPCI > 0 108 pci_chipset_tag_t pc; 109 struct pcibus_attach_args pba; 110 #endif 111 112 sc->sc_dev = self; 113 sc->sc_bst = ma->ma_iot; 114 if (bus_space_map(sc->sc_bst, ma->ma_addr, GT_REG_REGION, 115 0, &sc->sc_bsh)) { 116 aprint_error(": unable to map GT64111 registers\n"); 117 return; 118 } 119 120 aprint_normal("\n"); 121 122 gt_timer_init(sc); 123 124 bus_space_write_4(sc->sc_bst, sc->sc_bsh, GT_PCI_COMMAND, 125 (bus_space_read_4(sc->sc_bst, sc->sc_bsh, GT_PCI_COMMAND) & 126 ~PCI_SYNCMODE) | PCI_PCLK_HIGH); 127 128 (void)bus_space_read_4(sc->sc_bst, sc->sc_bsh, GT_PCI_TIMEOUT_RETRY); 129 bus_space_write_4(sc->sc_bst, sc->sc_bsh, GT_PCI_TIMEOUT_RETRY, 130 0x00 << PCI_RETRYCTR_SHIFT | 0xff << PCI_TIMEOUT1_SHIFT | 0xff); 131 132 gt_bus_mem_init(>_memt, NULL); 133 gt_bus_io_init(>_iot, NULL); 134 135 #if NPCI > 0 136 pc = &sc->sc_pc; 137 pc->pc_bst = sc->sc_bst; 138 pc->pc_bsh = sc->sc_bsh; 139 140 #ifdef PCI_NETBSD_CONFIGURE 141 struct pciconf_resources *pcires = pciconf_resource_init(); 142 pciconf_resource_add(pcires, PCICONF_RESOURCE_IO, 143 PCI_IO_START, PCI_IO_SIZE); 144 pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM, 145 PCI_MEM_START, PCI_MEM_SIZE); 146 pci_configure_bus(pc, pcires, 0, mips_cache_info.mci_dcache_align); 147 pciconf_resource_fini(pcires); 148 #endif 149 memset(&pba, 0, sizeof(pba)); 150 pba.pba_memt = >_memt; 151 pba.pba_iot = >_iot; 152 pba.pba_dmat = &pci_bus_dma_tag; 153 pba.pba_dmat64 = NULL; 154 pba.pba_bus = 0; 155 pba.pba_bridgetag = NULL; 156 pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY | 157 PCI_FLAGS_MRL_OKAY | /*PCI_FLAGS_MRM_OKAY|*/ PCI_FLAGS_MWI_OKAY; 158 pba.pba_pc = pc; 159 config_found(self, &pba, gt_print, CFARGS_NONE); 160 #endif 161 } 162 163 static int 164 gt_print(void *aux, const char *pnp) 165 { 166 167 /* XXX */ 168 return 0; 169 } 170 171 static void 172 gt_timer_init(struct gt_softc *sc) 173 { 174 175 /* stop timer0 */ 176 bus_space_write_4(sc->sc_bst, sc->sc_bsh, GT_TIMER_CTRL, 177 bus_space_read_4(sc->sc_bst, sc->sc_bsh, GT_TIMER_CTRL) & ~ENTC0); 178 /* mask timer0 interrupt */ 179 bus_space_write_4(sc->sc_bst, sc->sc_bsh, GT_MASTER_MASK, 180 bus_space_read_4(sc->sc_bst, sc->sc_bsh, GT_MASTER_MASK) & ~T0EXP); 181 } 182 183 #if 0 /* unused; now NetBSD/cobalt uses CPU INT5 for hardclock(9) */ 184 #define TIMER0_INIT_VALUE 500000 185 186 static void 187 gt_timer0_init(void *cookie) 188 { 189 struct gt_softc *sc = cookie; 190 191 bus_space_write_4(sc->sc_bst, sc->sc_bsh, 192 GT_TIMER_COUNTER0, TIMER0_INIT_VALUE); 193 /* start timer0 */ 194 bus_space_write_4(sc->sc_bst, sc->sc_bsh, GT_TIMER_CTRL, 195 bus_space_read_4(sc->sc_bst, sc->sc_bsh, GT_TIMER_CTRL) | ENTC0); 196 /* unmask timer0 interrupt */ 197 bus_space_write_4(sc->sc_bst, sc->sc_bsh, GT_MASTER_MASK, 198 bus_space_read_4(sc->sc_bst, sc->sc_bsh, GT_MASTER_MASK) | T0EXP); 199 } 200 201 static long 202 gt_timer0_read(void *cookie) 203 { 204 struct gt_softc *sc = cookie; 205 uint32_t counter0; 206 207 counter0 = bus_space_read_4(sc->sc_bst, sc->sc_bsh, GT_TIMER_COUNTER0); 208 counter0 = TIMER0_INIT_VALUE - counter0; 209 #if 0 210 counter /= 50; 211 #else 212 /* 213 * From pmax/pmax/dec_3min.c: 214 * 1/64 + 1/256 + 1/2048 = 41/2048 = 1/49.9512... 215 */ 216 counter0 = (counter0 >> 6) + (counter0 >> 8) + (counter0 >> 11); 217 #endif 218 return counter0; 219 } 220 #endif 221
Indexes created Wed Sep 24 02:09:48 GMT 2025