| /src/sys/external/bsd/drm2/dist/drm/i915/ |
| intel_wopcm.h | 17 * @guc: GuC WOPCM Region info.
18 * @guc.base: GuC WOPCM base which is offset from WOPCM base.
19 * @guc.size: Size of the GuC WOPCM region.
26 } guc; member in struct:intel_wopcm
36 * 0 if GuC is not present or not in use.
37 * Otherwise, the GuC WOPCM base.
41 return wopcm->guc.base
[all...] |
| i915_debugfs.c | 517 seq_printf(m, "GUC/SG Intr Enable:\t %08x\n",
642 seq_printf(m, "GUC/SG Intr Mask:\t %08x\n",
1720 intel_uc_fw_dump(&dev_priv->gt.uc.guc.fw, &p);
1763 struct intel_guc_log *log = &dev_priv->gt.uc.guc.log;
1767 seq_puts(m, "GuC log relay not created\n");
1771 seq_puts(m, "GuC logging stats:\n");
1801 const struct intel_guc *guc = &dev_priv->gt.uc.guc; local in function:i915_guc_stage_pool
1802 struct guc_stage_desc *desc = guc->stage_desc_pool_vaddr;
1814 seq_printf(m, "GuC stage descriptor %u:\n", index)
1918 struct intel_guc *guc = &i915->gt.uc.guc; local in function:i915_guc_log_relay_open
1958 struct intel_guc *guc = &i915->gt.uc.guc; local in function:i915_guc_log_relay_release
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/i915/gt/uc/ |
| intel_huc.c | 25 * triggering its security authentication, which is performed by the GuC. For
26 * The GuC to correctly perform the authentication, the HuC binary must be
27 * loaded before the GuC one. Loading the HuC is optional; however, not using
38 * Similarly to the GuC, the HuC can't do any memory allocations on its own,
65 struct intel_guc *guc = >->uc.guc; local in function:intel_huc_rsa_data_create
77 * through GTT. Unfortunately, this means GuC cannot perform
78 * the HuC auth. as the rsa offset now falls within the GuC
81 * signature. The GuC can use this extra pinning to perform
82 * the authentication since its GGTT offset will be GuC
161 struct intel_guc *guc = >->uc.guc; local in function:intel_huc_auth
[all...] |
| intel_uc.h | 29 struct intel_guc guc; member in struct:intel_uc
32 /* Snapshot of GuC log from last failed load */
47 return intel_guc_is_supported(&uc->guc);
52 return intel_guc_is_enabled(&uc->guc);
57 return intel_guc_is_submission_supported(&uc->guc);
62 return intel_guc_is_submission_supported(&uc->guc);
|
| intel_guc_log.c | 21 * DOC: GuC firmware log
29 static int guc_action_flush_log_complete(struct intel_guc *guc)
35 return intel_guc_send(guc, action, ARRAY_SIZE(action));
38 static int guc_action_flush_log(struct intel_guc *guc)
45 return intel_guc_send(guc, action, ARRAY_SIZE(action));
48 static int guc_action_control_log(struct intel_guc *guc, bool enable,
60 return intel_guc_send(guc, action, ARRAY_SIZE(action));
201 "GuC log buffer overflow\n");
237 /* Get the pointer to shared GuC log buffer */
260 * Make a copy of the state structure, inside GuC log buffe
374 struct intel_guc *guc = log_to_guc(log); local in function:guc_log_relay_create
421 struct intel_guc *guc = log_to_guc(log); local in function:guc_log_capture_logs
460 struct intel_guc *guc = log_to_guc(log); local in function:intel_guc_log_create
518 struct intel_guc *guc = log_to_guc(log); local in function:intel_guc_log_set_level
626 struct intel_guc *guc = log_to_guc(log); local in function:intel_guc_log_relay_flush
652 struct intel_guc *guc = log_to_guc(log); local in function:guc_log_relay_stop
[all...] |
| intel_uc.c | 23 /* Reset GuC providing us with fresh state for both GuC and HuC.
37 DRM_ERROR("Failed to reset GuC, ret = %d\n", ret);
43 "GuC status: 0x%x, MIA core expected to be in reset\n",
54 "enable_guc=%d (guc:%s submission:%s huc:%s)\n",
73 i915_modparams.enable_guc, "GuC is not supported!");
85 i915_modparams.enable_guc, "GuC submission is N/A");
96 intel_guc_init_early(&uc->guc);
120 intel_guc_init_send_regs(&uc->guc);
125 struct intel_guc *guc = &uc->guc local in function:__uc_capture_load_err_log
283 struct intel_guc *guc = &uc->guc; local in function:__uc_init
312 struct intel_guc *guc = &uc->guc; local in function:__uc_sanitize
405 struct intel_guc *guc = &uc->guc; local in function:__uc_init_hw
511 struct intel_guc *guc = &uc->guc; local in function:__uc_fini_hw
533 struct intel_guc *guc = &uc->guc; local in function:intel_uc_reset_prepare
544 struct intel_guc *guc = &uc->guc; local in function:intel_uc_runtime_suspend
559 struct intel_guc *guc = &uc->guc; local in function:intel_uc_suspend
571 struct intel_guc *guc = &uc->guc; local in function:__uc_resume
[all...] |
| intel_guc_ct.c | 87 static int guc_action_register_ct_buffer(struct intel_guc *guc,
100 err = intel_guc_send_mmio(guc, action, ARRAY_SIZE(action), NULL, 0);
107 static int guc_action_deregister_ct_buffer(struct intel_guc *guc,
118 err = intel_guc_send_mmio(guc, action, ARRAY_SIZE(action), NULL, 0);
135 struct intel_guc *guc = ct_to_guc(ct); local in function:intel_guc_ct_init
164 err = intel_guc_allocate_and_map_vma(guc, PAGE_SIZE, &ct->vma, &blob);
171 intel_guc_ggtt_offset(guc, ct->vma));
205 struct intel_guc *guc = ct_to_guc(ct); local in function:intel_guc_ct_enable
214 base = intel_guc_ggtt_offset(guc, ct->vma);
229 err = guc_action_register_ct_buffer(guc,
259 struct intel_guc *guc = ct_to_guc(ct); local in function:intel_guc_ct_disable
548 struct intel_guc *guc = ct_to_guc(ct); local in function:intel_guc_ct_send
719 struct intel_guc *guc = ct_to_guc(ct); local in function:ct_process_request
[all...] |
| intel_guc_submission.c | 27 * DOC: GuC-based command submission
29 * IMPORTANT NOTE: GuC submission is currently not supported in i915. The GuC
35 * GuC stage descriptor:
37 * descriptors, and shares them with the GuC. Currently, we only use one
38 * descriptor. This stage descriptor lets the GuC know about the workqueue and
39 * process descriptor. Theoretically, it also lets the GuC know about our HW
41 * where the GuC uses the LRCA sent via the work item instead. This is called
47 * triggers an interrupt on the GuC via another register write (0xC4C8).
55 * WQ_TYPE_INORDER is needed to support legacy submission via GuC, whic
250 struct intel_guc *guc = &engine->gt->uc.guc; local in function:guc_submit
[all...] |
