1 /* $NetBSD: nouveau_nvkm_engine_gr_gv100.c,v 1.2 2021/12/18 23:45:36 riastradh Exp $ */ 2 3 /* 4 * Copyright 2018 Red Hat Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_engine_gr_gv100.c,v 1.2 2021/12/18 23:45:36 riastradh Exp $"); 26 27 #include "gf100.h" 28 #include "ctxgf100.h" 29 30 #include <nvif/class.h> 31 32 static void 33 gv100_gr_trap_sm(struct gf100_gr *gr, int gpc, int tpc, int sm) 34 { 35 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 36 struct nvkm_device *device = subdev->device; 37 u32 werr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x730 + (sm * 0x80))); 38 u32 gerr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x734 + (sm * 0x80))); 39 const struct nvkm_enum *warp; 40 char glob[128]; 41 42 nvkm_snprintbf(glob, sizeof(glob), gf100_mp_global_error, gerr); 43 warp = nvkm_enum_find(gf100_mp_warp_error, werr & 0xffff); 44 45 nvkm_error(subdev, "GPC%i/TPC%i/SM%d trap: " 46 "global %08x [%s] warp %04x [%s]\n", 47 gpc, tpc, sm, gerr, glob, werr, warp ? warp->name : ""); 48 49 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x730 + sm * 0x80), 0x00000000); 50 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x734 + sm * 0x80), gerr); 51 } 52 53 void 54 gv100_gr_trap_mp(struct gf100_gr *gr, int gpc, int tpc) 55 { 56 gv100_gr_trap_sm(gr, gpc, tpc, 0); 57 gv100_gr_trap_sm(gr, gpc, tpc, 1); 58 } 59 60 static void 61 gv100_gr_init_4188a4(struct gf100_gr *gr) 62 { 63 struct nvkm_device *device = gr->base.engine.subdev.device; 64 nvkm_mask(device, 0x4188a4, 0x03000000, 0x03000000); 65 } 66 67 void 68 gv100_gr_init_shader_exceptions(struct gf100_gr *gr, int gpc, int tpc) 69 { 70 struct nvkm_device *device = gr->base.engine.subdev.device; 71 int sm; 72 for (sm = 0; sm < 0x100; sm += 0x80) { 73 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x728 + sm), 0x0085eb64); 74 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x610), 0x00000001); 75 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x72c + sm), 0x00000004); 76 } 77 } 78 79 void 80 gv100_gr_init_504430(struct gf100_gr *gr, int gpc, int tpc) 81 { 82 struct nvkm_device *device = gr->base.engine.subdev.device; 83 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x430), 0x403f0000); 84 } 85 86 void 87 gv100_gr_init_419bd8(struct gf100_gr *gr) 88 { 89 struct nvkm_device *device = gr->base.engine.subdev.device; 90 nvkm_mask(device, 0x419bd8, 0x00000700, 0x00000000); 91 } 92 93 static const struct gf100_gr_func 94 gv100_gr = { 95 .oneinit_tiles = gm200_gr_oneinit_tiles, 96 .oneinit_sm_id = gm200_gr_oneinit_sm_id, 97 .init = gf100_gr_init, 98 .init_419bd8 = gv100_gr_init_419bd8, 99 .init_gpc_mmu = gm200_gr_init_gpc_mmu, 100 .init_vsc_stream_master = gk104_gr_init_vsc_stream_master, 101 .init_zcull = gf117_gr_init_zcull, 102 .init_num_active_ltcs = gm200_gr_init_num_active_ltcs, 103 .init_rop_active_fbps = gp100_gr_init_rop_active_fbps, 104 .init_swdx_pes_mask = gp102_gr_init_swdx_pes_mask, 105 .init_fecs_exceptions = gp100_gr_init_fecs_exceptions, 106 .init_ds_hww_esr_2 = gm200_gr_init_ds_hww_esr_2, 107 .init_sked_hww_esr = gk104_gr_init_sked_hww_esr, 108 .init_ppc_exceptions = gk104_gr_init_ppc_exceptions, 109 .init_504430 = gv100_gr_init_504430, 110 .init_shader_exceptions = gv100_gr_init_shader_exceptions, 111 .init_4188a4 = gv100_gr_init_4188a4, 112 .trap_mp = gv100_gr_trap_mp, 113 .rops = gm200_gr_rops, 114 .gpc_nr = 6, 115 .tpc_nr = 5, 116 .ppc_nr = 3, 117 .grctx = &gv100_grctx, 118 .zbc = &gp102_gr_zbc, 119 .sclass = { 120 { -1, -1, FERMI_TWOD_A }, 121 { -1, -1, KEPLER_INLINE_TO_MEMORY_B }, 122 { -1, -1, VOLTA_A, &gf100_fermi }, 123 { -1, -1, VOLTA_COMPUTE_A }, 124 {} 125 } 126 }; 127 128 MODULE_FIRMWARE("nvidia/gv100/gr/fecs_bl.bin"); 129 MODULE_FIRMWARE("nvidia/gv100/gr/fecs_inst.bin"); 130 MODULE_FIRMWARE("nvidia/gv100/gr/fecs_data.bin"); 131 MODULE_FIRMWARE("nvidia/gv100/gr/fecs_sig.bin"); 132 MODULE_FIRMWARE("nvidia/gv100/gr/gpccs_bl.bin"); 133 MODULE_FIRMWARE("nvidia/gv100/gr/gpccs_inst.bin"); 134 MODULE_FIRMWARE("nvidia/gv100/gr/gpccs_data.bin"); 135 MODULE_FIRMWARE("nvidia/gv100/gr/gpccs_sig.bin"); 136 MODULE_FIRMWARE("nvidia/gv100/gr/sw_ctx.bin"); 137 MODULE_FIRMWARE("nvidia/gv100/gr/sw_nonctx.bin"); 138 MODULE_FIRMWARE("nvidia/gv100/gr/sw_bundle_init.bin"); 139 MODULE_FIRMWARE("nvidia/gv100/gr/sw_method_init.bin"); 140 141 static const struct gf100_gr_fwif 142 gv100_gr_fwif[] = { 143 { 0, gm200_gr_load, &gv100_gr, &gp108_gr_fecs_acr, &gp108_gr_gpccs_acr }, 144 {} 145 }; 146 147 int 148 gv100_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) 149 { 150 return gf100_gr_new_(gv100_gr_fwif, device, index, pgr); 151 } 152
Indexes created Sun Sep 21 20:09:37 GMT 2025