| /src/sys/arch/evbarm/stand/board/ |
| smdk2800_io_init.c | 57 unsigned int hclk; local in function:smdk2800_io_init
90 hclk = FCLK / 2;
92 hclk = FCLK;
95 pclk = hclk / 2;
97 pclk = hclk;
|
| /src/sys/arch/arm/ep93xx/ |
| epsoc.c | 79 uint64_t fclk, pclk, hclk; local in function:epsoc_attach
138 hclk = fclk / hclkdivisors[hclkdiv];
139 pclk = hclk >> pclkdiv;
146 printf("%s: fclk %lld.%02lld MHz hclk %lld.%02lld MHz pclk %lld.%02lld MHz\n",
149 hclk / 1000000, (hclk % 1000000 + 5000) / 10000,
153 sc->sc_hclk = hclk;
|
| /src/sys/arch/arm/s3c2xx0/ |
| s3c24x0_lcd.c | 101 int hclk = s3c2xx0_softc->sc_hclk; local in function:s3c24x0_set_lcd_panel_info
107 clkval = (hclk / info->pixel_clock / 2) - 1;
110 clkval = uimax(2, hclk / info->pixel_clock / 2);
119 printf("hclk=%d pixel clock=%d, clkval = %x lcdcon1=%x\n",
120 hclk, info->pixel_clock, clkval, reg);
|
| /src/sys/arch/evbarm/stand/boot2440/ |
| main.c | 80 static void s3c24x0_clock_freq2(vaddr_t clkman_base, int *fclk, int *hclk,
112 int fclk, hclk; local in function:main
146 s3c24x0_clock_freq2(S3C2440_CLKMAN_BASE, &fclk, &hclk, &pclk);
408 s3c24x0_clock_freq2(vaddr_t clkman_base, int *fclk, int *hclk, int *pclk)
429 /* 00b: HCLK = FCLK/1*/
432 /* 01b: HCLK = FCLK/2*/
436 /* 10b: HCLK = FCLK/4 when CAMDIVN[9] (HCLK4_HALF) = 0
437 * HCLK = FCLK/8 when CAMDIVN[9] (HCLK4_HALF) = 1 */
444 /* 11b: HCLK = FCLK/3 when CAMDIVN[8] (HCLK3_HALF) = 0
445 * HCLK = FCLK/6 when CAMDIVN[8] (HCLK3_HALF) = 1 *
[all...] |
| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
| ste-nomadik-stn8815.dtsi | 226 /* HCLK divides the PLL1 with 1,2,3 or 4 */
227 hclk: hclk@0 { label in label:src
229 compatible = "st,nomadik-hclk-clock";
232 /* The PCLK domain uses HCLK right off */
238 clocks = <&hclk>;
302 clocks = <&hclk>;
308 clocks = <&hclk>;
314 clocks = <&hclk>;
320 clocks = <&hclk>;
[all...] |
