1 /* $NetBSD: nouveau_dispnv04_hw.c,v 1.4 2021/12/18 23:45:32 riastradh Exp $ */ 2 3 /* 4 * Copyright 2006 Dave Airlie 5 * Copyright 2007 Maarten Maathuis 6 * Copyright 2007-2009 Stuart Bennett 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 22 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF 23 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 24 * SOFTWARE. 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: nouveau_dispnv04_hw.c,v 1.4 2021/12/18 23:45:32 riastradh Exp $"); 29 30 #include "nouveau_drv.h" 31 #include "hw.h" 32 33 #include <subdev/bios/pll.h> 34 35 #define CHIPSET_NFORCE 0x01a0 36 #define CHIPSET_NFORCE2 0x01f0 37 38 /* 39 * misc hw access wrappers/control functions 40 */ 41 42 void 43 NVWriteVgaSeq(struct drm_device *dev, int head, uint8_t index, uint8_t value) 44 { 45 NVWritePRMVIO(dev, head, NV_PRMVIO_SRX, index); 46 NVWritePRMVIO(dev, head, NV_PRMVIO_SR, value); 47 } 48 49 uint8_t 50 NVReadVgaSeq(struct drm_device *dev, int head, uint8_t index) 51 { 52 NVWritePRMVIO(dev, head, NV_PRMVIO_SRX, index); 53 return NVReadPRMVIO(dev, head, NV_PRMVIO_SR); 54 } 55 56 void 57 NVWriteVgaGr(struct drm_device *dev, int head, uint8_t index, uint8_t value) 58 { 59 NVWritePRMVIO(dev, head, NV_PRMVIO_GRX, index); 60 NVWritePRMVIO(dev, head, NV_PRMVIO_GX, value); 61 } 62 63 uint8_t 64 NVReadVgaGr(struct drm_device *dev, int head, uint8_t index) 65 { 66 NVWritePRMVIO(dev, head, NV_PRMVIO_GRX, index); 67 return NVReadPRMVIO(dev, head, NV_PRMVIO_GX); 68 } 69 70 /* CR44 takes values 0 (head A), 3 (head B) and 4 (heads tied) 71 * it affects only the 8 bit vga io regs, which we access using mmio at 72 * 0xc{0,2}3c*, 0x60{1,3}3*, and 0x68{1,3}3d* 73 * in general, the set value of cr44 does not matter: reg access works as 74 * expected and values can be set for the appropriate head by using a 0x2000 75 * offset as required 76 * however: 77 * a) pre nv40, the head B range of PRMVIO regs at 0xc23c* was not exposed and 78 * cr44 must be set to 0 or 3 for accessing values on the correct head 79 * through the common 0xc03c* addresses 80 * b) in tied mode (4) head B is programmed to the values set on head A, and 81 * access using the head B addresses can have strange results, ergo we leave 82 * tied mode in init once we know to what cr44 should be restored on exit 83 * 84 * the owner parameter is slightly abused: 85 * 0 and 1 are treated as head values and so the set value is (owner * 3) 86 * other values are treated as literal values to set 87 */ 88 void 89 NVSetOwner(struct drm_device *dev, int owner) 90 { 91 struct nouveau_drm *drm = nouveau_drm(dev); 92 93 if (owner == 1) 94 owner *= 3; 95 96 if (drm->client.device.info.chipset == 0x11) { 97 /* This might seem stupid, but the blob does it and 98 * omitting it often locks the system up. 99 */ 100 NVReadVgaCrtc(dev, 0, NV_CIO_SR_LOCK_INDEX); 101 NVReadVgaCrtc(dev, 1, NV_CIO_SR_LOCK_INDEX); 102 } 103 104 /* CR44 is always changed on CRTC0 */ 105 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_44, owner); 106 107 if (drm->client.device.info.chipset == 0x11) { /* set me harder */ 108 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_2E, owner); 109 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_2E, owner); 110 } 111 } 112 113 void 114 NVBlankScreen(struct drm_device *dev, int head, bool blank) 115 { 116 unsigned char seq1; 117 118 if (nv_two_heads(dev)) 119 NVSetOwner(dev, head); 120 121 seq1 = NVReadVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX); 122 123 NVVgaSeqReset(dev, head, true); 124 if (blank) 125 NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 | 0x20); 126 else 127 NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 & ~0x20); 128 NVVgaSeqReset(dev, head, false); 129 } 130 131 /* 132 * PLL getting 133 */ 134 135 static void 136 nouveau_hw_decode_pll(struct drm_device *dev, uint32_t reg1, uint32_t pll1, 137 uint32_t pll2, struct nvkm_pll_vals *pllvals) 138 { 139 struct nouveau_drm *drm = nouveau_drm(dev); 140 141 /* to force parsing as single stage (i.e. nv40 vplls) pass pll2 as 0 */ 142 143 /* log2P is & 0x7 as never more than 7, and nv30/35 only uses 3 bits */ 144 pllvals->log2P = (pll1 >> 16) & 0x7; 145 pllvals->N2 = pllvals->M2 = 1; 146 147 if (reg1 <= 0x405c) { 148 pllvals->NM1 = pll2 & 0xffff; 149 /* single stage NVPLL and VPLLs use 1 << 8, MPLL uses 1 << 12 */ 150 if (!(pll1 & 0x1100)) 151 pllvals->NM2 = pll2 >> 16; 152 } else { 153 pllvals->NM1 = pll1 & 0xffff; 154 if (nv_two_reg_pll(dev) && pll2 & NV31_RAMDAC_ENABLE_VCO2) 155 pllvals->NM2 = pll2 & 0xffff; 156 else if (drm->client.device.info.chipset == 0x30 || drm->client.device.info.chipset == 0x35) { 157 pllvals->M1 &= 0xf; /* only 4 bits */ 158 if (pll1 & NV30_RAMDAC_ENABLE_VCO2) { 159 pllvals->M2 = (pll1 >> 4) & 0x7; 160 pllvals->N2 = ((pll1 >> 21) & 0x18) | 161 ((pll1 >> 19) & 0x7); 162 } 163 } 164 } 165 } 166 167 int 168 nouveau_hw_get_pllvals(struct drm_device *dev, enum nvbios_pll_type plltype, 169 struct nvkm_pll_vals *pllvals) 170 { 171 struct nouveau_drm *drm = nouveau_drm(dev); 172 struct nvif_object *device = &drm->client.device.object; 173 struct nvkm_bios *bios = nvxx_bios(&drm->client.device); 174 uint32_t reg1, pll1, pll2 = 0; 175 struct nvbios_pll pll_lim; 176 int ret; 177 178 ret = nvbios_pll_parse(bios, plltype, &pll_lim); 179 if (ret || !(reg1 = pll_lim.reg)) 180 return -ENOENT; 181 182 pll1 = nvif_rd32(device, reg1); 183 if (reg1 <= 0x405c) 184 pll2 = nvif_rd32(device, reg1 + 4); 185 else if (nv_two_reg_pll(dev)) { 186 uint32_t reg2 = reg1 + (reg1 == NV_RAMDAC_VPLL2 ? 0x5c : 0x70); 187 188 pll2 = nvif_rd32(device, reg2); 189 } 190 191 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CELSIUS && reg1 >= NV_PRAMDAC_VPLL_COEFF) { 192 uint32_t ramdac580 = NVReadRAMDAC(dev, 0, NV_PRAMDAC_580); 193 194 /* check whether vpll has been forced into single stage mode */ 195 if (reg1 == NV_PRAMDAC_VPLL_COEFF) { 196 if (ramdac580 & NV_RAMDAC_580_VPLL1_ACTIVE) 197 pll2 = 0; 198 } else 199 if (ramdac580 & NV_RAMDAC_580_VPLL2_ACTIVE) 200 pll2 = 0; 201 } 202 203 nouveau_hw_decode_pll(dev, reg1, pll1, pll2, pllvals); 204 pllvals->refclk = pll_lim.refclk; 205 return 0; 206 } 207 208 int 209 nouveau_hw_pllvals_to_clk(struct nvkm_pll_vals *pv) 210 { 211 /* Avoid divide by zero if called at an inappropriate time */ 212 if (!pv->M1 || !pv->M2) 213 return 0; 214 215 return pv->N1 * pv->N2 * pv->refclk / (pv->M1 * pv->M2) >> pv->log2P; 216 } 217 218 int 219 nouveau_hw_get_clock(struct drm_device *dev, enum nvbios_pll_type plltype) 220 { 221 struct nvkm_pll_vals pllvals; 222 int ret; 223 int domain; 224 225 domain = pci_domain_nr(dev->pdev->bus); 226 227 if (plltype == PLL_MEMORY && 228 (dev->pdev->device & 0x0ff0) == CHIPSET_NFORCE) { 229 uint32_t mpllP; 230 pci_read_config_dword(pci_get_domain_bus_and_slot(domain, 0, 3), 231 0x6c, &mpllP); 232 mpllP = (mpllP >> 8) & 0xf; 233 if (!mpllP) 234 mpllP = 4; 235 236 return 400000 / mpllP; 237 } else 238 if (plltype == PLL_MEMORY && 239 (dev->pdev->device & 0xff0) == CHIPSET_NFORCE2) { 240 uint32_t clock; 241 242 pci_read_config_dword(pci_get_domain_bus_and_slot(domain, 0, 5), 243 0x4c, &clock); 244 return clock / 1000; 245 } 246 247 ret = nouveau_hw_get_pllvals(dev, plltype, &pllvals); 248 if (ret) 249 return ret; 250 251 return nouveau_hw_pllvals_to_clk(&pllvals); 252 } 253 254 static void 255 nouveau_hw_fix_bad_vpll(struct drm_device *dev, int head) 256 { 257 /* the vpll on an unused head can come up with a random value, way 258 * beyond the pll limits. for some reason this causes the chip to 259 * lock up when reading the dac palette regs, so set a valid pll here 260 * when such a condition detected. only seen on nv11 to date 261 */ 262 263 struct nouveau_drm *drm = nouveau_drm(dev); 264 struct nvif_device *device = &drm->client.device; 265 struct nvkm_clk *clk = nvxx_clk(device); 266 struct nvkm_bios *bios = nvxx_bios(device); 267 struct nvbios_pll pll_lim; 268 struct nvkm_pll_vals pv; 269 enum nvbios_pll_type pll = head ? PLL_VPLL1 : PLL_VPLL0; 270 271 if (nvbios_pll_parse(bios, pll, &pll_lim)) 272 return; 273 nouveau_hw_get_pllvals(dev, pll, &pv); 274 275 if (pv.M1 >= pll_lim.vco1.min_m && pv.M1 <= pll_lim.vco1.max_m && 276 pv.N1 >= pll_lim.vco1.min_n && pv.N1 <= pll_lim.vco1.max_n && 277 pv.log2P <= pll_lim.max_p) 278 return; 279 280 NV_WARN(drm, "VPLL %d outwith limits, attempting to fix\n", head + 1); 281 282 /* set lowest clock within static limits */ 283 pv.M1 = pll_lim.vco1.max_m; 284 pv.N1 = pll_lim.vco1.min_n; 285 pv.log2P = pll_lim.max_p_usable; 286 clk->pll_prog(clk, pll_lim.reg, &pv); 287 } 288 289 /* 290 * vga font save/restore 291 */ 292 293 static void nouveau_vga_font_io(struct drm_device *dev, 294 #ifdef __NetBSD__ 295 bus_space_tag_t iovramt, 296 bus_space_handle_t iovramh, 297 #else 298 void __iomem *iovram, 299 #endif 300 bool save, unsigned plane) 301 { 302 unsigned i; 303 304 NVWriteVgaSeq(dev, 0, NV_VIO_SR_PLANE_MASK_INDEX, 1 << plane); 305 NVWriteVgaGr(dev, 0, NV_VIO_GX_READ_MAP_INDEX, plane); 306 for (i = 0; i < 16384; i++) { 307 if (save) { 308 #ifdef __NetBSD__ 309 nv04_display(dev)->saved_vga_font[plane][i] = 310 bus_space_read_stream_4(iovramt, iovramh, i * 4); 311 #else 312 nv04_display(dev)->saved_vga_font[plane][i] = 313 ioread32_native(iovram + i * 4); 314 #endif 315 } else { 316 #ifdef __NetBSD__ 317 bus_space_write_stream_4(iovramt, iovramh, i * 4, 318 nv04_display(dev)->saved_vga_font[plane][i]); 319 #else 320 iowrite32_native(nv04_display(dev)->saved_vga_font[plane][i], 321 iovram + i * 4); 322 #endif 323 } 324 } 325 } 326 327 void 328 nouveau_hw_save_vga_fonts(struct drm_device *dev, bool save) 329 { 330 struct nouveau_drm *drm = nouveau_drm(dev); 331 uint8_t misc, gr4, gr5, gr6, seq2, seq4; 332 bool graphicsmode; 333 unsigned plane; 334 #ifdef __NetBSD__ 335 bus_space_tag_t iovramt; 336 bus_space_handle_t iovramh; 337 bus_size_t iovramsz; 338 #else 339 void __iomem *iovram; 340 #endif 341 342 if (nv_two_heads(dev)) 343 NVSetOwner(dev, 0); 344 345 NVSetEnablePalette(dev, 0, true); 346 graphicsmode = NVReadVgaAttr(dev, 0, NV_CIO_AR_MODE_INDEX) & 1; 347 NVSetEnablePalette(dev, 0, false); 348 349 if (graphicsmode) /* graphics mode => framebuffer => no need to save */ 350 return; 351 352 NV_INFO(drm, "%sing VGA fonts\n", save ? "Sav" : "Restor"); 353 354 /* map first 64KiB of VRAM, holds VGA fonts etc */ 355 #ifdef __NetBSD__ 356 if (pci_mapreg_map(&dev->pdev->pd_pa, PCI_BAR(1), 357 pci_mapreg_type(dev->pdev->pd_pa.pa_pc, 358 dev->pdev->pd_pa.pa_tag, PCI_BAR(1)), 359 0, &iovramt, &iovramh, NULL, &iovramsz)) { 360 NV_ERROR(drm, "Failed to map VRAM, " 361 "cannot save/restore VGA fonts.\n"); 362 return; 363 } 364 #else 365 iovram = ioremap(pci_resource_start(dev->pdev, 1), 65536); 366 if (!iovram) { 367 NV_ERROR(drm, "Failed to map VRAM, " 368 "cannot save/restore VGA fonts.\n"); 369 return; 370 } 371 #endif 372 373 if (nv_two_heads(dev)) 374 NVBlankScreen(dev, 1, true); 375 NVBlankScreen(dev, 0, true); 376 377 /* save control regs */ 378 misc = NVReadPRMVIO(dev, 0, NV_PRMVIO_MISC__READ); 379 seq2 = NVReadVgaSeq(dev, 0, NV_VIO_SR_PLANE_MASK_INDEX); 380 seq4 = NVReadVgaSeq(dev, 0, NV_VIO_SR_MEM_MODE_INDEX); 381 gr4 = NVReadVgaGr(dev, 0, NV_VIO_GX_READ_MAP_INDEX); 382 gr5 = NVReadVgaGr(dev, 0, NV_VIO_GX_MODE_INDEX); 383 gr6 = NVReadVgaGr(dev, 0, NV_VIO_GX_MISC_INDEX); 384 385 NVWritePRMVIO(dev, 0, NV_PRMVIO_MISC__WRITE, 0x67); 386 NVWriteVgaSeq(dev, 0, NV_VIO_SR_MEM_MODE_INDEX, 0x6); 387 NVWriteVgaGr(dev, 0, NV_VIO_GX_MODE_INDEX, 0x0); 388 NVWriteVgaGr(dev, 0, NV_VIO_GX_MISC_INDEX, 0x5); 389 390 /* store font in planes 0..3 */ 391 for (plane = 0; plane < 4; plane++) 392 #ifdef __NetBSD__ 393 nouveau_vga_font_io(dev, iovramt, iovramh, save, plane); 394 #else 395 nouveau_vga_font_io(dev, iovram, save, plane); 396 #endif 397 398 /* restore control regs */ 399 NVWritePRMVIO(dev, 0, NV_PRMVIO_MISC__WRITE, misc); 400 NVWriteVgaGr(dev, 0, NV_VIO_GX_READ_MAP_INDEX, gr4); 401 NVWriteVgaGr(dev, 0, NV_VIO_GX_MODE_INDEX, gr5); 402 NVWriteVgaGr(dev, 0, NV_VIO_GX_MISC_INDEX, gr6); 403 NVWriteVgaSeq(dev, 0, NV_VIO_SR_PLANE_MASK_INDEX, seq2); 404 NVWriteVgaSeq(dev, 0, NV_VIO_SR_MEM_MODE_INDEX, seq4); 405 406 if (nv_two_heads(dev)) 407 NVBlankScreen(dev, 1, false); 408 NVBlankScreen(dev, 0, false); 409 410 #ifdef __NetBSD__ 411 bus_space_unmap(iovramt, iovramh, iovramsz); 412 #else 413 iounmap(iovram); 414 #endif 415 } 416 417 /* 418 * mode state save/load 419 */ 420 421 static void 422 rd_cio_state(struct drm_device *dev, int head, 423 struct nv04_crtc_reg *crtcstate, int index) 424 { 425 crtcstate->CRTC[index] = NVReadVgaCrtc(dev, head, index); 426 } 427 428 static void 429 wr_cio_state(struct drm_device *dev, int head, 430 struct nv04_crtc_reg *crtcstate, int index) 431 { 432 NVWriteVgaCrtc(dev, head, index, crtcstate->CRTC[index]); 433 } 434 435 static void 436 nv_save_state_ramdac(struct drm_device *dev, int head, 437 struct nv04_mode_state *state) 438 { 439 struct nouveau_drm *drm = nouveau_drm(dev); 440 struct nv04_crtc_reg *regp = &state->crtc_reg[head]; 441 int i; 442 443 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) 444 regp->nv10_cursync = NVReadRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC); 445 446 nouveau_hw_get_pllvals(dev, head ? PLL_VPLL1 : PLL_VPLL0, ®p->pllvals); 447 state->pllsel = NVReadRAMDAC(dev, 0, NV_PRAMDAC_PLL_COEFF_SELECT); 448 if (nv_two_heads(dev)) 449 state->sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK); 450 if (drm->client.device.info.chipset == 0x11) 451 regp->dither = NVReadRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11); 452 453 regp->ramdac_gen_ctrl = NVReadRAMDAC(dev, head, NV_PRAMDAC_GENERAL_CONTROL); 454 455 if (nv_gf4_disp_arch(dev)) 456 regp->ramdac_630 = NVReadRAMDAC(dev, head, NV_PRAMDAC_630); 457 if (drm->client.device.info.chipset >= 0x30) 458 regp->ramdac_634 = NVReadRAMDAC(dev, head, NV_PRAMDAC_634); 459 460 regp->tv_setup = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP); 461 regp->tv_vtotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VTOTAL); 462 regp->tv_vskew = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VSKEW); 463 regp->tv_vsync_delay = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VSYNC_DELAY); 464 regp->tv_htotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HTOTAL); 465 regp->tv_hskew = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSKEW); 466 regp->tv_hsync_delay = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY); 467 regp->tv_hsync_delay2 = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY2); 468 469 for (i = 0; i < 7; i++) { 470 uint32_t ramdac_reg = NV_PRAMDAC_FP_VDISPLAY_END + (i * 4); 471 regp->fp_vert_regs[i] = NVReadRAMDAC(dev, head, ramdac_reg); 472 regp->fp_horiz_regs[i] = NVReadRAMDAC(dev, head, ramdac_reg + 0x20); 473 } 474 475 if (nv_gf4_disp_arch(dev)) { 476 regp->dither = NVReadRAMDAC(dev, head, NV_RAMDAC_FP_DITHER); 477 for (i = 0; i < 3; i++) { 478 regp->dither_regs[i] = NVReadRAMDAC(dev, head, NV_PRAMDAC_850 + i * 4); 479 regp->dither_regs[i + 3] = NVReadRAMDAC(dev, head, NV_PRAMDAC_85C + i * 4); 480 } 481 } 482 483 regp->fp_control = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL); 484 regp->fp_debug_0 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_0); 485 if (!nv_gf4_disp_arch(dev) && head == 0) { 486 /* early chips don't allow access to PRAMDAC_TMDS_* without 487 * the head A FPCLK on (nv11 even locks up) */ 488 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_FP_DEBUG_0, regp->fp_debug_0 & 489 ~NV_PRAMDAC_FP_DEBUG_0_PWRDOWN_FPCLK); 490 } 491 regp->fp_debug_1 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_1); 492 regp->fp_debug_2 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_2); 493 494 regp->fp_margin_color = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_MARGIN_COLOR); 495 496 if (nv_gf4_disp_arch(dev)) 497 regp->ramdac_8c0 = NVReadRAMDAC(dev, head, NV_PRAMDAC_8C0); 498 499 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) { 500 regp->ramdac_a20 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A20); 501 regp->ramdac_a24 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A24); 502 regp->ramdac_a34 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A34); 503 504 for (i = 0; i < 38; i++) 505 regp->ctv_regs[i] = NVReadRAMDAC(dev, head, 506 NV_PRAMDAC_CTV + 4*i); 507 } 508 } 509 510 static void 511 nv_load_state_ramdac(struct drm_device *dev, int head, 512 struct nv04_mode_state *state) 513 { 514 struct nouveau_drm *drm = nouveau_drm(dev); 515 struct nvkm_clk *clk = nvxx_clk(&drm->client.device); 516 struct nv04_crtc_reg *regp = &state->crtc_reg[head]; 517 uint32_t pllreg = head ? NV_RAMDAC_VPLL2 : NV_PRAMDAC_VPLL_COEFF; 518 int i; 519 520 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) 521 NVWriteRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync); 522 523 clk->pll_prog(clk, pllreg, ®p->pllvals); 524 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_PLL_COEFF_SELECT, state->pllsel); 525 if (nv_two_heads(dev)) 526 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, state->sel_clk); 527 if (drm->client.device.info.chipset == 0x11) 528 NVWriteRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11, regp->dither); 529 530 NVWriteRAMDAC(dev, head, NV_PRAMDAC_GENERAL_CONTROL, regp->ramdac_gen_ctrl); 531 532 if (nv_gf4_disp_arch(dev)) 533 NVWriteRAMDAC(dev, head, NV_PRAMDAC_630, regp->ramdac_630); 534 if (drm->client.device.info.chipset >= 0x30) 535 NVWriteRAMDAC(dev, head, NV_PRAMDAC_634, regp->ramdac_634); 536 537 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP, regp->tv_setup); 538 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VTOTAL, regp->tv_vtotal); 539 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VSKEW, regp->tv_vskew); 540 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VSYNC_DELAY, regp->tv_vsync_delay); 541 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HTOTAL, regp->tv_htotal); 542 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSKEW, regp->tv_hskew); 543 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY, regp->tv_hsync_delay); 544 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY2, regp->tv_hsync_delay2); 545 546 for (i = 0; i < 7; i++) { 547 uint32_t ramdac_reg = NV_PRAMDAC_FP_VDISPLAY_END + (i * 4); 548 549 NVWriteRAMDAC(dev, head, ramdac_reg, regp->fp_vert_regs[i]); 550 NVWriteRAMDAC(dev, head, ramdac_reg + 0x20, regp->fp_horiz_regs[i]); 551 } 552 553 if (nv_gf4_disp_arch(dev)) { 554 NVWriteRAMDAC(dev, head, NV_RAMDAC_FP_DITHER, regp->dither); 555 for (i = 0; i < 3; i++) { 556 NVWriteRAMDAC(dev, head, NV_PRAMDAC_850 + i * 4, regp->dither_regs[i]); 557 NVWriteRAMDAC(dev, head, NV_PRAMDAC_85C + i * 4, regp->dither_regs[i + 3]); 558 } 559 } 560 561 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL, regp->fp_control); 562 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_0, regp->fp_debug_0); 563 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_1, regp->fp_debug_1); 564 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_2, regp->fp_debug_2); 565 566 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_MARGIN_COLOR, regp->fp_margin_color); 567 568 if (nv_gf4_disp_arch(dev)) 569 NVWriteRAMDAC(dev, head, NV_PRAMDAC_8C0, regp->ramdac_8c0); 570 571 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) { 572 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A20, regp->ramdac_a20); 573 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A24, regp->ramdac_a24); 574 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A34, regp->ramdac_a34); 575 576 for (i = 0; i < 38; i++) 577 NVWriteRAMDAC(dev, head, 578 NV_PRAMDAC_CTV + 4*i, regp->ctv_regs[i]); 579 } 580 } 581 582 static void 583 nv_save_state_vga(struct drm_device *dev, int head, 584 struct nv04_mode_state *state) 585 { 586 struct nv04_crtc_reg *regp = &state->crtc_reg[head]; 587 int i; 588 589 regp->MiscOutReg = NVReadPRMVIO(dev, head, NV_PRMVIO_MISC__READ); 590 591 for (i = 0; i < 25; i++) 592 rd_cio_state(dev, head, regp, i); 593 594 NVSetEnablePalette(dev, head, true); 595 for (i = 0; i < 21; i++) 596 regp->Attribute[i] = NVReadVgaAttr(dev, head, i); 597 NVSetEnablePalette(dev, head, false); 598 599 for (i = 0; i < 9; i++) 600 regp->Graphics[i] = NVReadVgaGr(dev, head, i); 601 602 for (i = 0; i < 5; i++) 603 regp->Sequencer[i] = NVReadVgaSeq(dev, head, i); 604 } 605 606 static void 607 nv_load_state_vga(struct drm_device *dev, int head, 608 struct nv04_mode_state *state) 609 { 610 struct nv04_crtc_reg *regp = &state->crtc_reg[head]; 611 int i; 612 613 NVWritePRMVIO(dev, head, NV_PRMVIO_MISC__WRITE, regp->MiscOutReg); 614 615 for (i = 0; i < 5; i++) 616 NVWriteVgaSeq(dev, head, i, regp->Sequencer[i]); 617 618 nv_lock_vga_crtc_base(dev, head, false); 619 for (i = 0; i < 25; i++) 620 wr_cio_state(dev, head, regp, i); 621 nv_lock_vga_crtc_base(dev, head, true); 622 623 for (i = 0; i < 9; i++) 624 NVWriteVgaGr(dev, head, i, regp->Graphics[i]); 625 626 NVSetEnablePalette(dev, head, true); 627 for (i = 0; i < 21; i++) 628 NVWriteVgaAttr(dev, head, i, regp->Attribute[i]); 629 NVSetEnablePalette(dev, head, false); 630 } 631 632 static void 633 nv_save_state_ext(struct drm_device *dev, int head, 634 struct nv04_mode_state *state) 635 { 636 struct nouveau_drm *drm = nouveau_drm(dev); 637 struct nv04_crtc_reg *regp = &state->crtc_reg[head]; 638 int i; 639 640 rd_cio_state(dev, head, regp, NV_CIO_CRE_LCD__INDEX); 641 rd_cio_state(dev, head, regp, NV_CIO_CRE_RPC0_INDEX); 642 rd_cio_state(dev, head, regp, NV_CIO_CRE_RPC1_INDEX); 643 rd_cio_state(dev, head, regp, NV_CIO_CRE_LSR_INDEX); 644 rd_cio_state(dev, head, regp, NV_CIO_CRE_PIXEL_INDEX); 645 rd_cio_state(dev, head, regp, NV_CIO_CRE_HEB__INDEX); 646 rd_cio_state(dev, head, regp, NV_CIO_CRE_ENH_INDEX); 647 648 rd_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX); 649 rd_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX); 650 rd_cio_state(dev, head, regp, NV_CIO_CRE_21); 651 652 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_KELVIN) 653 rd_cio_state(dev, head, regp, NV_CIO_CRE_47); 654 655 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_RANKINE) 656 rd_cio_state(dev, head, regp, 0x9f); 657 658 rd_cio_state(dev, head, regp, NV_CIO_CRE_49); 659 rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX); 660 rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX); 661 rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX); 662 rd_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX); 663 664 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) { 665 regp->crtc_830 = NVReadCRTC(dev, head, NV_PCRTC_830); 666 regp->crtc_834 = NVReadCRTC(dev, head, NV_PCRTC_834); 667 668 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_RANKINE) 669 regp->gpio_ext = NVReadCRTC(dev, head, NV_PCRTC_GPIO_EXT); 670 671 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) 672 regp->crtc_850 = NVReadCRTC(dev, head, NV_PCRTC_850); 673 674 if (nv_two_heads(dev)) 675 regp->crtc_eng_ctrl = NVReadCRTC(dev, head, NV_PCRTC_ENGINE_CTRL); 676 regp->cursor_cfg = NVReadCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG); 677 } 678 679 regp->crtc_cfg = NVReadCRTC(dev, head, NV_PCRTC_CONFIG); 680 681 rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX); 682 rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX); 683 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) { 684 rd_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX); 685 rd_cio_state(dev, head, regp, NV_CIO_CRE_CSB); 686 rd_cio_state(dev, head, regp, NV_CIO_CRE_4B); 687 rd_cio_state(dev, head, regp, NV_CIO_CRE_TVOUT_LATENCY); 688 } 689 /* NV11 and NV20 don't have this, they stop at 0x52. */ 690 if (nv_gf4_disp_arch(dev)) { 691 rd_cio_state(dev, head, regp, NV_CIO_CRE_42); 692 rd_cio_state(dev, head, regp, NV_CIO_CRE_53); 693 rd_cio_state(dev, head, regp, NV_CIO_CRE_54); 694 695 for (i = 0; i < 0x10; i++) 696 regp->CR58[i] = NVReadVgaCrtc5758(dev, head, i); 697 rd_cio_state(dev, head, regp, NV_CIO_CRE_59); 698 rd_cio_state(dev, head, regp, NV_CIO_CRE_5B); 699 700 rd_cio_state(dev, head, regp, NV_CIO_CRE_85); 701 rd_cio_state(dev, head, regp, NV_CIO_CRE_86); 702 } 703 704 regp->fb_start = NVReadCRTC(dev, head, NV_PCRTC_START); 705 } 706 707 static void 708 nv_load_state_ext(struct drm_device *dev, int head, 709 struct nv04_mode_state *state) 710 { 711 struct nouveau_drm *drm = nouveau_drm(dev); 712 struct nvif_object *device = &drm->client.device.object; 713 struct nv04_crtc_reg *regp = &state->crtc_reg[head]; 714 uint32_t reg900; 715 int i; 716 717 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) { 718 if (nv_two_heads(dev)) 719 /* setting ENGINE_CTRL (EC) *must* come before 720 * CIO_CRE_LCD, as writing CRE_LCD sets bits 16 & 17 in 721 * EC that should not be overwritten by writing stale EC 722 */ 723 NVWriteCRTC(dev, head, NV_PCRTC_ENGINE_CTRL, regp->crtc_eng_ctrl); 724 725 nvif_wr32(device, NV_PVIDEO_STOP, 1); 726 nvif_wr32(device, NV_PVIDEO_INTR_EN, 0); 727 nvif_wr32(device, NV_PVIDEO_OFFSET_BUFF(0), 0); 728 nvif_wr32(device, NV_PVIDEO_OFFSET_BUFF(1), 0); 729 nvif_wr32(device, NV_PVIDEO_LIMIT(0), drm->client.device.info.ram_size - 1); 730 nvif_wr32(device, NV_PVIDEO_LIMIT(1), drm->client.device.info.ram_size - 1); 731 nvif_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(0), drm->client.device.info.ram_size - 1); 732 nvif_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(1), drm->client.device.info.ram_size - 1); 733 nvif_wr32(device, NV_PBUS_POWERCTRL_2, 0); 734 735 NVWriteCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG, regp->cursor_cfg); 736 NVWriteCRTC(dev, head, NV_PCRTC_830, regp->crtc_830); 737 NVWriteCRTC(dev, head, NV_PCRTC_834, regp->crtc_834); 738 739 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_RANKINE) 740 NVWriteCRTC(dev, head, NV_PCRTC_GPIO_EXT, regp->gpio_ext); 741 742 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) { 743 NVWriteCRTC(dev, head, NV_PCRTC_850, regp->crtc_850); 744 745 reg900 = NVReadRAMDAC(dev, head, NV_PRAMDAC_900); 746 if (regp->crtc_cfg == NV10_PCRTC_CONFIG_START_ADDRESS_HSYNC) 747 NVWriteRAMDAC(dev, head, NV_PRAMDAC_900, reg900 | 0x10000); 748 else 749 NVWriteRAMDAC(dev, head, NV_PRAMDAC_900, reg900 & ~0x10000); 750 } 751 } 752 753 NVWriteCRTC(dev, head, NV_PCRTC_CONFIG, regp->crtc_cfg); 754 755 wr_cio_state(dev, head, regp, NV_CIO_CRE_RPC0_INDEX); 756 wr_cio_state(dev, head, regp, NV_CIO_CRE_RPC1_INDEX); 757 wr_cio_state(dev, head, regp, NV_CIO_CRE_LSR_INDEX); 758 wr_cio_state(dev, head, regp, NV_CIO_CRE_PIXEL_INDEX); 759 wr_cio_state(dev, head, regp, NV_CIO_CRE_LCD__INDEX); 760 wr_cio_state(dev, head, regp, NV_CIO_CRE_HEB__INDEX); 761 wr_cio_state(dev, head, regp, NV_CIO_CRE_ENH_INDEX); 762 wr_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX); 763 wr_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX); 764 765 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_KELVIN) 766 wr_cio_state(dev, head, regp, NV_CIO_CRE_47); 767 768 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_RANKINE) 769 wr_cio_state(dev, head, regp, 0x9f); 770 771 wr_cio_state(dev, head, regp, NV_CIO_CRE_49); 772 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX); 773 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX); 774 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX); 775 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) 776 nv_fix_nv40_hw_cursor(dev, head); 777 wr_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX); 778 779 wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX); 780 wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX); 781 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) { 782 wr_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX); 783 wr_cio_state(dev, head, regp, NV_CIO_CRE_CSB); 784 wr_cio_state(dev, head, regp, NV_CIO_CRE_4B); 785 wr_cio_state(dev, head, regp, NV_CIO_CRE_TVOUT_LATENCY); 786 } 787 /* NV11 and NV20 stop at 0x52. */ 788 if (nv_gf4_disp_arch(dev)) { 789 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_KELVIN) { 790 /* Not waiting for vertical retrace before modifying 791 CRE_53/CRE_54 causes lockups. */ 792 nvif_msec(&drm->client.device, 650, 793 if ( (nvif_rd32(device, NV_PRMCIO_INP0__COLOR) & 8)) 794 break; 795 ); 796 nvif_msec(&drm->client.device, 650, 797 if (!(nvif_rd32(device, NV_PRMCIO_INP0__COLOR) & 8)) 798 break; 799 ); 800 } 801 802 wr_cio_state(dev, head, regp, NV_CIO_CRE_42); 803 wr_cio_state(dev, head, regp, NV_CIO_CRE_53); 804 wr_cio_state(dev, head, regp, NV_CIO_CRE_54); 805 806 for (i = 0; i < 0x10; i++) 807 NVWriteVgaCrtc5758(dev, head, i, regp->CR58[i]); 808 wr_cio_state(dev, head, regp, NV_CIO_CRE_59); 809 wr_cio_state(dev, head, regp, NV_CIO_CRE_5B); 810 811 wr_cio_state(dev, head, regp, NV_CIO_CRE_85); 812 wr_cio_state(dev, head, regp, NV_CIO_CRE_86); 813 } 814 815 NVWriteCRTC(dev, head, NV_PCRTC_START, regp->fb_start); 816 } 817 818 static void 819 nv_save_state_palette(struct drm_device *dev, int head, 820 struct nv04_mode_state *state) 821 { 822 struct nvif_object *device = &nouveau_drm(dev)->client.device.object; 823 int head_offset = head * NV_PRMDIO_SIZE, i; 824 825 nvif_wr08(device, NV_PRMDIO_PIXEL_MASK + head_offset, 826 NV_PRMDIO_PIXEL_MASK_MASK); 827 nvif_wr08(device, NV_PRMDIO_READ_MODE_ADDRESS + head_offset, 0x0); 828 829 for (i = 0; i < 768; i++) { 830 state->crtc_reg[head].DAC[i] = nvif_rd08(device, 831 NV_PRMDIO_PALETTE_DATA + head_offset); 832 } 833 834 NVSetEnablePalette(dev, head, false); 835 } 836 837 void 838 nouveau_hw_load_state_palette(struct drm_device *dev, int head, 839 struct nv04_mode_state *state) 840 { 841 struct nvif_object *device = &nouveau_drm(dev)->client.device.object; 842 int head_offset = head * NV_PRMDIO_SIZE, i; 843 844 nvif_wr08(device, NV_PRMDIO_PIXEL_MASK + head_offset, 845 NV_PRMDIO_PIXEL_MASK_MASK); 846 nvif_wr08(device, NV_PRMDIO_WRITE_MODE_ADDRESS + head_offset, 0x0); 847 848 for (i = 0; i < 768; i++) { 849 nvif_wr08(device, NV_PRMDIO_PALETTE_DATA + head_offset, 850 state->crtc_reg[head].DAC[i]); 851 } 852 853 NVSetEnablePalette(dev, head, false); 854 } 855 856 void nouveau_hw_save_state(struct drm_device *dev, int head, 857 struct nv04_mode_state *state) 858 { 859 struct nouveau_drm *drm = nouveau_drm(dev); 860 861 if (drm->client.device.info.chipset == 0x11) 862 /* NB: no attempt is made to restore the bad pll later on */ 863 nouveau_hw_fix_bad_vpll(dev, head); 864 nv_save_state_ramdac(dev, head, state); 865 nv_save_state_vga(dev, head, state); 866 nv_save_state_palette(dev, head, state); 867 nv_save_state_ext(dev, head, state); 868 } 869 870 void nouveau_hw_load_state(struct drm_device *dev, int head, 871 struct nv04_mode_state *state) 872 { 873 NVVgaProtect(dev, head, true); 874 nv_load_state_ramdac(dev, head, state); 875 nv_load_state_ext(dev, head, state); 876 nouveau_hw_load_state_palette(dev, head, state); 877 nv_load_state_vga(dev, head, state); 878 NVVgaProtect(dev, head, false); 879 } 880
Indexes created Sun Sep 21 20:09:37 GMT 2025