1 /* Subroutines used for code generation for RISC-V. 2 Copyright (C) 2011-2022 Free Software Foundation, Inc. 3 Contributed by Andrew Waterman (andrew (at) sifive.com). 4 Based on MIPS target for GNU compiler. 5 6 This file is part of GCC. 7 8 GCC is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3, or (at your option) 11 any later version. 12 13 GCC is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with GCC; see the file COPYING3. If not see 20 <http://www.gnu.org/licenses/>. */ 21 22 #define IN_TARGET_CODE 1 23 24 #define INCLUDE_STRING 25 #include "config.h" 26 #include "system.h" 27 #include "coretypes.h" 28 #include "tm.h" 29 #include "rtl.h" 30 #include "regs.h" 31 #include "insn-config.h" 32 #include "insn-attr.h" 33 #include "recog.h" 34 #include "output.h" 35 #include "alias.h" 36 #include "tree.h" 37 #include "stringpool.h" 38 #include "attribs.h" 39 #include "varasm.h" 40 #include "stor-layout.h" 41 #include "calls.h" 42 #include "function.h" 43 #include "explow.h" 44 #include "memmodel.h" 45 #include "emit-rtl.h" 46 #include "reload.h" 47 #include "tm_p.h" 48 #include "target.h" 49 #include "target-def.h" 50 #include "basic-block.h" 51 #include "expr.h" 52 #include "optabs.h" 53 #include "bitmap.h" 54 #include "df.h" 55 #include "diagnostic.h" 56 #include "builtins.h" 57 #include "predict.h" 58 #include "tree-pass.h" 59 #include "opts.h" 60 61 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */ 62 #define UNSPEC_ADDRESS_P(X) \ 63 (GET_CODE (X) == UNSPEC \ 64 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \ 65 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES) 66 67 /* Extract the symbol or label from UNSPEC wrapper X. */ 68 #define UNSPEC_ADDRESS(X) \ 69 XVECEXP (X, 0, 0) 70 71 /* Extract the symbol type from UNSPEC wrapper X. */ 72 #define UNSPEC_ADDRESS_TYPE(X) \ 73 ((enum riscv_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST)) 74 75 /* True if bit BIT is set in VALUE. */ 76 #define BITSET_P(VALUE, BIT) (((VALUE) & (1ULL << (BIT))) != 0) 77 78 /* Classifies an address. 79 80 ADDRESS_REG 81 A natural register + offset address. The register satisfies 82 riscv_valid_base_register_p and the offset is a const_arith_operand. 83 84 ADDRESS_LO_SUM 85 A LO_SUM rtx. The first operand is a valid base register and 86 the second operand is a symbolic address. 87 88 ADDRESS_CONST_INT 89 A signed 16-bit constant address. 90 91 ADDRESS_SYMBOLIC: 92 A constant symbolic address. */ 93 enum riscv_address_type { 94 ADDRESS_REG, 95 ADDRESS_LO_SUM, 96 ADDRESS_CONST_INT, 97 ADDRESS_SYMBOLIC 98 }; 99 100 /* Information about a function's frame layout. */ 101 struct GTY(()) riscv_frame_info { 102 /* The size of the frame in bytes. */ 103 HOST_WIDE_INT total_size; 104 105 /* Bit X is set if the function saves or restores GPR X. */ 106 unsigned int mask; 107 108 /* Likewise FPR X. */ 109 unsigned int fmask; 110 111 /* How much the GPR save/restore routines adjust sp (or 0 if unused). */ 112 unsigned save_libcall_adjustment; 113 114 /* Offsets of fixed-point and floating-point save areas from frame bottom */ 115 HOST_WIDE_INT gp_sp_offset; 116 HOST_WIDE_INT fp_sp_offset; 117 118 /* Offset of virtual frame pointer from stack pointer/frame bottom */ 119 HOST_WIDE_INT frame_pointer_offset; 120 121 /* Offset of hard frame pointer from stack pointer/frame bottom */ 122 HOST_WIDE_INT hard_frame_pointer_offset; 123 124 /* The offset of arg_pointer_rtx from the bottom of the frame. */ 125 HOST_WIDE_INT arg_pointer_offset; 126 }; 127 128 enum riscv_privilege_levels { 129 UNKNOWN_MODE, USER_MODE, SUPERVISOR_MODE, MACHINE_MODE 130 }; 131 132 struct GTY(()) machine_function { 133 /* The number of extra stack bytes taken up by register varargs. 134 This area is allocated by the callee at the very top of the frame. */ 135 int varargs_size; 136 137 /* True if current function is a naked function. */ 138 bool naked_p; 139 140 /* True if current function is an interrupt function. */ 141 bool interrupt_handler_p; 142 /* For an interrupt handler, indicates the privilege level. */ 143 enum riscv_privilege_levels interrupt_mode; 144 145 /* True if attributes on current function have been checked. */ 146 bool attributes_checked_p; 147 148 /* The current frame information, calculated by riscv_compute_frame_info. */ 149 struct riscv_frame_info frame; 150 }; 151 152 /* Information about a single argument. */ 153 struct riscv_arg_info { 154 /* True if the argument is at least partially passed on the stack. */ 155 bool stack_p; 156 157 /* The number of integer registers allocated to this argument. */ 158 unsigned int num_gprs; 159 160 /* The offset of the first register used, provided num_gprs is nonzero. 161 If passed entirely on the stack, the value is MAX_ARGS_IN_REGISTERS. */ 162 unsigned int gpr_offset; 163 164 /* The number of floating-point registers allocated to this argument. */ 165 unsigned int num_fprs; 166 167 /* The offset of the first register used, provided num_fprs is nonzero. */ 168 unsigned int fpr_offset; 169 }; 170 171 /* Information about an address described by riscv_address_type. 172 173 ADDRESS_CONST_INT 174 No fields are used. 175 176 ADDRESS_REG 177 REG is the base register and OFFSET is the constant offset. 178 179 ADDRESS_LO_SUM 180 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE 181 is the type of symbol it references. 182 183 ADDRESS_SYMBOLIC 184 SYMBOL_TYPE is the type of symbol that the address references. */ 185 struct riscv_address_info { 186 enum riscv_address_type type; 187 rtx reg; 188 rtx offset; 189 enum riscv_symbol_type symbol_type; 190 }; 191 192 /* One stage in a constant building sequence. These sequences have 193 the form: 194 195 A = VALUE[0] 196 A = A CODE[1] VALUE[1] 197 A = A CODE[2] VALUE[2] 198 ... 199 200 where A is an accumulator, each CODE[i] is a binary rtl operation 201 and each VALUE[i] is a constant integer. CODE[0] is undefined. */ 202 struct riscv_integer_op { 203 enum rtx_code code; 204 unsigned HOST_WIDE_INT value; 205 }; 206 207 /* The largest number of operations needed to load an integer constant. 208 The worst case is LUI, ADDI, SLLI, ADDI, SLLI, ADDI, SLLI, ADDI. */ 209 #define RISCV_MAX_INTEGER_OPS 8 210 211 /* Costs of various operations on the different architectures. */ 212 213 struct riscv_tune_param 214 { 215 unsigned short fp_add[2]; 216 unsigned short fp_mul[2]; 217 unsigned short fp_div[2]; 218 unsigned short int_mul[2]; 219 unsigned short int_div[2]; 220 unsigned short issue_rate; 221 unsigned short branch_cost; 222 unsigned short memory_cost; 223 unsigned short fmv_cost; 224 bool slow_unaligned_access; 225 }; 226 227 /* Information about one micro-arch we know about. */ 228 struct riscv_tune_info { 229 /* This micro-arch canonical name. */ 230 const char *name; 231 232 /* Which automaton to use for tuning. */ 233 enum riscv_microarchitecture_type microarchitecture; 234 235 /* Tuning parameters for this micro-arch. */ 236 const struct riscv_tune_param *tune_param; 237 }; 238 239 /* Global variables for machine-dependent things. */ 240 241 /* Whether unaligned accesses execute very slowly. */ 242 bool riscv_slow_unaligned_access_p; 243 244 /* Stack alignment to assume/maintain. */ 245 unsigned riscv_stack_boundary; 246 247 /* If non-zero, this is an offset to be added to SP to redefine the CFA 248 when restoring the FP register from the stack. Only valid when generating 249 the epilogue. */ 250 static int epilogue_cfa_sp_offset; 251 252 /* Which tuning parameters to use. */ 253 static const struct riscv_tune_param *tune_param; 254 255 /* Which automaton to use for tuning. */ 256 enum riscv_microarchitecture_type riscv_microarchitecture; 257 258 /* Index R is the smallest register class that contains register R. */ 259 const enum reg_class riscv_regno_to_class[FIRST_PSEUDO_REGISTER] = { 260 GR_REGS, GR_REGS, GR_REGS, GR_REGS, 261 GR_REGS, GR_REGS, SIBCALL_REGS, SIBCALL_REGS, 262 JALR_REGS, JALR_REGS, SIBCALL_REGS, SIBCALL_REGS, 263 SIBCALL_REGS, SIBCALL_REGS, SIBCALL_REGS, SIBCALL_REGS, 264 SIBCALL_REGS, SIBCALL_REGS, JALR_REGS, JALR_REGS, 265 JALR_REGS, JALR_REGS, JALR_REGS, JALR_REGS, 266 JALR_REGS, JALR_REGS, JALR_REGS, JALR_REGS, 267 SIBCALL_REGS, SIBCALL_REGS, SIBCALL_REGS, SIBCALL_REGS, 268 FP_REGS, FP_REGS, FP_REGS, FP_REGS, 269 FP_REGS, FP_REGS, FP_REGS, FP_REGS, 270 FP_REGS, FP_REGS, FP_REGS, FP_REGS, 271 FP_REGS, FP_REGS, FP_REGS, FP_REGS, 272 FP_REGS, FP_REGS, FP_REGS, FP_REGS, 273 FP_REGS, FP_REGS, FP_REGS, FP_REGS, 274 FP_REGS, FP_REGS, FP_REGS, FP_REGS, 275 FP_REGS, FP_REGS, FP_REGS, FP_REGS, 276 FRAME_REGS, FRAME_REGS, 277 }; 278 279 /* Costs to use when optimizing for rocket. */ 280 static const struct riscv_tune_param rocket_tune_info = { 281 {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_add */ 282 {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_mul */ 283 {COSTS_N_INSNS (20), COSTS_N_INSNS (20)}, /* fp_div */ 284 {COSTS_N_INSNS (4), COSTS_N_INSNS (4)}, /* int_mul */ 285 {COSTS_N_INSNS (6), COSTS_N_INSNS (6)}, /* int_div */ 286 1, /* issue_rate */ 287 3, /* branch_cost */ 288 5, /* memory_cost */ 289 8, /* fmv_cost */ 290 true, /* slow_unaligned_access */ 291 }; 292 293 /* Costs to use when optimizing for Sifive 7 Series. */ 294 static const struct riscv_tune_param sifive_7_tune_info = { 295 {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_add */ 296 {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_mul */ 297 {COSTS_N_INSNS (20), COSTS_N_INSNS (20)}, /* fp_div */ 298 {COSTS_N_INSNS (4), COSTS_N_INSNS (4)}, /* int_mul */ 299 {COSTS_N_INSNS (6), COSTS_N_INSNS (6)}, /* int_div */ 300 2, /* issue_rate */ 301 4, /* branch_cost */ 302 3, /* memory_cost */ 303 8, /* fmv_cost */ 304 true, /* slow_unaligned_access */ 305 }; 306 307 /* Costs to use when optimizing for T-HEAD c906. */ 308 static const struct riscv_tune_param thead_c906_tune_info = { 309 {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_add */ 310 {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_mul */ 311 {COSTS_N_INSNS (20), COSTS_N_INSNS (20)}, /* fp_div */ 312 {COSTS_N_INSNS (4), COSTS_N_INSNS (4)}, /* int_mul */ 313 {COSTS_N_INSNS (6), COSTS_N_INSNS (6)}, /* int_div */ 314 1, /* issue_rate */ 315 3, /* branch_cost */ 316 5, /* memory_cost */ 317 8, /* fmv_cost */ 318 false, /* slow_unaligned_access */ 319 }; 320 321 /* Costs to use when optimizing for size. */ 322 static const struct riscv_tune_param optimize_size_tune_info = { 323 {COSTS_N_INSNS (1), COSTS_N_INSNS (1)}, /* fp_add */ 324 {COSTS_N_INSNS (1), COSTS_N_INSNS (1)}, /* fp_mul */ 325 {COSTS_N_INSNS (1), COSTS_N_INSNS (1)}, /* fp_div */ 326 {COSTS_N_INSNS (1), COSTS_N_INSNS (1)}, /* int_mul */ 327 {COSTS_N_INSNS (1), COSTS_N_INSNS (1)}, /* int_div */ 328 1, /* issue_rate */ 329 1, /* branch_cost */ 330 2, /* memory_cost */ 331 8, /* fmv_cost */ 332 false, /* slow_unaligned_access */ 333 }; 334 335 static tree riscv_handle_fndecl_attribute (tree *, tree, tree, int, bool *); 336 static tree riscv_handle_type_attribute (tree *, tree, tree, int, bool *); 337 338 /* Defining target-specific uses of __attribute__. */ 339 static const struct attribute_spec riscv_attribute_table[] = 340 { 341 /* Syntax: { name, min_len, max_len, decl_required, type_required, 342 function_type_required, affects_type_identity, handler, 343 exclude } */ 344 345 /* The attribute telling no prologue/epilogue. */ 346 { "naked", 0, 0, true, false, false, false, 347 riscv_handle_fndecl_attribute, NULL }, 348 /* This attribute generates prologue/epilogue for interrupt handlers. */ 349 { "interrupt", 0, 1, false, true, true, false, 350 riscv_handle_type_attribute, NULL }, 351 352 /* The last attribute spec is set to be NULL. */ 353 { NULL, 0, 0, false, false, false, false, NULL, NULL } 354 }; 355 356 /* Order for the CLOBBERs/USEs of gpr_save. */ 357 static const unsigned gpr_save_reg_order[] = { 358 INVALID_REGNUM, T0_REGNUM, T1_REGNUM, RETURN_ADDR_REGNUM, 359 S0_REGNUM, S1_REGNUM, S2_REGNUM, S3_REGNUM, S4_REGNUM, 360 S5_REGNUM, S6_REGNUM, S7_REGNUM, S8_REGNUM, S9_REGNUM, 361 S10_REGNUM, S11_REGNUM 362 }; 363 364 /* A table describing all the processors GCC knows about. */ 365 static const struct riscv_tune_info riscv_tune_info_table[] = { 366 { "rocket", generic, &rocket_tune_info }, 367 { "sifive-3-series", generic, &rocket_tune_info }, 368 { "sifive-5-series", generic, &rocket_tune_info }, 369 { "sifive-7-series", sifive_7, &sifive_7_tune_info }, 370 { "thead-c906", generic, &thead_c906_tune_info }, 371 { "size", generic, &optimize_size_tune_info }, 372 }; 373 374 /* Implement TARGET_MIN_ARITHMETIC_PRECISION. */ 375 376 static unsigned int 377 riscv_min_arithmetic_precision (void) 378 { 379 return 32; 380 } 381 382 /* Return the riscv_tune_info entry for the given name string. */ 383 384 static const struct riscv_tune_info * 385 riscv_parse_tune (const char *tune_string) 386 { 387 const riscv_cpu_info *cpu = riscv_find_cpu (tune_string); 388 389 if (cpu) 390 tune_string = cpu->tune; 391 392 for (unsigned i = 0; i < ARRAY_SIZE (riscv_tune_info_table); i++) 393 if (strcmp (riscv_tune_info_table[i].name, tune_string) == 0) 394 return riscv_tune_info_table + i; 395 396 error ("unknown cpu %qs for %<-mtune%>", tune_string); 397 return riscv_tune_info_table; 398 } 399 400 /* Helper function for riscv_build_integer; arguments are as for 401 riscv_build_integer. */ 402 403 static int 404 riscv_build_integer_1 (struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS], 405 HOST_WIDE_INT value, machine_mode mode) 406 { 407 HOST_WIDE_INT low_part = CONST_LOW_PART (value); 408 int cost = RISCV_MAX_INTEGER_OPS + 1, alt_cost; 409 struct riscv_integer_op alt_codes[RISCV_MAX_INTEGER_OPS]; 410 411 if (SMALL_OPERAND (value) || LUI_OPERAND (value)) 412 { 413 /* Simply ADDI or LUI. */ 414 codes[0].code = UNKNOWN; 415 codes[0].value = value; 416 return 1; 417 } 418 if (TARGET_ZBS && SINGLE_BIT_MASK_OPERAND (value)) 419 { 420 /* Simply BSETI. */ 421 codes[0].code = UNKNOWN; 422 codes[0].value = value; 423 424 /* RISC-V sign-extends all 32bit values that live in a 32bit 425 register. To avoid paradoxes, we thus need to use the 426 sign-extended (negative) representation (-1 << 31) for the 427 value, if we want to build (1 << 31) in SImode. This will 428 then expand to an LUI instruction. */ 429 if (mode == SImode && value == (HOST_WIDE_INT_1U << 31)) 430 codes[0].value = (HOST_WIDE_INT_M1U << 31); 431 432 return 1; 433 } 434 435 /* End with ADDI. When constructing HImode constants, do not generate any 436 intermediate value that is not itself a valid HImode constant. The 437 XORI case below will handle those remaining HImode constants. */ 438 if (low_part != 0 439 && (mode != HImode 440 || value - low_part <= ((1 << (GET_MODE_BITSIZE (HImode) - 1)) - 1))) 441 { 442 alt_cost = 1 + riscv_build_integer_1 (alt_codes, value - low_part, mode); 443 if (alt_cost < cost) 444 { 445 alt_codes[alt_cost-1].code = PLUS; 446 alt_codes[alt_cost-1].value = low_part; 447 memcpy (codes, alt_codes, sizeof (alt_codes)); 448 cost = alt_cost; 449 } 450 } 451 452 /* End with XORI. */ 453 if (cost > 2 && (low_part < 0 || mode == HImode)) 454 { 455 alt_cost = 1 + riscv_build_integer_1 (alt_codes, value ^ low_part, mode); 456 if (alt_cost < cost) 457 { 458 alt_codes[alt_cost-1].code = XOR; 459 alt_codes[alt_cost-1].value = low_part; 460 memcpy (codes, alt_codes, sizeof (alt_codes)); 461 cost = alt_cost; 462 } 463 } 464 465 /* Eliminate trailing zeros and end with SLLI. */ 466 if (cost > 2 && (value & 1) == 0) 467 { 468 int shift = ctz_hwi (value); 469 unsigned HOST_WIDE_INT x = value; 470 x = sext_hwi (x >> shift, HOST_BITS_PER_WIDE_INT - shift); 471 472 /* Don't eliminate the lower 12 bits if LUI might apply. */ 473 if (shift > IMM_BITS && !SMALL_OPERAND (x) && LUI_OPERAND (x << IMM_BITS)) 474 shift -= IMM_BITS, x <<= IMM_BITS; 475 476 alt_cost = 1 + riscv_build_integer_1 (alt_codes, x, mode); 477 if (alt_cost < cost) 478 { 479 alt_codes[alt_cost-1].code = ASHIFT; 480 alt_codes[alt_cost-1].value = shift; 481 memcpy (codes, alt_codes, sizeof (alt_codes)); 482 cost = alt_cost; 483 } 484 } 485 486 if (cost > 2 && TARGET_64BIT && TARGET_ZBB) 487 { 488 int leading_ones = clz_hwi (~value); 489 int trailing_ones = ctz_hwi (~value); 490 491 /* If all bits are one except a few that are zero, and the zero bits 492 are within a range of 11 bits, and at least one of the upper 32-bits 493 is a zero, then we can generate a constant by loading a small 494 negative constant and rotating. */ 495 if (leading_ones < 32 496 && ((64 - leading_ones - trailing_ones) < 12)) 497 { 498 codes[0].code = UNKNOWN; 499 /* The sign-bit might be zero, so just rotate to be safe. */ 500 codes[0].value = (((unsigned HOST_WIDE_INT) value >> trailing_ones) 501 | (value << (64 - trailing_ones))); 502 codes[1].code = ROTATERT; 503 codes[1].value = 64 - trailing_ones; 504 cost = 2; 505 } 506 /* Handle the case where the 11 bit range of zero bits wraps around. */ 507 else 508 { 509 int upper_trailing_ones = ctz_hwi (~value >> 32); 510 int lower_leading_ones = clz_hwi (~value << 32); 511 512 if (upper_trailing_ones < 32 && lower_leading_ones < 32 513 && ((64 - upper_trailing_ones - lower_leading_ones) < 12)) 514 { 515 codes[0].code = UNKNOWN; 516 /* The sign-bit might be zero, so just rotate to be safe. */ 517 codes[0].value = ((value << (32 - upper_trailing_ones)) 518 | ((unsigned HOST_WIDE_INT) value 519 >> (32 + upper_trailing_ones))); 520 codes[1].code = ROTATERT; 521 codes[1].value = 32 - upper_trailing_ones; 522 cost = 2; 523 } 524 } 525 } 526 527 gcc_assert (cost <= RISCV_MAX_INTEGER_OPS); 528 return cost; 529 } 530 531 /* Fill CODES with a sequence of rtl operations to load VALUE. 532 Return the number of operations needed. */ 533 534 static int 535 riscv_build_integer (struct riscv_integer_op *codes, HOST_WIDE_INT value, 536 machine_mode mode) 537 { 538 int cost = riscv_build_integer_1 (codes, value, mode); 539 540 /* Eliminate leading zeros and end with SRLI. */ 541 if (value > 0 && cost > 2) 542 { 543 struct riscv_integer_op alt_codes[RISCV_MAX_INTEGER_OPS]; 544 int alt_cost, shift = clz_hwi (value); 545 HOST_WIDE_INT shifted_val; 546 547 /* Try filling trailing bits with 1s. */ 548 shifted_val = (value << shift) | ((((HOST_WIDE_INT) 1) << shift) - 1); 549 alt_cost = 1 + riscv_build_integer_1 (alt_codes, shifted_val, mode); 550 if (alt_cost < cost) 551 { 552 alt_codes[alt_cost-1].code = LSHIFTRT; 553 alt_codes[alt_cost-1].value = shift; 554 memcpy (codes, alt_codes, sizeof (alt_codes)); 555 cost = alt_cost; 556 } 557 558 /* Try filling trailing bits with 0s. */ 559 shifted_val = value << shift; 560 alt_cost = 1 + riscv_build_integer_1 (alt_codes, shifted_val, mode); 561 if (alt_cost < cost) 562 { 563 alt_codes[alt_cost-1].code = LSHIFTRT; 564 alt_codes[alt_cost-1].value = shift; 565 memcpy (codes, alt_codes, sizeof (alt_codes)); 566 cost = alt_cost; 567 } 568 } 569 570 return cost; 571 } 572 573 /* Return the cost of constructing VAL in the event that a scratch 574 register is available. */ 575 576 static int 577 riscv_split_integer_cost (HOST_WIDE_INT val) 578 { 579 int cost; 580 unsigned HOST_WIDE_INT loval = sext_hwi (val, 32); 581 unsigned HOST_WIDE_INT hival = sext_hwi ((val - loval) >> 32, 32); 582 struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS]; 583 584 cost = 2 + riscv_build_integer (codes, loval, VOIDmode); 585 if (loval != hival) 586 cost += riscv_build_integer (codes, hival, VOIDmode); 587 588 return cost; 589 } 590 591 /* Return the cost of constructing the integer constant VAL. */ 592 593 static int 594 riscv_integer_cost (HOST_WIDE_INT val) 595 { 596 struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS]; 597 return MIN (riscv_build_integer (codes, val, VOIDmode), 598 riscv_split_integer_cost (val)); 599 } 600 601 /* Try to split a 64b integer into 32b parts, then reassemble. */ 602 603 static rtx 604 riscv_split_integer (HOST_WIDE_INT val, machine_mode mode) 605 { 606 unsigned HOST_WIDE_INT loval = sext_hwi (val, 32); 607 unsigned HOST_WIDE_INT hival = sext_hwi ((val - loval) >> 32, 32); 608 rtx hi = gen_reg_rtx (mode), lo = gen_reg_rtx (mode); 609 610 riscv_move_integer (hi, hi, hival, mode, FALSE); 611 riscv_move_integer (lo, lo, loval, mode, FALSE); 612 613 hi = gen_rtx_fmt_ee (ASHIFT, mode, hi, GEN_INT (32)); 614 hi = force_reg (mode, hi); 615 616 return gen_rtx_fmt_ee (PLUS, mode, hi, lo); 617 } 618 619 /* Return true if X is a thread-local symbol. */ 620 621 static bool 622 riscv_tls_symbol_p (const_rtx x) 623 { 624 return SYMBOL_REF_P (x) && SYMBOL_REF_TLS_MODEL (x) != 0; 625 } 626 627 /* Return true if symbol X binds locally. */ 628 629 static bool 630 riscv_symbol_binds_local_p (const_rtx x) 631 { 632 if (SYMBOL_REF_P (x)) 633 return (SYMBOL_REF_DECL (x) 634 ? targetm.binds_local_p (SYMBOL_REF_DECL (x)) 635 : SYMBOL_REF_LOCAL_P (x)); 636 else 637 return false; 638 } 639 640 /* Return the method that should be used to access SYMBOL_REF or 641 LABEL_REF X. */ 642 643 static enum riscv_symbol_type 644 riscv_classify_symbol (const_rtx x) 645 { 646 if (riscv_tls_symbol_p (x)) 647 return SYMBOL_TLS; 648 649 if (GET_CODE (x) == SYMBOL_REF && flag_pic && !riscv_symbol_binds_local_p (x)) 650 return SYMBOL_GOT_DISP; 651 652 return riscv_cmodel == CM_MEDLOW ? SYMBOL_ABSOLUTE : SYMBOL_PCREL; 653 } 654 655 /* Classify the base of symbolic expression X. */ 656 657 enum riscv_symbol_type 658 riscv_classify_symbolic_expression (rtx x) 659 { 660 rtx offset; 661 662 split_const (x, &x, &offset); 663 if (UNSPEC_ADDRESS_P (x)) 664 return UNSPEC_ADDRESS_TYPE (x); 665 666 return riscv_classify_symbol (x); 667 } 668 669 /* Return true if X is a symbolic constant. If it is, store the type of 670 the symbol in *SYMBOL_TYPE. */ 671 672 bool 673 riscv_symbolic_constant_p (rtx x, enum riscv_symbol_type *symbol_type) 674 { 675 rtx offset; 676 677 split_const (x, &x, &offset); 678 if (UNSPEC_ADDRESS_P (x)) 679 { 680 *symbol_type = UNSPEC_ADDRESS_TYPE (x); 681 x = UNSPEC_ADDRESS (x); 682 } 683 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF) 684 *symbol_type = riscv_classify_symbol (x); 685 else 686 return false; 687 688 if (offset == const0_rtx) 689 return true; 690 691 /* Nonzero offsets are only valid for references that don't use the GOT. */ 692 switch (*symbol_type) 693 { 694 case SYMBOL_ABSOLUTE: 695 case SYMBOL_PCREL: 696 case SYMBOL_TLS_LE: 697 /* GAS rejects offsets outside the range [-2^31, 2^31-1]. */ 698 return sext_hwi (INTVAL (offset), 32) == INTVAL (offset); 699 700 default: 701 return false; 702 } 703 } 704 705 /* Returns the number of instructions necessary to reference a symbol. */ 706 707 static int riscv_symbol_insns (enum riscv_symbol_type type) 708 { 709 switch (type) 710 { 711 case SYMBOL_TLS: return 0; /* Depends on the TLS model. */ 712 case SYMBOL_ABSOLUTE: return 2; /* LUI + the reference. */ 713 case SYMBOL_PCREL: return 2; /* AUIPC + the reference. */ 714 case SYMBOL_TLS_LE: return 3; /* LUI + ADD TP + the reference. */ 715 case SYMBOL_GOT_DISP: return 3; /* AUIPC + LD GOT + the reference. */ 716 default: gcc_unreachable (); 717 } 718 } 719 720 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */ 721 722 static bool 723 riscv_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED, rtx x) 724 { 725 return riscv_const_insns (x) > 0; 726 } 727 728 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */ 729 730 static bool 731 riscv_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED, rtx x) 732 { 733 enum riscv_symbol_type type; 734 rtx base, offset; 735 736 /* There is no assembler syntax for expressing an address-sized 737 high part. */ 738 if (GET_CODE (x) == HIGH) 739 return true; 740 741 split_const (x, &base, &offset); 742 if (riscv_symbolic_constant_p (base, &type)) 743 { 744 /* As an optimization, don't spill symbolic constants that are as 745 cheap to rematerialize as to access in the constant pool. */ 746 if (SMALL_OPERAND (INTVAL (offset)) && riscv_symbol_insns (type) > 0) 747 return true; 748 749 /* As an optimization, avoid needlessly generate dynamic relocations. */ 750 if (flag_pic) 751 return true; 752 } 753 754 /* TLS symbols must be computed by riscv_legitimize_move. */ 755 if (tls_referenced_p (x)) 756 return true; 757 758 return false; 759 } 760 761 /* Return true if register REGNO is a valid base register for mode MODE. 762 STRICT_P is true if REG_OK_STRICT is in effect. */ 763 764 int 765 riscv_regno_mode_ok_for_base_p (int regno, 766 machine_mode mode ATTRIBUTE_UNUSED, 767 bool strict_p) 768 { 769 if (!HARD_REGISTER_NUM_P (regno)) 770 { 771 if (!strict_p) 772 return true; 773 regno = reg_renumber[regno]; 774 } 775 776 /* These fake registers will be eliminated to either the stack or 777 hard frame pointer, both of which are usually valid base registers. 778 Reload deals with the cases where the eliminated form isn't valid. */ 779 if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM) 780 return true; 781 782 return GP_REG_P (regno); 783 } 784 785 /* Return true if X is a valid base register for mode MODE. 786 STRICT_P is true if REG_OK_STRICT is in effect. */ 787 788 static bool 789 riscv_valid_base_register_p (rtx x, machine_mode mode, bool strict_p) 790 { 791 if (!strict_p && GET_CODE (x) == SUBREG) 792 x = SUBREG_REG (x); 793 794 return (REG_P (x) 795 && riscv_regno_mode_ok_for_base_p (REGNO (x), mode, strict_p)); 796 } 797 798 /* Return true if, for every base register BASE_REG, (plus BASE_REG X) 799 can address a value of mode MODE. */ 800 801 static bool 802 riscv_valid_offset_p (rtx x, machine_mode mode) 803 { 804 /* Check that X is a signed 12-bit number. */ 805 if (!const_arith_operand (x, Pmode)) 806 return false; 807 808 /* We may need to split multiword moves, so make sure that every word 809 is accessible. */ 810 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD 811 && !SMALL_OPERAND (INTVAL (x) + GET_MODE_SIZE (mode) - UNITS_PER_WORD)) 812 return false; 813 814 return true; 815 } 816 817 /* Should a symbol of type SYMBOL_TYPE should be split in two? */ 818 819 bool 820 riscv_split_symbol_type (enum riscv_symbol_type symbol_type) 821 { 822 if (symbol_type == SYMBOL_TLS_LE) 823 return true; 824 825 if (!TARGET_EXPLICIT_RELOCS) 826 return false; 827 828 return symbol_type == SYMBOL_ABSOLUTE || symbol_type == SYMBOL_PCREL; 829 } 830 831 /* Return true if a LO_SUM can address a value of mode MODE when the 832 LO_SUM symbol has type SYM_TYPE. X is the LO_SUM second operand, which 833 is used when the mode is BLKmode. */ 834 835 static bool 836 riscv_valid_lo_sum_p (enum riscv_symbol_type sym_type, machine_mode mode, 837 rtx x) 838 { 839 int align, size; 840 841 /* Check that symbols of type SYMBOL_TYPE can be used to access values 842 of mode MODE. */ 843 if (riscv_symbol_insns (sym_type) == 0) 844 return false; 845 846 /* Check that there is a known low-part relocation. */ 847 if (!riscv_split_symbol_type (sym_type)) 848 return false; 849 850 /* We can't tell size or alignment when we have BLKmode, so try extracing a 851 decl from the symbol if possible. */ 852 if (mode == BLKmode) 853 { 854 rtx offset; 855 856 /* Extract the symbol from the LO_SUM operand, if any. */ 857 split_const (x, &x, &offset); 858 859 /* Might be a CODE_LABEL. We can compute align but not size for that, 860 so don't bother trying to handle it. */ 861 if (!SYMBOL_REF_P (x)) 862 return false; 863 864 /* Use worst case assumptions if we don't have a SYMBOL_REF_DECL. */ 865 align = (SYMBOL_REF_DECL (x) 866 ? DECL_ALIGN (SYMBOL_REF_DECL (x)) 867 : 1); 868 size = (SYMBOL_REF_DECL (x) && DECL_SIZE (SYMBOL_REF_DECL (x)) 869 ? tree_to_uhwi (DECL_SIZE (SYMBOL_REF_DECL (x))) 870 : 2*BITS_PER_WORD); 871 } 872 else 873 { 874 align = GET_MODE_ALIGNMENT (mode); 875 size = GET_MODE_BITSIZE (mode); 876 } 877 878 /* We may need to split multiword moves, so make sure that each word 879 can be accessed without inducing a carry. */ 880 if (size > BITS_PER_WORD 881 && (!TARGET_STRICT_ALIGN || size > align)) 882 return false; 883 884 return true; 885 } 886 887 /* Return true if X is a valid address for machine mode MODE. If it is, 888 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in 889 effect. */ 890 891 static bool 892 riscv_classify_address (struct riscv_address_info *info, rtx x, 893 machine_mode mode, bool strict_p) 894 { 895 switch (GET_CODE (x)) 896 { 897 case REG: 898 case SUBREG: 899 info->type = ADDRESS_REG; 900 info->reg = x; 901 info->offset = const0_rtx; 902 return riscv_valid_base_register_p (info->reg, mode, strict_p); 903 904 case PLUS: 905 info->type = ADDRESS_REG; 906 info->reg = XEXP (x, 0); 907 info->offset = XEXP (x, 1); 908 return (riscv_valid_base_register_p (info->reg, mode, strict_p) 909 && riscv_valid_offset_p (info->offset, mode)); 910 911 case LO_SUM: 912 info->type = ADDRESS_LO_SUM; 913 info->reg = XEXP (x, 0); 914 info->offset = XEXP (x, 1); 915 /* We have to trust the creator of the LO_SUM to do something vaguely 916 sane. Target-independent code that creates a LO_SUM should also 917 create and verify the matching HIGH. Target-independent code that 918 adds an offset to a LO_SUM must prove that the offset will not 919 induce a carry. Failure to do either of these things would be 920 a bug, and we are not required to check for it here. The RISC-V 921 backend itself should only create LO_SUMs for valid symbolic 922 constants, with the high part being either a HIGH or a copy 923 of _gp. */ 924 info->symbol_type 925 = riscv_classify_symbolic_expression (info->offset); 926 return (riscv_valid_base_register_p (info->reg, mode, strict_p) 927 && riscv_valid_lo_sum_p (info->symbol_type, mode, info->offset)); 928 929 case CONST_INT: 930 /* Small-integer addresses don't occur very often, but they 931 are legitimate if x0 is a valid base register. */ 932 info->type = ADDRESS_CONST_INT; 933 return SMALL_OPERAND (INTVAL (x)); 934 935 default: 936 return false; 937 } 938 } 939 940 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */ 941 942 static bool 943 riscv_legitimate_address_p (machine_mode mode, rtx x, bool strict_p) 944 { 945 struct riscv_address_info addr; 946 947 return riscv_classify_address (&addr, x, mode, strict_p); 948 } 949 950 /* Return true if hard reg REGNO can be used in compressed instructions. */ 951 952 static bool 953 riscv_compressed_reg_p (int regno) 954 { 955 /* x8-x15/f8-f15 are compressible registers. */ 956 return (TARGET_RVC && (IN_RANGE (regno, GP_REG_FIRST + 8, GP_REG_FIRST + 15) 957 || IN_RANGE (regno, FP_REG_FIRST + 8, FP_REG_FIRST + 15))); 958 } 959 960 /* Return true if x is an unsigned 5-bit immediate scaled by 4. */ 961 962 static bool 963 riscv_compressed_lw_offset_p (rtx x) 964 { 965 return (CONST_INT_P (x) 966 && (INTVAL (x) & 3) == 0 967 && IN_RANGE (INTVAL (x), 0, CSW_MAX_OFFSET)); 968 } 969 970 /* Return true if load/store from/to address x can be compressed. */ 971 972 static bool 973 riscv_compressed_lw_address_p (rtx x) 974 { 975 struct riscv_address_info addr; 976 bool result = riscv_classify_address (&addr, x, GET_MODE (x), 977 reload_completed); 978 979 /* Return false if address is not compressed_reg + small_offset. */ 980 if (!result 981 || addr.type != ADDRESS_REG 982 /* Before reload, assume all registers are OK. */ 983 || (reload_completed 984 && !riscv_compressed_reg_p (REGNO (addr.reg)) 985 && addr.reg != stack_pointer_rtx) 986 || !riscv_compressed_lw_offset_p (addr.offset)) 987 return false; 988 989 return result; 990 } 991 992 /* Return the number of instructions needed to load or store a value 993 of mode MODE at address X. Return 0 if X isn't valid for MODE. 994 Assume that multiword moves may need to be split into word moves 995 if MIGHT_SPLIT_P, otherwise assume that a single load or store is 996 enough. */ 997 998 int 999 riscv_address_insns (rtx x, machine_mode mode, bool might_split_p) 1000 { 1001 struct riscv_address_info addr = {}; 1002 int n = 1; 1003 1004 if (!riscv_classify_address (&addr, x, mode, false)) 1005 { 1006 /* This could be a pattern from the pic.md file. In which case we want 1007 this address to always have a cost of 3 to make it as expensive as the 1008 most expensive symbol. This prevents constant propagation from 1009 preferring symbols over register plus offset. */ 1010 return 3; 1011 } 1012 1013 /* BLKmode is used for single unaligned loads and stores and should 1014 not count as a multiword mode. */ 1015 if (mode != BLKmode && might_split_p) 1016 n += (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; 1017 1018 if (addr.type == ADDRESS_LO_SUM) 1019 n += riscv_symbol_insns (addr.symbol_type) - 1; 1020 1021 return n; 1022 } 1023 1024 /* Return the number of instructions needed to load constant X. 1025 Return 0 if X isn't a valid constant. */ 1026 1027 int 1028 riscv_const_insns (rtx x) 1029 { 1030 enum riscv_symbol_type symbol_type; 1031 rtx offset; 1032 1033 switch (GET_CODE (x)) 1034 { 1035 case HIGH: 1036 if (!riscv_symbolic_constant_p (XEXP (x, 0), &symbol_type) 1037 || !riscv_split_symbol_type (symbol_type)) 1038 return 0; 1039 1040 /* This is simply an LUI. */ 1041 return 1; 1042 1043 case CONST_INT: 1044 { 1045 int cost = riscv_integer_cost (INTVAL (x)); 1046 /* Force complicated constants to memory. */ 1047 return cost < 4 ? cost : 0; 1048 } 1049 1050 case CONST_DOUBLE: 1051 case CONST_VECTOR: 1052 /* We can use x0 to load floating-point zero. */ 1053 return x == CONST0_RTX (GET_MODE (x)) ? 1 : 0; 1054 1055 case CONST: 1056 /* See if we can refer to X directly. */ 1057 if (riscv_symbolic_constant_p (x, &symbol_type)) 1058 return riscv_symbol_insns (symbol_type); 1059 1060 /* Otherwise try splitting the constant into a base and offset. */ 1061 split_const (x, &x, &offset); 1062 if (offset != 0) 1063 { 1064 int n = riscv_const_insns (x); 1065 if (n != 0) 1066 return n + riscv_integer_cost (INTVAL (offset)); 1067 } 1068 return 0; 1069 1070 case SYMBOL_REF: 1071 case LABEL_REF: 1072 return riscv_symbol_insns (riscv_classify_symbol (x)); 1073 1074 default: 1075 return 0; 1076 } 1077 } 1078 1079 /* X is a doubleword constant that can be handled by splitting it into 1080 two words and loading each word separately. Return the number of 1081 instructions required to do this. */ 1082 1083 int 1084 riscv_split_const_insns (rtx x) 1085 { 1086 unsigned int low, high; 1087 1088 low = riscv_const_insns (riscv_subword (x, false)); 1089 high = riscv_const_insns (riscv_subword (x, true)); 1090 gcc_assert (low > 0 && high > 0); 1091 return low + high; 1092 } 1093 1094 /* Return the number of instructions needed to implement INSN, 1095 given that it loads from or stores to MEM. */ 1096 1097 int 1098 riscv_load_store_insns (rtx mem, rtx_insn *insn) 1099 { 1100 machine_mode mode; 1101 bool might_split_p; 1102 rtx set; 1103 1104 gcc_assert (MEM_P (mem)); 1105 mode = GET_MODE (mem); 1106 1107 /* Try to prove that INSN does not need to be split. */ 1108 might_split_p = true; 1109 if (GET_MODE_BITSIZE (mode) <= 32) 1110 might_split_p = false; 1111 else if (GET_MODE_BITSIZE (mode) == 64) 1112 { 1113 set = single_set (insn); 1114 if (set && !riscv_split_64bit_move_p (SET_DEST (set), SET_SRC (set))) 1115 might_split_p = false; 1116 } 1117 1118 return riscv_address_insns (XEXP (mem, 0), mode, might_split_p); 1119 } 1120 1121 /* Emit a move from SRC to DEST. Assume that the move expanders can 1122 handle all moves if !can_create_pseudo_p (). The distinction is 1123 important because, unlike emit_move_insn, the move expanders know 1124 how to force Pmode objects into the constant pool even when the 1125 constant pool address is not itself legitimate. */ 1126 1127 rtx 1128 riscv_emit_move (rtx dest, rtx src) 1129 { 1130 return (can_create_pseudo_p () 1131 ? emit_move_insn (dest, src) 1132 : emit_move_insn_1 (dest, src)); 1133 } 1134 1135 /* Emit an instruction of the form (set TARGET SRC). */ 1136 1137 static rtx 1138 riscv_emit_set (rtx target, rtx src) 1139 { 1140 emit_insn (gen_rtx_SET (target, src)); 1141 return target; 1142 } 1143 1144 /* Emit an instruction of the form (set DEST (CODE X Y)). */ 1145 1146 static rtx 1147 riscv_emit_binary (enum rtx_code code, rtx dest, rtx x, rtx y) 1148 { 1149 return riscv_emit_set (dest, gen_rtx_fmt_ee (code, GET_MODE (dest), x, y)); 1150 } 1151 1152 /* Compute (CODE X Y) and store the result in a new register 1153 of mode MODE. Return that new register. */ 1154 1155 static rtx 1156 riscv_force_binary (machine_mode mode, enum rtx_code code, rtx x, rtx y) 1157 { 1158 return riscv_emit_binary (code, gen_reg_rtx (mode), x, y); 1159 } 1160 1161 static rtx 1162 riscv_swap_instruction (rtx inst) 1163 { 1164 gcc_assert (GET_MODE (inst) == SImode); 1165 if (BYTES_BIG_ENDIAN) 1166 inst = expand_unop (SImode, bswap_optab, inst, gen_reg_rtx (SImode), 1); 1167 return inst; 1168 } 1169 1170 /* Copy VALUE to a register and return that register. If new pseudos 1171 are allowed, copy it into a new register, otherwise use DEST. */ 1172 1173 static rtx 1174 riscv_force_temporary (rtx dest, rtx value, bool in_splitter) 1175 { 1176 /* We can't call gen_reg_rtx from a splitter, because this might realloc 1177 the regno_reg_rtx array, which would invalidate reg rtx pointers in the 1178 combine undo buffer. */ 1179 if (can_create_pseudo_p () && !in_splitter) 1180 return force_reg (Pmode, value); 1181 else 1182 { 1183 riscv_emit_move (dest, value); 1184 return dest; 1185 } 1186 } 1187 1188 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE, 1189 then add CONST_INT OFFSET to the result. */ 1190 1191 static rtx 1192 riscv_unspec_address_offset (rtx base, rtx offset, 1193 enum riscv_symbol_type symbol_type) 1194 { 1195 base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base), 1196 UNSPEC_ADDRESS_FIRST + symbol_type); 1197 if (offset != const0_rtx) 1198 base = gen_rtx_PLUS (Pmode, base, offset); 1199 return gen_rtx_CONST (Pmode, base); 1200 } 1201 1202 /* Return an UNSPEC address with underlying address ADDRESS and symbol 1203 type SYMBOL_TYPE. */ 1204 1205 rtx 1206 riscv_unspec_address (rtx address, enum riscv_symbol_type symbol_type) 1207 { 1208 rtx base, offset; 1209 1210 split_const (address, &base, &offset); 1211 return riscv_unspec_address_offset (base, offset, symbol_type); 1212 } 1213 1214 /* If OP is an UNSPEC address, return the address to which it refers, 1215 otherwise return OP itself. */ 1216 1217 static rtx 1218 riscv_strip_unspec_address (rtx op) 1219 { 1220 rtx base, offset; 1221 1222 split_const (op, &base, &offset); 1223 if (UNSPEC_ADDRESS_P (base)) 1224 op = plus_constant (Pmode, UNSPEC_ADDRESS (base), INTVAL (offset)); 1225 return op; 1226 } 1227 1228 /* If riscv_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the 1229 high part to BASE and return the result. Just return BASE otherwise. 1230 TEMP is as for riscv_force_temporary. 1231 1232 The returned expression can be used as the first operand to a LO_SUM. */ 1233 1234 static rtx 1235 riscv_unspec_offset_high (rtx temp, rtx addr, enum riscv_symbol_type symbol_type) 1236 { 1237 addr = gen_rtx_HIGH (Pmode, riscv_unspec_address (addr, symbol_type)); 1238 return riscv_force_temporary (temp, addr, FALSE); 1239 } 1240 1241 /* Load an entry from the GOT for a TLS GD access. */ 1242 1243 static rtx riscv_got_load_tls_gd (rtx dest, rtx sym) 1244 { 1245 if (Pmode == DImode) 1246 return gen_got_load_tls_gddi (dest, sym); 1247 else 1248 return gen_got_load_tls_gdsi (dest, sym); 1249 } 1250 1251 /* Load an entry from the GOT for a TLS IE access. */ 1252 1253 static rtx riscv_got_load_tls_ie (rtx dest, rtx sym) 1254 { 1255 if (Pmode == DImode) 1256 return gen_got_load_tls_iedi (dest, sym); 1257 else 1258 return gen_got_load_tls_iesi (dest, sym); 1259 } 1260 1261 /* Add in the thread pointer for a TLS LE access. */ 1262 1263 static rtx riscv_tls_add_tp_le (rtx dest, rtx base, rtx sym) 1264 { 1265 rtx tp = gen_rtx_REG (Pmode, THREAD_POINTER_REGNUM); 1266 if (Pmode == DImode) 1267 return gen_tls_add_tp_ledi (dest, base, tp, sym); 1268 else 1269 return gen_tls_add_tp_lesi (dest, base, tp, sym); 1270 } 1271 1272 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise 1273 it appears in a MEM of that mode. Return true if ADDR is a legitimate 1274 constant in that context and can be split into high and low parts. 1275 If so, and if LOW_OUT is nonnull, emit the high part and store the 1276 low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise. 1277 1278 TEMP is as for riscv_force_temporary and is used to load the high 1279 part into a register. 1280 1281 When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be 1282 a legitimize SET_SRC for an .md pattern, otherwise the low part 1283 is guaranteed to be a legitimate address for mode MODE. */ 1284 1285 bool 1286 riscv_split_symbol (rtx temp, rtx addr, machine_mode mode, rtx *low_out, 1287 bool in_splitter) 1288 { 1289 enum riscv_symbol_type symbol_type; 1290 1291 if ((GET_CODE (addr) == HIGH && mode == MAX_MACHINE_MODE) 1292 || !riscv_symbolic_constant_p (addr, &symbol_type) 1293 || riscv_symbol_insns (symbol_type) == 0 1294 || !riscv_split_symbol_type (symbol_type)) 1295 return false; 1296 1297 if (low_out) 1298 switch (symbol_type) 1299 { 1300 case SYMBOL_ABSOLUTE: 1301 { 1302 rtx high = gen_rtx_HIGH (Pmode, copy_rtx (addr)); 1303 high = riscv_force_temporary (temp, high, in_splitter); 1304 *low_out = gen_rtx_LO_SUM (Pmode, high, addr); 1305 } 1306 break; 1307 1308 case SYMBOL_PCREL: 1309 { 1310 static unsigned seqno; 1311 char buf[32]; 1312 rtx label; 1313 1314 ssize_t bytes = snprintf (buf, sizeof (buf), ".LA%u", seqno); 1315 gcc_assert ((size_t) bytes < sizeof (buf)); 1316 1317 label = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); 1318 SYMBOL_REF_FLAGS (label) |= SYMBOL_FLAG_LOCAL; 1319 /* ??? Ugly hack to make weak symbols work. May need to change the 1320 RTL for the auipc and/or low patterns to get a better fix for 1321 this. */ 1322 if (! nonzero_address_p (addr)) 1323 SYMBOL_REF_WEAK (label) = 1; 1324 1325 if (temp == NULL) 1326 temp = gen_reg_rtx (Pmode); 1327 1328 if (Pmode == DImode) 1329 emit_insn (gen_auipcdi (temp, copy_rtx (addr), GEN_INT (seqno))); 1330 else 1331 emit_insn (gen_auipcsi (temp, copy_rtx (addr), GEN_INT (seqno))); 1332 1333 *low_out = gen_rtx_LO_SUM (Pmode, temp, label); 1334 1335 seqno++; 1336 } 1337 break; 1338 1339 default: 1340 gcc_unreachable (); 1341 } 1342 1343 return true; 1344 } 1345 1346 /* Return a legitimate address for REG + OFFSET. TEMP is as for 1347 riscv_force_temporary; it is only needed when OFFSET is not a 1348 SMALL_OPERAND. */ 1349 1350 static rtx 1351 riscv_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset) 1352 { 1353 if (!SMALL_OPERAND (offset)) 1354 { 1355 rtx high; 1356 1357 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH. 1358 The addition inside the macro CONST_HIGH_PART may cause an 1359 overflow, so we need to force a sign-extension check. */ 1360 high = gen_int_mode (CONST_HIGH_PART (offset), Pmode); 1361 offset = CONST_LOW_PART (offset); 1362 high = riscv_force_temporary (temp, high, FALSE); 1363 reg = riscv_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg), 1364 FALSE); 1365 } 1366 return plus_constant (Pmode, reg, offset); 1367 } 1368 1369 /* The __tls_get_attr symbol. */ 1370 static GTY(()) rtx riscv_tls_symbol; 1371 1372 /* Return an instruction sequence that calls __tls_get_addr. SYM is 1373 the TLS symbol we are referencing and TYPE is the symbol type to use 1374 (either global dynamic or local dynamic). RESULT is an RTX for the 1375 return value location. */ 1376 1377 static rtx_insn * 1378 riscv_call_tls_get_addr (rtx sym, rtx result) 1379 { 1380 rtx a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST), func; 1381 rtx_insn *insn; 1382 1383 if (!riscv_tls_symbol) 1384 riscv_tls_symbol = init_one_libfunc ("__tls_get_addr"); 1385 func = gen_rtx_MEM (FUNCTION_MODE, riscv_tls_symbol); 1386 1387 start_sequence (); 1388 1389 emit_insn (riscv_got_load_tls_gd (a0, sym)); 1390 insn = emit_call_insn (gen_call_value (result, func, const0_rtx, NULL)); 1391 RTL_CONST_CALL_P (insn) = 1; 1392 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0); 1393 insn = get_insns (); 1394 1395 end_sequence (); 1396 1397 return insn; 1398 } 1399 1400 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return 1401 its address. The return value will be both a valid address and a valid 1402 SET_SRC (either a REG or a LO_SUM). */ 1403 1404 static rtx 1405 riscv_legitimize_tls_address (rtx loc) 1406 { 1407 rtx dest, tp, tmp; 1408 enum tls_model model = SYMBOL_REF_TLS_MODEL (loc); 1409 1410 #if 0 1411 /* TLS copy relocs are now deprecated and should not be used. */ 1412 /* Since we support TLS copy relocs, non-PIC TLS accesses may all use LE. */ 1413 if (!flag_pic) 1414 model = TLS_MODEL_LOCAL_EXEC; 1415 #endif 1416 1417 switch (model) 1418 { 1419 case TLS_MODEL_LOCAL_DYNAMIC: 1420 /* Rely on section anchors for the optimization that LDM TLS 1421 provides. The anchor's address is loaded with GD TLS. */ 1422 case TLS_MODEL_GLOBAL_DYNAMIC: 1423 tmp = gen_rtx_REG (Pmode, GP_RETURN); 1424 dest = gen_reg_rtx (Pmode); 1425 emit_libcall_block (riscv_call_tls_get_addr (loc, tmp), dest, tmp, loc); 1426 break; 1427 1428 case TLS_MODEL_INITIAL_EXEC: 1429 /* la.tls.ie; tp-relative add */ 1430 tp = gen_rtx_REG (Pmode, THREAD_POINTER_REGNUM); 1431 tmp = gen_reg_rtx (Pmode); 1432 emit_insn (riscv_got_load_tls_ie (tmp, loc)); 1433 dest = gen_reg_rtx (Pmode); 1434 emit_insn (gen_add3_insn (dest, tmp, tp)); 1435 break; 1436 1437 case TLS_MODEL_LOCAL_EXEC: 1438 tmp = riscv_unspec_offset_high (NULL, loc, SYMBOL_TLS_LE); 1439 dest = gen_reg_rtx (Pmode); 1440 emit_insn (riscv_tls_add_tp_le (dest, tmp, loc)); 1441 dest = gen_rtx_LO_SUM (Pmode, dest, 1442 riscv_unspec_address (loc, SYMBOL_TLS_LE)); 1443 break; 1444 1445 default: 1446 gcc_unreachable (); 1447 } 1448 return dest; 1449 } 1450 1451 /* If X is not a valid address for mode MODE, force it into a register. */ 1453 1454 static rtx 1455 riscv_force_address (rtx x, machine_mode mode) 1456 { 1457 if (!riscv_legitimate_address_p (mode, x, false)) 1458 x = force_reg (Pmode, x); 1459 return x; 1460 } 1461 1462 /* Modify base + offset so that offset fits within a compressed load/store insn 1463 and the excess is added to base. */ 1464 1465 static rtx 1466 riscv_shorten_lw_offset (rtx base, HOST_WIDE_INT offset) 1467 { 1468 rtx addr, high; 1469 /* Leave OFFSET as an unsigned 5-bit offset scaled by 4 and put the excess 1470 into HIGH. */ 1471 high = GEN_INT (offset & ~CSW_MAX_OFFSET); 1472 offset &= CSW_MAX_OFFSET; 1473 if (!SMALL_OPERAND (INTVAL (high))) 1474 high = force_reg (Pmode, high); 1475 base = force_reg (Pmode, gen_rtx_PLUS (Pmode, high, base)); 1476 addr = plus_constant (Pmode, base, offset); 1477 return addr; 1478 } 1479 1480 /* This function is used to implement LEGITIMIZE_ADDRESS. If X can 1481 be legitimized in a way that the generic machinery might not expect, 1482 return a new address, otherwise return NULL. MODE is the mode of 1483 the memory being accessed. */ 1484 1485 static rtx 1486 riscv_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, 1487 machine_mode mode) 1488 { 1489 rtx addr; 1490 1491 if (riscv_tls_symbol_p (x)) 1492 return riscv_legitimize_tls_address (x); 1493 1494 /* See if the address can split into a high part and a LO_SUM. */ 1495 if (riscv_split_symbol (NULL, x, mode, &addr, FALSE)) 1496 return riscv_force_address (addr, mode); 1497 1498 /* Handle BASE + OFFSET. */ 1499 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)) 1500 && INTVAL (XEXP (x, 1)) != 0) 1501 { 1502 rtx base = XEXP (x, 0); 1503 HOST_WIDE_INT offset = INTVAL (XEXP (x, 1)); 1504 1505 if (!riscv_valid_base_register_p (base, mode, false)) 1506 base = copy_to_mode_reg (Pmode, base); 1507 if (optimize_function_for_size_p (cfun) 1508 && (strcmp (current_pass->name, "shorten_memrefs") == 0) 1509 && mode == SImode) 1510 /* Convert BASE + LARGE_OFFSET into NEW_BASE + SMALL_OFFSET to allow 1511 possible compressed load/store. */ 1512 addr = riscv_shorten_lw_offset (base, offset); 1513 else 1514 addr = riscv_add_offset (NULL, base, offset); 1515 return riscv_force_address (addr, mode); 1516 } 1517 1518 return x; 1519 } 1520 1521 /* Load VALUE into DEST. TEMP is as for riscv_force_temporary. ORIG_MODE 1522 is the original src mode before promotion. */ 1523 1524 void 1525 riscv_move_integer (rtx temp, rtx dest, HOST_WIDE_INT value, 1526 machine_mode orig_mode, bool in_splitter) 1527 { 1528 struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS]; 1529 machine_mode mode; 1530 int i, num_ops; 1531 rtx x; 1532 1533 /* We can't call gen_reg_rtx from a splitter, because this might realloc 1534 the regno_reg_rtx array, which would invalidate reg rtx pointers in the 1535 combine undo buffer. */ 1536 bool can_create_pseudo = can_create_pseudo_p () && ! in_splitter; 1537 1538 mode = GET_MODE (dest); 1539 /* We use the original mode for the riscv_build_integer call, because HImode 1540 values are given special treatment. */ 1541 num_ops = riscv_build_integer (codes, value, orig_mode); 1542 1543 if (can_create_pseudo && num_ops > 2 /* not a simple constant */ 1544 && num_ops >= riscv_split_integer_cost (value)) 1545 x = riscv_split_integer (value, mode); 1546 else 1547 { 1548 /* Apply each binary operation to X. */ 1549 x = GEN_INT (codes[0].value); 1550 1551 for (i = 1; i < num_ops; i++) 1552 { 1553 if (!can_create_pseudo) 1554 x = riscv_emit_set (temp, x); 1555 else 1556 x = force_reg (mode, x); 1557 1558 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value)); 1559 } 1560 } 1561 1562 riscv_emit_set (dest, x); 1563 } 1564 1565 /* Subroutine of riscv_legitimize_move. Move constant SRC into register 1566 DEST given that SRC satisfies immediate_operand but doesn't satisfy 1567 move_operand. */ 1568 1569 static void 1570 riscv_legitimize_const_move (machine_mode mode, rtx dest, rtx src) 1571 { 1572 rtx base, offset; 1573 1574 /* Split moves of big integers into smaller pieces. */ 1575 if (splittable_const_int_operand (src, mode)) 1576 { 1577 riscv_move_integer (dest, dest, INTVAL (src), mode, FALSE); 1578 return; 1579 } 1580 1581 /* Split moves of symbolic constants into high/low pairs. */ 1582 if (riscv_split_symbol (dest, src, MAX_MACHINE_MODE, &src, FALSE)) 1583 { 1584 riscv_emit_set (dest, src); 1585 return; 1586 } 1587 1588 /* Generate the appropriate access sequences for TLS symbols. */ 1589 if (riscv_tls_symbol_p (src)) 1590 { 1591 riscv_emit_move (dest, riscv_legitimize_tls_address (src)); 1592 return; 1593 } 1594 1595 /* If we have (const (plus symbol offset)), and that expression cannot 1596 be forced into memory, load the symbol first and add in the offset. Also 1597 prefer to do this even if the constant _can_ be forced into memory, as it 1598 usually produces better code. */ 1599 split_const (src, &base, &offset); 1600 if (offset != const0_rtx 1601 && (targetm.cannot_force_const_mem (mode, src) || can_create_pseudo_p ())) 1602 { 1603 base = riscv_force_temporary (dest, base, FALSE); 1604 riscv_emit_move (dest, riscv_add_offset (NULL, base, INTVAL (offset))); 1605 return; 1606 } 1607 1608 src = force_const_mem (mode, src); 1609 1610 /* When using explicit relocs, constant pool references are sometimes 1611 not legitimate addresses. */ 1612 riscv_split_symbol (dest, XEXP (src, 0), mode, &XEXP (src, 0), FALSE); 1613 riscv_emit_move (dest, src); 1614 } 1615 1616 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent 1617 sequence that is valid. */ 1618 1619 bool 1620 riscv_legitimize_move (machine_mode mode, rtx dest, rtx src) 1621 { 1622 /* Expand 1623 (set (reg:QI target) (mem:QI (address))) 1624 to 1625 (set (reg:DI temp) (zero_extend:DI (mem:QI (address)))) 1626 (set (reg:QI target) (subreg:QI (reg:DI temp) 0)) 1627 with auto-sign/zero extend. */ 1628 if (GET_MODE_CLASS (mode) == MODE_INT 1629 && GET_MODE_SIZE (mode) < UNITS_PER_WORD 1630 && can_create_pseudo_p () 1631 && MEM_P (src)) 1632 { 1633 rtx temp_reg; 1634 int zero_extend_p; 1635 1636 temp_reg = gen_reg_rtx (word_mode); 1637 zero_extend_p = (LOAD_EXTEND_OP (mode) == ZERO_EXTEND); 1638 emit_insn (gen_extend_insn (temp_reg, src, word_mode, mode, 1639 zero_extend_p)); 1640 riscv_emit_move (dest, gen_lowpart (mode, temp_reg)); 1641 return true; 1642 } 1643 1644 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode)) 1645 { 1646 rtx reg; 1647 1648 if (GET_CODE (src) == CONST_INT) 1649 { 1650 /* Apply the equivalent of PROMOTE_MODE here for constants to 1651 improve cse. */ 1652 machine_mode promoted_mode = mode; 1653 if (GET_MODE_CLASS (mode) == MODE_INT 1654 && GET_MODE_SIZE (mode) < UNITS_PER_WORD) 1655 promoted_mode = word_mode; 1656 1657 if (splittable_const_int_operand (src, mode)) 1658 { 1659 reg = gen_reg_rtx (promoted_mode); 1660 riscv_move_integer (reg, reg, INTVAL (src), mode, FALSE); 1661 } 1662 else 1663 reg = force_reg (promoted_mode, src); 1664 1665 if (promoted_mode != mode) 1666 reg = gen_lowpart (mode, reg); 1667 } 1668 else 1669 reg = force_reg (mode, src); 1670 riscv_emit_move (dest, reg); 1671 return true; 1672 } 1673 1674 /* We need to deal with constants that would be legitimate 1675 immediate_operands but aren't legitimate move_operands. */ 1676 if (CONSTANT_P (src) && !move_operand (src, mode)) 1677 { 1678 riscv_legitimize_const_move (mode, dest, src); 1679 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src)); 1680 return true; 1681 } 1682 1683 /* RISC-V GCC may generate non-legitimate address due to we provide some 1684 pattern for optimize access PIC local symbol and it's make GCC generate 1685 unrecognizable instruction during optmizing. */ 1686 1687 if (MEM_P (dest) && !riscv_legitimate_address_p (mode, XEXP (dest, 0), 1688 reload_completed)) 1689 { 1690 XEXP (dest, 0) = riscv_force_address (XEXP (dest, 0), mode); 1691 } 1692 1693 if (MEM_P (src) && !riscv_legitimate_address_p (mode, XEXP (src, 0), 1694 reload_completed)) 1695 { 1696 XEXP (src, 0) = riscv_force_address (XEXP (src, 0), mode); 1697 } 1698 1699 return false; 1700 } 1701 1702 /* Return true if there is an instruction that implements CODE and accepts 1703 X as an immediate operand. */ 1704 1705 static int 1706 riscv_immediate_operand_p (int code, HOST_WIDE_INT x) 1707 { 1708 switch (code) 1709 { 1710 case ASHIFT: 1711 case ASHIFTRT: 1712 case LSHIFTRT: 1713 /* All shift counts are truncated to a valid constant. */ 1714 return true; 1715 1716 case AND: 1717 case IOR: 1718 case XOR: 1719 case PLUS: 1720 case LT: 1721 case LTU: 1722 /* These instructions take 12-bit signed immediates. */ 1723 return SMALL_OPERAND (x); 1724 1725 case LE: 1726 /* We add 1 to the immediate and use SLT. */ 1727 return SMALL_OPERAND (x + 1); 1728 1729 case LEU: 1730 /* Likewise SLTU, but reject the always-true case. */ 1731 return SMALL_OPERAND (x + 1) && x + 1 != 0; 1732 1733 case GE: 1734 case GEU: 1735 /* We can emulate an immediate of 1 by using GT/GTU against x0. */ 1736 return x == 1; 1737 1738 default: 1739 /* By default assume that x0 can be used for 0. */ 1740 return x == 0; 1741 } 1742 } 1743 1744 /* Return the cost of binary operation X, given that the instruction 1745 sequence for a word-sized or smaller operation takes SIGNLE_INSNS 1746 instructions and that the sequence of a double-word operation takes 1747 DOUBLE_INSNS instructions. */ 1748 1749 static int 1750 riscv_binary_cost (rtx x, int single_insns, int double_insns) 1751 { 1752 if (GET_MODE_SIZE (GET_MODE (x)) == UNITS_PER_WORD * 2) 1753 return COSTS_N_INSNS (double_insns); 1754 return COSTS_N_INSNS (single_insns); 1755 } 1756 1757 /* Return the cost of sign- or zero-extending OP. */ 1758 1759 static int 1760 riscv_extend_cost (rtx op, bool unsigned_p) 1761 { 1762 if (MEM_P (op)) 1763 return 0; 1764 1765 if (unsigned_p && GET_MODE (op) == QImode) 1766 /* We can use ANDI. */ 1767 return COSTS_N_INSNS (1); 1768 1769 /* ZBA provide zext.w. */ 1770 if (TARGET_ZBA && TARGET_64BIT && unsigned_p && GET_MODE (op) == SImode) 1771 return COSTS_N_INSNS (1); 1772 1773 /* ZBB provide zext.h, sext.b and sext.h. */ 1774 if (TARGET_ZBB) 1775 { 1776 if (!unsigned_p && GET_MODE (op) == QImode) 1777 return COSTS_N_INSNS (1); 1778 1779 if (GET_MODE (op) == HImode) 1780 return COSTS_N_INSNS (1); 1781 } 1782 1783 if (!unsigned_p && GET_MODE (op) == SImode) 1784 /* We can use SEXT.W. */ 1785 return COSTS_N_INSNS (1); 1786 1787 /* We need to use a shift left and a shift right. */ 1788 return COSTS_N_INSNS (2); 1789 } 1790 1791 /* Implement TARGET_RTX_COSTS. */ 1792 1793 #define SINGLE_SHIFT_COST 1 1794 1795 static bool 1796 riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UNUSED, 1797 int *total, bool speed) 1798 { 1799 bool float_mode_p = FLOAT_MODE_P (mode); 1800 int cost; 1801 1802 switch (GET_CODE (x)) 1803 { 1804 case CONST_INT: 1805 if (riscv_immediate_operand_p (outer_code, INTVAL (x))) 1806 { 1807 *total = 0; 1808 return true; 1809 } 1810 /* Fall through. */ 1811 1812 case SYMBOL_REF: 1813 case LABEL_REF: 1814 case CONST_DOUBLE: 1815 case CONST: 1816 if ((cost = riscv_const_insns (x)) > 0) 1817 { 1818 /* If the constant is likely to be stored in a GPR, SETs of 1819 single-insn constants are as cheap as register sets; we 1820 never want to CSE them. */ 1821 if (cost == 1 && outer_code == SET) 1822 *total = 0; 1823 /* When we load a constant more than once, it usually is better 1824 to duplicate the last operation in the sequence than to CSE 1825 the constant itself. */ 1826 else if (outer_code == SET || GET_MODE (x) == VOIDmode) 1827 *total = COSTS_N_INSNS (1); 1828 } 1829 else /* The instruction will be fetched from the constant pool. */ 1830 *total = COSTS_N_INSNS (riscv_symbol_insns (SYMBOL_ABSOLUTE)); 1831 return true; 1832 1833 case MEM: 1834 /* If the address is legitimate, return the number of 1835 instructions it needs. */ 1836 if ((cost = riscv_address_insns (XEXP (x, 0), mode, true)) > 0) 1837 { 1838 /* When optimizing for size, make uncompressible 32-bit addresses 1839 more expensive so that compressible 32-bit addresses are 1840 preferred. */ 1841 if (TARGET_RVC && !speed && riscv_mshorten_memrefs && mode == SImode 1842 && !riscv_compressed_lw_address_p (XEXP (x, 0))) 1843 cost++; 1844 1845 *total = COSTS_N_INSNS (cost + tune_param->memory_cost); 1846 return true; 1847 } 1848 /* Otherwise use the default handling. */ 1849 return false; 1850 1851 case NOT: 1852 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 2 : 1); 1853 return false; 1854 1855 case AND: 1856 /* slli.uw pattern for zba. */ 1857 if (TARGET_ZBA && TARGET_64BIT && mode == DImode 1858 && GET_CODE (XEXP (x, 0)) == ASHIFT) 1859 { 1860 rtx and_rhs = XEXP (x, 1); 1861 rtx ashift_lhs = XEXP (XEXP (x, 0), 0); 1862 rtx ashift_rhs = XEXP (XEXP (x, 0), 1); 1863 if (REG_P (ashift_lhs) 1864 && CONST_INT_P (ashift_rhs) 1865 && CONST_INT_P (and_rhs) 1866 && ((INTVAL (and_rhs) >> INTVAL (ashift_rhs)) == 0xffffffff)) 1867 *total = COSTS_N_INSNS (1); 1868 return true; 1869 } 1870 /* bclri pattern for zbs. */ 1871 if (TARGET_ZBS 1872 && not_single_bit_mask_operand (XEXP (x, 1), VOIDmode)) 1873 { 1874 *total = COSTS_N_INSNS (1); 1875 return true; 1876 } 1877 /* bclr pattern for zbs. */ 1878 if (TARGET_ZBS 1879 && REG_P (XEXP (x, 1)) 1880 && GET_CODE (XEXP (x, 0)) == ROTATE 1881 && CONST_INT_P (XEXP ((XEXP (x, 0)), 0)) 1882 && INTVAL (XEXP ((XEXP (x, 0)), 0)) == -2) 1883 { 1884 *total = COSTS_N_INSNS (1); 1885 return true; 1886 } 1887 1888 gcc_fallthrough (); 1889 case IOR: 1890 case XOR: 1891 /* orn, andn and xorn pattern for zbb. */ 1892 if (TARGET_ZBB 1893 && GET_CODE (XEXP (x, 0)) == NOT) 1894 { 1895 *total = riscv_binary_cost (x, 1, 2); 1896 return true; 1897 } 1898 1899 /* bset[i] and binv[i] pattern for zbs. */ 1900 if ((GET_CODE (x) == IOR || GET_CODE (x) == XOR) 1901 && TARGET_ZBS 1902 && ((GET_CODE (XEXP (x, 0)) == ASHIFT 1903 && CONST_INT_P (XEXP (XEXP (x, 0), 0))) 1904 || single_bit_mask_operand (XEXP (x, 1), VOIDmode))) 1905 { 1906 *total = COSTS_N_INSNS (1); 1907 return true; 1908 } 1909 1910 /* Double-word operations use two single-word operations. */ 1911 *total = riscv_binary_cost (x, 1, 2); 1912 return false; 1913 1914 case ZERO_EXTRACT: 1915 /* This is an SImode shift. */ 1916 if (outer_code == SET 1917 && CONST_INT_P (XEXP (x, 1)) 1918 && CONST_INT_P (XEXP (x, 2)) 1919 && (INTVAL (XEXP (x, 2)) > 0) 1920 && (INTVAL (XEXP (x, 1)) + INTVAL (XEXP (x, 2)) == 32)) 1921 { 1922 *total = COSTS_N_INSNS (SINGLE_SHIFT_COST); 1923 return true; 1924 } 1925 /* bext pattern for zbs. */ 1926 if (TARGET_ZBS && outer_code == SET 1927 && GET_CODE (XEXP (x, 1)) == CONST_INT 1928 && INTVAL (XEXP (x, 1)) == 1) 1929 { 1930 *total = COSTS_N_INSNS (SINGLE_SHIFT_COST); 1931 return true; 1932 } 1933 return false; 1934 1935 case ASHIFT: 1936 /* bset pattern for zbs. */ 1937 if (TARGET_ZBS 1938 && CONST_INT_P (XEXP (x, 0)) 1939 && INTVAL (XEXP (x, 0)) == 1) 1940 { 1941 *total = COSTS_N_INSNS (1); 1942 return true; 1943 } 1944 gcc_fallthrough (); 1945 case ASHIFTRT: 1946 case LSHIFTRT: 1947 *total = riscv_binary_cost (x, SINGLE_SHIFT_COST, 1948 CONSTANT_P (XEXP (x, 1)) ? 4 : 9); 1949 return false; 1950 1951 case ABS: 1952 *total = COSTS_N_INSNS (float_mode_p ? 1 : 3); 1953 return false; 1954 1955 case LO_SUM: 1956 *total = set_src_cost (XEXP (x, 0), mode, speed); 1957 return true; 1958 1959 case LT: 1960 /* This is an SImode shift. */ 1961 if (outer_code == SET && GET_MODE (x) == DImode 1962 && GET_MODE (XEXP (x, 0)) == SImode) 1963 { 1964 *total = COSTS_N_INSNS (SINGLE_SHIFT_COST); 1965 return true; 1966 } 1967 /* Fall through. */ 1968 case LTU: 1969 case LE: 1970 case LEU: 1971 case GT: 1972 case GTU: 1973 case GE: 1974 case GEU: 1975 case EQ: 1976 case NE: 1977 /* Branch comparisons have VOIDmode, so use the first operand's 1978 mode instead. */ 1979 mode = GET_MODE (XEXP (x, 0)); 1980 if (float_mode_p) 1981 *total = tune_param->fp_add[mode == DFmode]; 1982 else 1983 *total = riscv_binary_cost (x, 1, 3); 1984 return false; 1985 1986 case UNORDERED: 1987 case ORDERED: 1988 /* (FEQ(A, A) & FEQ(B, B)) compared against 0. */ 1989 mode = GET_MODE (XEXP (x, 0)); 1990 *total = tune_param->fp_add[mode == DFmode] + COSTS_N_INSNS (2); 1991 return false; 1992 1993 case UNEQ: 1994 /* (FEQ(A, A) & FEQ(B, B)) compared against FEQ(A, B). */ 1995 mode = GET_MODE (XEXP (x, 0)); 1996 *total = tune_param->fp_add[mode == DFmode] + COSTS_N_INSNS (3); 1997 return false; 1998 1999 case LTGT: 2000 /* (FLT(A, A) || FGT(B, B)). */ 2001 mode = GET_MODE (XEXP (x, 0)); 2002 *total = tune_param->fp_add[mode == DFmode] + COSTS_N_INSNS (2); 2003 return false; 2004 2005 case UNGE: 2006 case UNGT: 2007 case UNLE: 2008 case UNLT: 2009 /* FLT or FLE, but guarded by an FFLAGS read and write. */ 2010 mode = GET_MODE (XEXP (x, 0)); 2011 *total = tune_param->fp_add[mode == DFmode] + COSTS_N_INSNS (4); 2012 return false; 2013 2014 case MINUS: 2015 case PLUS: 2016 /* add.uw pattern for zba. */ 2017 if (TARGET_ZBA 2018 && (TARGET_64BIT && (mode == DImode)) 2019 && GET_CODE (XEXP (x, 0)) == ZERO_EXTEND 2020 && REG_P (XEXP (XEXP (x, 0), 0)) 2021 && GET_MODE (XEXP (XEXP (x, 0), 0)) == SImode) 2022 { 2023 *total = COSTS_N_INSNS (1); 2024 return true; 2025 } 2026 /* shNadd pattern for zba. */ 2027 if (TARGET_ZBA 2028 && ((!TARGET_64BIT && (mode == SImode)) || 2029 (TARGET_64BIT && (mode == DImode))) 2030 && (GET_CODE (XEXP (x, 0)) == ASHIFT) 2031 && REG_P (XEXP (XEXP (x, 0), 0)) 2032 && CONST_INT_P (XEXP (XEXP (x, 0), 1)) 2033 && IN_RANGE (INTVAL (XEXP (XEXP (x, 0), 1)), 1, 3)) 2034 { 2035 *total = COSTS_N_INSNS (1); 2036 return true; 2037 } 2038 /* shNadd.uw pattern for zba. 2039 [(set (match_operand:DI 0 "register_operand" "=r") 2040 (plus:DI 2041 (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r") 2042 (match_operand:QI 2 "immediate_operand" "I")) 2043 (match_operand 3 "immediate_operand" "")) 2044 (match_operand:DI 4 "register_operand" "r")))] 2045 "TARGET_64BIT && TARGET_ZBA 2046 && (INTVAL (operands[2]) >= 1) && (INTVAL (operands[2]) <= 3) 2047 && (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff" 2048 */ 2049 if (TARGET_ZBA 2050 && (TARGET_64BIT && (mode == DImode)) 2051 && (GET_CODE (XEXP (x, 0)) == AND) 2052 && (REG_P (XEXP (x, 1)))) 2053 { 2054 do { 2055 rtx and_lhs = XEXP (XEXP (x, 0), 0); 2056 rtx and_rhs = XEXP (XEXP (x, 0), 1); 2057 if (GET_CODE (and_lhs) != ASHIFT) 2058 break; 2059 if (!CONST_INT_P (and_rhs)) 2060 break; 2061 2062 rtx ashift_rhs = XEXP (and_lhs, 1); 2063 2064 if (!CONST_INT_P (ashift_rhs) 2065 || !IN_RANGE (INTVAL (ashift_rhs), 1, 3)) 2066 break; 2067 2068 if (CONST_INT_P (and_rhs) 2069 && ((INTVAL (and_rhs) >> INTVAL (ashift_rhs)) == 0xffffffff)) 2070 { 2071 *total = COSTS_N_INSNS (1); 2072 return true; 2073 } 2074 } while (false); 2075 } 2076 2077 if (float_mode_p) 2078 *total = tune_param->fp_add[mode == DFmode]; 2079 else 2080 *total = riscv_binary_cost (x, 1, 4); 2081 return false; 2082 2083 case NEG: 2084 { 2085 rtx op = XEXP (x, 0); 2086 if (GET_CODE (op) == FMA && !HONOR_SIGNED_ZEROS (mode)) 2087 { 2088 *total = (tune_param->fp_mul[mode == DFmode] 2089 + set_src_cost (XEXP (op, 0), mode, speed) 2090 + set_src_cost (XEXP (op, 1), mode, speed) 2091 + set_src_cost (XEXP (op, 2), mode, speed)); 2092 return true; 2093 } 2094 } 2095 2096 if (float_mode_p) 2097 *total = tune_param->fp_add[mode == DFmode]; 2098 else 2099 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 4 : 1); 2100 return false; 2101 2102 case MULT: 2103 if (float_mode_p) 2104 *total = tune_param->fp_mul[mode == DFmode]; 2105 else if (!TARGET_MUL) 2106 /* Estimate the cost of a library call. */ 2107 *total = COSTS_N_INSNS (speed ? 32 : 6); 2108 else if (GET_MODE_SIZE (mode) > UNITS_PER_WORD) 2109 *total = 3 * tune_param->int_mul[0] + COSTS_N_INSNS (2); 2110 else if (!speed) 2111 *total = COSTS_N_INSNS (1); 2112 else 2113 *total = tune_param->int_mul[mode == DImode]; 2114 return false; 2115 2116 case DIV: 2117 case SQRT: 2118 case MOD: 2119 if (float_mode_p) 2120 { 2121 *total = tune_param->fp_div[mode == DFmode]; 2122 return false; 2123 } 2124 /* Fall through. */ 2125 2126 case UDIV: 2127 case UMOD: 2128 if (!TARGET_DIV) 2129 /* Estimate the cost of a library call. */ 2130 *total = COSTS_N_INSNS (speed ? 32 : 6); 2131 else if (speed) 2132 *total = tune_param->int_div[mode == DImode]; 2133 else 2134 *total = COSTS_N_INSNS (1); 2135 return false; 2136 2137 case ZERO_EXTEND: 2138 /* This is an SImode shift. */ 2139 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT) 2140 { 2141 *total = COSTS_N_INSNS (SINGLE_SHIFT_COST); 2142 return true; 2143 } 2144 /* Fall through. */ 2145 case SIGN_EXTEND: 2146 *total = riscv_extend_cost (XEXP (x, 0), GET_CODE (x) == ZERO_EXTEND); 2147 return false; 2148 2149 case FLOAT: 2150 case UNSIGNED_FLOAT: 2151 case FIX: 2152 case FLOAT_EXTEND: 2153 case FLOAT_TRUNCATE: 2154 *total = tune_param->fp_add[mode == DFmode]; 2155 return false; 2156 2157 case FMA: 2158 *total = (tune_param->fp_mul[mode == DFmode] 2159 + set_src_cost (XEXP (x, 0), mode, speed) 2160 + set_src_cost (XEXP (x, 1), mode, speed) 2161 + set_src_cost (XEXP (x, 2), mode, speed)); 2162 return true; 2163 2164 case UNSPEC: 2165 if (XINT (x, 1) == UNSPEC_AUIPC) 2166 { 2167 /* Make AUIPC cheap to avoid spilling its result to the stack. */ 2168 *total = 1; 2169 return true; 2170 } 2171 return false; 2172 2173 default: 2174 return false; 2175 } 2176 } 2177 2178 /* Implement TARGET_ADDRESS_COST. */ 2179 2180 static int 2181 riscv_address_cost (rtx addr, machine_mode mode, 2182 addr_space_t as ATTRIBUTE_UNUSED, 2183 bool speed ATTRIBUTE_UNUSED) 2184 { 2185 /* When optimizing for size, make uncompressible 32-bit addresses more 2186 * expensive so that compressible 32-bit addresses are preferred. */ 2187 if (TARGET_RVC && !speed && riscv_mshorten_memrefs && mode == SImode 2188 && !riscv_compressed_lw_address_p (addr)) 2189 return riscv_address_insns (addr, mode, false) + 1; 2190 return riscv_address_insns (addr, mode, false); 2191 } 2192 2193 /* Return one word of double-word value OP. HIGH_P is true to select the 2194 high part or false to select the low part. */ 2195 2196 rtx 2197 riscv_subword (rtx op, bool high_p) 2198 { 2199 unsigned int byte = (high_p != BYTES_BIG_ENDIAN) ? UNITS_PER_WORD : 0; 2200 machine_mode mode = GET_MODE (op); 2201 2202 if (mode == VOIDmode) 2203 mode = TARGET_64BIT ? TImode : DImode; 2204 2205 if (MEM_P (op)) 2206 return adjust_address (op, word_mode, byte); 2207 2208 if (REG_P (op)) 2209 gcc_assert (!FP_REG_RTX_P (op)); 2210 2211 return simplify_gen_subreg (word_mode, op, mode, byte); 2212 } 2213 2214 /* Return true if a 64-bit move from SRC to DEST should be split into two. */ 2215 2216 bool 2217 riscv_split_64bit_move_p (rtx dest, rtx src) 2218 { 2219 if (TARGET_64BIT) 2220 return false; 2221 2222 /* Allow FPR <-> FPR and FPR <-> MEM moves, and permit the special case 2223 of zeroing an FPR with FCVT.D.W. */ 2224 if (TARGET_DOUBLE_FLOAT 2225 && ((FP_REG_RTX_P (src) && FP_REG_RTX_P (dest)) 2226 || (FP_REG_RTX_P (dest) && MEM_P (src)) 2227 || (FP_REG_RTX_P (src) && MEM_P (dest)) 2228 || (FP_REG_RTX_P (dest) && src == CONST0_RTX (GET_MODE (src))))) 2229 return false; 2230 2231 return true; 2232 } 2233 2234 /* Split a doubleword move from SRC to DEST. On 32-bit targets, 2235 this function handles 64-bit moves for which riscv_split_64bit_move_p 2236 holds. For 64-bit targets, this function handles 128-bit moves. */ 2237 2238 void 2239 riscv_split_doubleword_move (rtx dest, rtx src) 2240 { 2241 rtx low_dest; 2242 2243 /* The operation can be split into two normal moves. Decide in 2244 which order to do them. */ 2245 low_dest = riscv_subword (dest, false); 2246 if (REG_P (low_dest) && reg_overlap_mentioned_p (low_dest, src)) 2247 { 2248 riscv_emit_move (riscv_subword (dest, true), riscv_subword (src, true)); 2249 riscv_emit_move (low_dest, riscv_subword (src, false)); 2250 } 2251 else 2252 { 2253 riscv_emit_move (low_dest, riscv_subword (src, false)); 2254 riscv_emit_move (riscv_subword (dest, true), riscv_subword (src, true)); 2255 } 2256 } 2257 2258 /* Return the appropriate instructions to move SRC into DEST. Assume 2260 that SRC is operand 1 and DEST is operand 0. */ 2261 2262 const char * 2263 riscv_output_move (rtx dest, rtx src) 2264 { 2265 enum rtx_code dest_code, src_code; 2266 machine_mode mode; 2267 bool dbl_p; 2268 2269 dest_code = GET_CODE (dest); 2270 src_code = GET_CODE (src); 2271 mode = GET_MODE (dest); 2272 dbl_p = (GET_MODE_SIZE (mode) == 8); 2273 2274 if (dbl_p && riscv_split_64bit_move_p (dest, src)) 2275 return "#"; 2276 2277 if (dest_code == REG && GP_REG_P (REGNO (dest))) 2278 { 2279 if (src_code == REG && FP_REG_P (REGNO (src))) 2280 return dbl_p ? "fmv.x.d\t%0,%1" : "fmv.x.w\t%0,%1"; 2281 2282 if (src_code == MEM) 2283 switch (GET_MODE_SIZE (mode)) 2284 { 2285 case 1: return "lbu\t%0,%1"; 2286 case 2: return "lhu\t%0,%1"; 2287 case 4: return "lw\t%0,%1"; 2288 case 8: return "ld\t%0,%1"; 2289 } 2290 2291 if (src_code == CONST_INT) 2292 { 2293 if (SMALL_OPERAND (INTVAL (src)) || LUI_OPERAND (INTVAL (src))) 2294 return "li\t%0,%1"; 2295 2296 if (TARGET_ZBS 2297 && SINGLE_BIT_MASK_OPERAND (INTVAL (src))) 2298 return "bseti\t%0,zero,%S1"; 2299 2300 /* Should never reach here. */ 2301 abort (); 2302 } 2303 2304 if (src_code == HIGH) 2305 return "lui\t%0,%h1"; 2306 2307 if (symbolic_operand (src, VOIDmode)) 2308 switch (riscv_classify_symbolic_expression (src)) 2309 { 2310 case SYMBOL_GOT_DISP: return "la\t%0,%1"; 2311 case SYMBOL_ABSOLUTE: return "lla\t%0,%1"; 2312 case SYMBOL_PCREL: return "lla\t%0,%1"; 2313 default: gcc_unreachable (); 2314 } 2315 } 2316 if ((src_code == REG && GP_REG_P (REGNO (src))) 2317 || (src == CONST0_RTX (mode))) 2318 { 2319 if (dest_code == REG) 2320 { 2321 if (GP_REG_P (REGNO (dest))) 2322 return "mv\t%0,%z1"; 2323 2324 if (FP_REG_P (REGNO (dest))) 2325 { 2326 if (!dbl_p) 2327 return "fmv.w.x\t%0,%z1"; 2328 if (TARGET_64BIT) 2329 return "fmv.d.x\t%0,%z1"; 2330 /* in RV32, we can emulate fmv.d.x %0, x0 using fcvt.d.w */ 2331 gcc_assert (src == CONST0_RTX (mode)); 2332 return "fcvt.d.w\t%0,x0"; 2333 } 2334 } 2335 if (dest_code == MEM) 2336 switch (GET_MODE_SIZE (mode)) 2337 { 2338 case 1: return "sb\t%z1,%0"; 2339 case 2: return "sh\t%z1,%0"; 2340 case 4: return "sw\t%z1,%0"; 2341 case 8: return "sd\t%z1,%0"; 2342 } 2343 } 2344 if (src_code == REG && FP_REG_P (REGNO (src))) 2345 { 2346 if (dest_code == REG && FP_REG_P (REGNO (dest))) 2347 return dbl_p ? "fmv.d\t%0,%1" : "fmv.s\t%0,%1"; 2348 2349 if (dest_code == MEM) 2350 return dbl_p ? "fsd\t%1,%0" : "fsw\t%1,%0"; 2351 } 2352 if (dest_code == REG && FP_REG_P (REGNO (dest))) 2353 { 2354 if (src_code == MEM) 2355 return dbl_p ? "fld\t%0,%1" : "flw\t%0,%1"; 2356 } 2357 gcc_unreachable (); 2358 } 2359 2360 const char * 2361 riscv_output_return () 2362 { 2363 if (cfun->machine->naked_p) 2364 return ""; 2365 2366 return "ret"; 2367 } 2368 2369 2370 /* Return true if CMP1 is a suitable second operand for integer ordering 2372 test CODE. See also the *sCC patterns in riscv.md. */ 2373 2374 static bool 2375 riscv_int_order_operand_ok_p (enum rtx_code code, rtx cmp1) 2376 { 2377 switch (code) 2378 { 2379 case GT: 2380 case GTU: 2381 return reg_or_0_operand (cmp1, VOIDmode); 2382 2383 case GE: 2384 case GEU: 2385 return cmp1 == const1_rtx; 2386 2387 case LT: 2388 case LTU: 2389 return arith_operand (cmp1, VOIDmode); 2390 2391 case LE: 2392 return sle_operand (cmp1, VOIDmode); 2393 2394 case LEU: 2395 return sleu_operand (cmp1, VOIDmode); 2396 2397 default: 2398 gcc_unreachable (); 2399 } 2400 } 2401 2402 /* Return true if *CMP1 (of mode MODE) is a valid second operand for 2403 integer ordering test *CODE, or if an equivalent combination can 2404 be formed by adjusting *CODE and *CMP1. When returning true, update 2405 *CODE and *CMP1 with the chosen code and operand, otherwise leave 2406 them alone. */ 2407 2408 static bool 2409 riscv_canonicalize_int_order_test (enum rtx_code *code, rtx *cmp1, 2410 machine_mode mode) 2411 { 2412 HOST_WIDE_INT plus_one; 2413 2414 if (riscv_int_order_operand_ok_p (*code, *cmp1)) 2415 return true; 2416 2417 if (CONST_INT_P (*cmp1)) 2418 switch (*code) 2419 { 2420 case LE: 2421 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode); 2422 if (INTVAL (*cmp1) < plus_one) 2423 { 2424 *code = LT; 2425 *cmp1 = force_reg (mode, GEN_INT (plus_one)); 2426 return true; 2427 } 2428 break; 2429 2430 case LEU: 2431 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode); 2432 if (plus_one != 0) 2433 { 2434 *code = LTU; 2435 *cmp1 = force_reg (mode, GEN_INT (plus_one)); 2436 return true; 2437 } 2438 break; 2439 2440 default: 2441 break; 2442 } 2443 return false; 2444 } 2445 2446 /* Compare CMP0 and CMP1 using ordering test CODE and store the result 2447 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR 2448 is nonnull, it's OK to set TARGET to the inverse of the result and 2449 flip *INVERT_PTR instead. */ 2450 2451 static void 2452 riscv_emit_int_order_test (enum rtx_code code, bool *invert_ptr, 2453 rtx target, rtx cmp0, rtx cmp1) 2454 { 2455 machine_mode mode; 2456 2457 /* First see if there is a RISCV instruction that can do this operation. 2458 If not, try doing the same for the inverse operation. If that also 2459 fails, force CMP1 into a register and try again. */ 2460 mode = GET_MODE (cmp0); 2461 if (riscv_canonicalize_int_order_test (&code, &cmp1, mode)) 2462 riscv_emit_binary (code, target, cmp0, cmp1); 2463 else 2464 { 2465 enum rtx_code inv_code = reverse_condition (code); 2466 if (!riscv_canonicalize_int_order_test (&inv_code, &cmp1, mode)) 2467 { 2468 cmp1 = force_reg (mode, cmp1); 2469 riscv_emit_int_order_test (code, invert_ptr, target, cmp0, cmp1); 2470 } 2471 else if (invert_ptr == 0) 2472 { 2473 rtx inv_target = riscv_force_binary (GET_MODE (target), 2474 inv_code, cmp0, cmp1); 2475 riscv_emit_binary (XOR, target, inv_target, const1_rtx); 2476 } 2477 else 2478 { 2479 *invert_ptr = !*invert_ptr; 2480 riscv_emit_binary (inv_code, target, cmp0, cmp1); 2481 } 2482 } 2483 } 2484 2485 /* Return a register that is zero iff CMP0 and CMP1 are equal. 2486 The register will have the same mode as CMP0. */ 2487 2488 static rtx 2489 riscv_zero_if_equal (rtx cmp0, rtx cmp1) 2490 { 2491 if (cmp1 == const0_rtx) 2492 return cmp0; 2493 2494 return expand_binop (GET_MODE (cmp0), sub_optab, 2495 cmp0, cmp1, 0, 0, OPTAB_DIRECT); 2496 } 2497 2498 /* Sign- or zero-extend OP0 and OP1 for integer comparisons. */ 2499 2500 static void 2501 riscv_extend_comparands (rtx_code code, rtx *op0, rtx *op1) 2502 { 2503 /* Comparisons consider all XLEN bits, so extend sub-XLEN values. */ 2504 if (GET_MODE_SIZE (word_mode) > GET_MODE_SIZE (GET_MODE (*op0))) 2505 { 2506 /* It is more profitable to zero-extend QImode values. But not if the 2507 first operand has already been sign-extended, and the second one is 2508 is a constant or has already been sign-extended also. */ 2509 if (unsigned_condition (code) == code 2510 && (GET_MODE (*op0) == QImode 2511 && ! (GET_CODE (*op0) == SUBREG 2512 && SUBREG_PROMOTED_VAR_P (*op0) 2513 && SUBREG_PROMOTED_SIGNED_P (*op0) 2514 && (CONST_INT_P (*op1) 2515 || (GET_CODE (*op1) == SUBREG 2516 && SUBREG_PROMOTED_VAR_P (*op1) 2517 && SUBREG_PROMOTED_SIGNED_P (*op1)))))) 2518 { 2519 *op0 = gen_rtx_ZERO_EXTEND (word_mode, *op0); 2520 if (CONST_INT_P (*op1)) 2521 *op1 = GEN_INT ((uint8_t) INTVAL (*op1)); 2522 else 2523 *op1 = gen_rtx_ZERO_EXTEND (word_mode, *op1); 2524 } 2525 else 2526 { 2527 *op0 = gen_rtx_SIGN_EXTEND (word_mode, *op0); 2528 if (*op1 != const0_rtx) 2529 *op1 = gen_rtx_SIGN_EXTEND (word_mode, *op1); 2530 } 2531 } 2532 } 2533 2534 /* Convert a comparison into something that can be used in a branch. On 2535 entry, *OP0 and *OP1 are the values being compared and *CODE is the code 2536 used to compare them. Update them to describe the final comparison. */ 2537 2538 static void 2539 riscv_emit_int_compare (enum rtx_code *code, rtx *op0, rtx *op1) 2540 { 2541 if (splittable_const_int_operand (*op1, VOIDmode)) 2542 { 2543 HOST_WIDE_INT rhs = INTVAL (*op1); 2544 2545 if (*code == EQ || *code == NE) 2546 { 2547 /* Convert e.g. OP0 == 2048 into OP0 - 2048 == 0. */ 2548 if (SMALL_OPERAND (-rhs)) 2549 { 2550 *op0 = riscv_force_binary (GET_MODE (*op0), PLUS, *op0, 2551 GEN_INT (-rhs)); 2552 *op1 = const0_rtx; 2553 } 2554 } 2555 else 2556 { 2557 static const enum rtx_code mag_comparisons[][2] = { 2558 {LEU, LTU}, {GTU, GEU}, {LE, LT}, {GT, GE} 2559 }; 2560 2561 /* Convert e.g. (OP0 <= 0xFFF) into (OP0 < 0x1000). */ 2562 for (size_t i = 0; i < ARRAY_SIZE (mag_comparisons); i++) 2563 { 2564 HOST_WIDE_INT new_rhs; 2565 bool increment = *code == mag_comparisons[i][0]; 2566 bool decrement = *code == mag_comparisons[i][1]; 2567 if (!increment && !decrement) 2568 continue; 2569 2570 new_rhs = rhs + (increment ? 1 : -1); 2571 if (riscv_integer_cost (new_rhs) < riscv_integer_cost (rhs) 2572 && (rhs < 0) == (new_rhs < 0)) 2573 { 2574 *op1 = GEN_INT (new_rhs); 2575 *code = mag_comparisons[i][increment]; 2576 } 2577 break; 2578 } 2579 } 2580 } 2581 2582 riscv_extend_comparands (*code, op0, op1); 2583 2584 *op0 = force_reg (word_mode, *op0); 2585 if (*op1 != const0_rtx) 2586 *op1 = force_reg (word_mode, *op1); 2587 } 2588 2589 /* Like riscv_emit_int_compare, but for floating-point comparisons. */ 2590 2591 static void 2592 riscv_emit_float_compare (enum rtx_code *code, rtx *op0, rtx *op1) 2593 { 2594 rtx tmp0, tmp1, cmp_op0 = *op0, cmp_op1 = *op1; 2595 enum rtx_code fp_code = *code; 2596 *code = NE; 2597 2598 switch (fp_code) 2599 { 2600 case UNORDERED: 2601 *code = EQ; 2602 /* Fall through. */ 2603 2604 case ORDERED: 2605 /* a == a && b == b */ 2606 tmp0 = riscv_force_binary (word_mode, EQ, cmp_op0, cmp_op0); 2607 tmp1 = riscv_force_binary (word_mode, EQ, cmp_op1, cmp_op1); 2608 *op0 = riscv_force_binary (word_mode, AND, tmp0, tmp1); 2609 *op1 = const0_rtx; 2610 break; 2611 2612 case UNEQ: 2613 /* ordered(a, b) > (a == b) */ 2614 *code = EQ; 2615 tmp0 = riscv_force_binary (word_mode, EQ, cmp_op0, cmp_op0); 2616 tmp1 = riscv_force_binary (word_mode, EQ, cmp_op1, cmp_op1); 2617 *op0 = riscv_force_binary (word_mode, AND, tmp0, tmp1); 2618 *op1 = riscv_force_binary (word_mode, EQ, cmp_op0, cmp_op1); 2619 break; 2620 2621 #define UNORDERED_COMPARISON(CODE, CMP) \ 2622 case CODE: \ 2623 *code = EQ; \ 2624 *op0 = gen_reg_rtx (word_mode); \ 2625 if (GET_MODE (cmp_op0) == SFmode && TARGET_64BIT) \ 2626 emit_insn (gen_f##CMP##_quietsfdi4 (*op0, cmp_op0, cmp_op1)); \ 2627 else if (GET_MODE (cmp_op0) == SFmode) \ 2628 emit_insn (gen_f##CMP##_quietsfsi4 (*op0, cmp_op0, cmp_op1)); \ 2629 else if (GET_MODE (cmp_op0) == DFmode && TARGET_64BIT) \ 2630 emit_insn (gen_f##CMP##_quietdfdi4 (*op0, cmp_op0, cmp_op1)); \ 2631 else if (GET_MODE (cmp_op0) == DFmode) \ 2632 emit_insn (gen_f##CMP##_quietdfsi4 (*op0, cmp_op0, cmp_op1)); \ 2633 else \ 2634 gcc_unreachable (); \ 2635 *op1 = const0_rtx; \ 2636 break; 2637 2638 case UNLT: 2639 std::swap (cmp_op0, cmp_op1); 2640 gcc_fallthrough (); 2641 2642 UNORDERED_COMPARISON(UNGT, le) 2643 2644 case UNLE: 2645 std::swap (cmp_op0, cmp_op1); 2646 gcc_fallthrough (); 2647 2648 UNORDERED_COMPARISON(UNGE, lt) 2649 #undef UNORDERED_COMPARISON 2650 2651 case NE: 2652 fp_code = EQ; 2653 *code = EQ; 2654 /* Fall through. */ 2655 2656 case EQ: 2657 case LE: 2658 case LT: 2659 case GE: 2660 case GT: 2661 /* We have instructions for these cases. */ 2662 *op0 = riscv_force_binary (word_mode, fp_code, cmp_op0, cmp_op1); 2663 *op1 = const0_rtx; 2664 break; 2665 2666 case LTGT: 2667 /* (a < b) | (a > b) */ 2668 tmp0 = riscv_force_binary (word_mode, LT, cmp_op0, cmp_op1); 2669 tmp1 = riscv_force_binary (word_mode, GT, cmp_op0, cmp_op1); 2670 *op0 = riscv_force_binary (word_mode, IOR, tmp0, tmp1); 2671 *op1 = const0_rtx; 2672 break; 2673 2674 default: 2675 gcc_unreachable (); 2676 } 2677 } 2678 2679 /* CODE-compare OP0 and OP1. Store the result in TARGET. */ 2680 2681 void 2682 riscv_expand_int_scc (rtx target, enum rtx_code code, rtx op0, rtx op1) 2683 { 2684 riscv_extend_comparands (code, &op0, &op1); 2685 op0 = force_reg (word_mode, op0); 2686 2687 if (code == EQ || code == NE) 2688 { 2689 rtx zie = riscv_zero_if_equal (op0, op1); 2690 riscv_emit_binary (code, target, zie, const0_rtx); 2691 } 2692 else 2693 riscv_emit_int_order_test (code, 0, target, op0, op1); 2694 } 2695 2696 /* Like riscv_expand_int_scc, but for floating-point comparisons. */ 2697 2698 void 2699 riscv_expand_float_scc (rtx target, enum rtx_code code, rtx op0, rtx op1) 2700 { 2701 riscv_emit_float_compare (&code, &op0, &op1); 2702 2703 rtx cmp = riscv_force_binary (word_mode, code, op0, op1); 2704 riscv_emit_set (target, lowpart_subreg (SImode, cmp, word_mode)); 2705 } 2706 2707 /* Jump to LABEL if (CODE OP0 OP1) holds. */ 2708 2709 void 2710 riscv_expand_conditional_branch (rtx label, rtx_code code, rtx op0, rtx op1) 2711 { 2712 if (FLOAT_MODE_P (GET_MODE (op1))) 2713 riscv_emit_float_compare (&code, &op0, &op1); 2714 else 2715 riscv_emit_int_compare (&code, &op0, &op1); 2716 2717 rtx condition = gen_rtx_fmt_ee (code, VOIDmode, op0, op1); 2718 emit_jump_insn (gen_condjump (condition, label)); 2719 } 2720 2721 /* If (CODE OP0 OP1) holds, move CONS to DEST; else move ALT to DEST. */ 2722 2723 void 2724 riscv_expand_conditional_move (rtx dest, rtx cons, rtx alt, rtx_code code, 2725 rtx op0, rtx op1) 2726 { 2727 riscv_emit_int_compare (&code, &op0, &op1); 2728 rtx cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1); 2729 emit_insn (gen_rtx_SET (dest, gen_rtx_IF_THEN_ELSE (GET_MODE (dest), cond, 2730 cons, alt))); 2731 } 2732 2733 /* Implement TARGET_FUNCTION_ARG_BOUNDARY. Every parameter gets at 2734 least PARM_BOUNDARY bits of alignment, but will be given anything up 2735 to PREFERRED_STACK_BOUNDARY bits if the type requires it. */ 2736 2737 static unsigned int 2738 riscv_function_arg_boundary (machine_mode mode, const_tree type) 2739 { 2740 unsigned int alignment; 2741 2742 /* Use natural alignment if the type is not aggregate data. */ 2743 if (type && !AGGREGATE_TYPE_P (type)) 2744 alignment = TYPE_ALIGN (TYPE_MAIN_VARIANT (type)); 2745 else 2746 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode); 2747 2748 return MIN (PREFERRED_STACK_BOUNDARY, MAX (PARM_BOUNDARY, alignment)); 2749 } 2750 2751 /* If MODE represents an argument that can be passed or returned in 2752 floating-point registers, return the number of registers, else 0. */ 2753 2754 static unsigned 2755 riscv_pass_mode_in_fpr_p (machine_mode mode) 2756 { 2757 if (GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FP_ARG) 2758 { 2759 if (GET_MODE_CLASS (mode) == MODE_FLOAT) 2760 return 1; 2761 2762 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) 2763 return 2; 2764 } 2765 2766 return 0; 2767 } 2768 2769 typedef struct { 2770 const_tree type; 2771 HOST_WIDE_INT offset; 2772 } riscv_aggregate_field; 2773 2774 /* Identify subfields of aggregates that are candidates for passing in 2775 floating-point registers. */ 2776 2777 static int 2778 riscv_flatten_aggregate_field (const_tree type, 2779 riscv_aggregate_field fields[2], 2780 int n, HOST_WIDE_INT offset, 2781 bool ignore_zero_width_bit_field_p) 2782 { 2783 switch (TREE_CODE (type)) 2784 { 2785 case RECORD_TYPE: 2786 /* Can't handle incomplete types nor sizes that are not fixed. */ 2787 if (!COMPLETE_TYPE_P (type) 2788 || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST 2789 || !tree_fits_uhwi_p (TYPE_SIZE (type))) 2790 return -1; 2791 2792 for (tree f = TYPE_FIELDS (type); f; f = DECL_CHAIN (f)) 2793 if (TREE_CODE (f) == FIELD_DECL) 2794 { 2795 if (!TYPE_P (TREE_TYPE (f))) 2796 return -1; 2797 2798 /* The C++ front end strips zero-length bit-fields from structs. 2799 So we need to ignore them in the C front end to make C code 2800 compatible with C++ code. */ 2801 if (ignore_zero_width_bit_field_p 2802 && DECL_BIT_FIELD (f) 2803 && (DECL_SIZE (f) == NULL_TREE 2804 || integer_zerop (DECL_SIZE (f)))) 2805 ; 2806 else 2807 { 2808 HOST_WIDE_INT pos = offset + int_byte_position (f); 2809 n = riscv_flatten_aggregate_field (TREE_TYPE (f), 2810 fields, n, pos, 2811 ignore_zero_width_bit_field_p); 2812 } 2813 if (n < 0) 2814 return -1; 2815 } 2816 return n; 2817 2818 case ARRAY_TYPE: 2819 { 2820 HOST_WIDE_INT n_elts; 2821 riscv_aggregate_field subfields[2]; 2822 tree index = TYPE_DOMAIN (type); 2823 tree elt_size = TYPE_SIZE_UNIT (TREE_TYPE (type)); 2824 int n_subfields = riscv_flatten_aggregate_field (TREE_TYPE (type), 2825 subfields, 0, offset, 2826 ignore_zero_width_bit_field_p); 2827 2828 /* Can't handle incomplete types nor sizes that are not fixed. */ 2829 if (n_subfields <= 0 2830 || !COMPLETE_TYPE_P (type) 2831 || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST 2832 || !index 2833 || !TYPE_MAX_VALUE (index) 2834 || !tree_fits_uhwi_p (TYPE_MAX_VALUE (index)) 2835 || !TYPE_MIN_VALUE (index) 2836 || !tree_fits_uhwi_p (TYPE_MIN_VALUE (index)) 2837 || !tree_fits_uhwi_p (elt_size)) 2838 return -1; 2839 2840 n_elts = 1 + tree_to_uhwi (TYPE_MAX_VALUE (index)) 2841 - tree_to_uhwi (TYPE_MIN_VALUE (index)); 2842 gcc_assert (n_elts >= 0); 2843 2844 for (HOST_WIDE_INT i = 0; i < n_elts; i++) 2845 for (int j = 0; j < n_subfields; j++) 2846 { 2847 if (n >= 2) 2848 return -1; 2849 2850 fields[n] = subfields[j]; 2851 fields[n++].offset += i * tree_to_uhwi (elt_size); 2852 } 2853 2854 return n; 2855 } 2856 2857 case COMPLEX_TYPE: 2858 { 2859 /* Complex type need consume 2 field, so n must be 0. */ 2860 if (n != 0) 2861 return -1; 2862 2863 HOST_WIDE_INT elt_size = GET_MODE_SIZE (TYPE_MODE (TREE_TYPE (type))); 2864 2865 if (elt_size <= UNITS_PER_FP_ARG) 2866 { 2867 fields[0].type = TREE_TYPE (type); 2868 fields[0].offset = offset; 2869 fields[1].type = TREE_TYPE (type); 2870 fields[1].offset = offset + elt_size; 2871 2872 return 2; 2873 } 2874 2875 return -1; 2876 } 2877 2878 default: 2879 if (n < 2 2880 && ((SCALAR_FLOAT_TYPE_P (type) 2881 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FP_ARG) 2882 || (INTEGRAL_TYPE_P (type) 2883 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_WORD))) 2884 { 2885 fields[n].type = type; 2886 fields[n].offset = offset; 2887 return n + 1; 2888 } 2889 else 2890 return -1; 2891 } 2892 } 2893 2894 /* Identify candidate aggregates for passing in floating-point registers. 2895 Candidates have at most two fields after flattening. */ 2896 2897 static int 2898 riscv_flatten_aggregate_argument (const_tree type, 2899 riscv_aggregate_field fields[2], 2900 bool ignore_zero_width_bit_field_p) 2901 { 2902 if (!type || TREE_CODE (type) != RECORD_TYPE) 2903 return -1; 2904 2905 return riscv_flatten_aggregate_field (type, fields, 0, 0, 2906 ignore_zero_width_bit_field_p); 2907 } 2908 2909 /* See whether TYPE is a record whose fields should be returned in one or 2910 two floating-point registers. If so, populate FIELDS accordingly. */ 2911 2912 static unsigned 2913 riscv_pass_aggregate_in_fpr_pair_p (const_tree type, 2914 riscv_aggregate_field fields[2]) 2915 { 2916 static int warned = 0; 2917 2918 /* This is the old ABI, which differs for C++ and C. */ 2919 int n_old = riscv_flatten_aggregate_argument (type, fields, false); 2920 for (int i = 0; i < n_old; i++) 2921 if (!SCALAR_FLOAT_TYPE_P (fields[i].type)) 2922 { 2923 n_old = -1; 2924 break; 2925 } 2926 2927 /* This is the new ABI, which is the same for C++ and C. */ 2928 int n_new = riscv_flatten_aggregate_argument (type, fields, true); 2929 for (int i = 0; i < n_new; i++) 2930 if (!SCALAR_FLOAT_TYPE_P (fields[i].type)) 2931 { 2932 n_new = -1; 2933 break; 2934 } 2935 2936 if ((n_old != n_new) && (warned == 0)) 2937 { 2938 warning (OPT_Wpsabi, "ABI for flattened struct with zero-length " 2939 "bit-fields changed in GCC 10"); 2940 warned = 1; 2941 } 2942 2943 return n_new > 0 ? n_new : 0; 2944 } 2945 2946 /* See whether TYPE is a record whose fields should be returned in one or 2947 floating-point register and one integer register. If so, populate 2948 FIELDS accordingly. */ 2949 2950 static bool 2951 riscv_pass_aggregate_in_fpr_and_gpr_p (const_tree type, 2952 riscv_aggregate_field fields[2]) 2953 { 2954 static int warned = 0; 2955 2956 /* This is the old ABI, which differs for C++ and C. */ 2957 unsigned num_int_old = 0, num_float_old = 0; 2958 int n_old = riscv_flatten_aggregate_argument (type, fields, false); 2959 for (int i = 0; i < n_old; i++) 2960 { 2961 num_float_old += SCALAR_FLOAT_TYPE_P (fields[i].type); 2962 num_int_old += INTEGRAL_TYPE_P (fields[i].type); 2963 } 2964 2965 /* This is the new ABI, which is the same for C++ and C. */ 2966 unsigned num_int_new = 0, num_float_new = 0; 2967 int n_new = riscv_flatten_aggregate_argument (type, fields, true); 2968 for (int i = 0; i < n_new; i++) 2969 { 2970 num_float_new += SCALAR_FLOAT_TYPE_P (fields[i].type); 2971 num_int_new += INTEGRAL_TYPE_P (fields[i].type); 2972 } 2973 2974 if (((num_int_old == 1 && num_float_old == 1 2975 && (num_int_old != num_int_new || num_float_old != num_float_new)) 2976 || (num_int_new == 1 && num_float_new == 1 2977 && (num_int_old != num_int_new || num_float_old != num_float_new))) 2978 && (warned == 0)) 2979 { 2980 warning (OPT_Wpsabi, "ABI for flattened struct with zero-length " 2981 "bit-fields changed in GCC 10"); 2982 warned = 1; 2983 } 2984 2985 return num_int_new == 1 && num_float_new == 1; 2986 } 2987 2988 /* Return the representation of an argument passed or returned in an FPR 2989 when the value has mode VALUE_MODE and the type has TYPE_MODE. The 2990 two modes may be different for structures like: 2991 2992 struct __attribute__((packed)) foo { float f; } 2993 2994 where the SFmode value "f" is passed in REGNO but the struct itself 2995 has mode BLKmode. */ 2996 2997 static rtx 2998 riscv_pass_fpr_single (machine_mode type_mode, unsigned regno, 2999 machine_mode value_mode, 3000 HOST_WIDE_INT offset) 3001 { 3002 rtx x = gen_rtx_REG (value_mode, regno); 3003 3004 if (type_mode != value_mode) 3005 { 3006 x = gen_rtx_EXPR_LIST (VOIDmode, x, GEN_INT (offset)); 3007 x = gen_rtx_PARALLEL (type_mode, gen_rtvec (1, x)); 3008 } 3009 return x; 3010 } 3011 3012 /* Pass or return a composite value in the FPR pair REGNO and REGNO + 1. 3013 MODE is the mode of the composite. MODE1 and OFFSET1 are the mode and 3014 byte offset for the first value, likewise MODE2 and OFFSET2 for the 3015 second value. */ 3016 3017 static rtx 3018 riscv_pass_fpr_pair (machine_mode mode, unsigned regno1, 3019 machine_mode mode1, HOST_WIDE_INT offset1, 3020 unsigned regno2, machine_mode mode2, 3021 HOST_WIDE_INT offset2) 3022 { 3023 return gen_rtx_PARALLEL 3024 (mode, 3025 gen_rtvec (2, 3026 gen_rtx_EXPR_LIST (VOIDmode, 3027 gen_rtx_REG (mode1, regno1), 3028 GEN_INT (offset1)), 3029 gen_rtx_EXPR_LIST (VOIDmode, 3030 gen_rtx_REG (mode2, regno2), 3031 GEN_INT (offset2)))); 3032 } 3033 3034 /* Fill INFO with information about a single argument, and return an 3035 RTL pattern to pass or return the argument. CUM is the cumulative 3036 state for earlier arguments. MODE is the mode of this argument and 3037 TYPE is its type (if known). NAMED is true if this is a named 3038 (fixed) argument rather than a variable one. RETURN_P is true if 3039 returning the argument, or false if passing the argument. */ 3040 3041 static rtx 3042 riscv_get_arg_info (struct riscv_arg_info *info, const CUMULATIVE_ARGS *cum, 3043 machine_mode mode, const_tree type, bool named, 3044 bool return_p) 3045 { 3046 unsigned num_bytes, num_words; 3047 unsigned fpr_base = return_p ? FP_RETURN : FP_ARG_FIRST; 3048 unsigned gpr_base = return_p ? GP_RETURN : GP_ARG_FIRST; 3049 unsigned alignment = riscv_function_arg_boundary (mode, type); 3050 3051 memset (info, 0, sizeof (*info)); 3052 info->gpr_offset = cum->num_gprs; 3053 info->fpr_offset = cum->num_fprs; 3054 3055 if (named) 3056 { 3057 riscv_aggregate_field fields[2]; 3058 unsigned fregno = fpr_base + info->fpr_offset; 3059 unsigned gregno = gpr_base + info->gpr_offset; 3060 3061 /* Pass one- or two-element floating-point aggregates in FPRs. */ 3062 if ((info->num_fprs = riscv_pass_aggregate_in_fpr_pair_p (type, fields)) 3063 && info->fpr_offset + info->num_fprs <= MAX_ARGS_IN_REGISTERS) 3064 switch (info->num_fprs) 3065 { 3066 case 1: 3067 return riscv_pass_fpr_single (mode, fregno, 3068 TYPE_MODE (fields[0].type), 3069 fields[0].offset); 3070 3071 case 2: 3072 return riscv_pass_fpr_pair (mode, fregno, 3073 TYPE_MODE (fields[0].type), 3074 fields[0].offset, 3075 fregno + 1, 3076 TYPE_MODE (fields[1].type), 3077 fields[1].offset); 3078 3079 default: 3080 gcc_unreachable (); 3081 } 3082 3083 /* Pass real and complex floating-point numbers in FPRs. */ 3084 if ((info->num_fprs = riscv_pass_mode_in_fpr_p (mode)) 3085 && info->fpr_offset + info->num_fprs <= MAX_ARGS_IN_REGISTERS) 3086 switch (GET_MODE_CLASS (mode)) 3087 { 3088 case MODE_FLOAT: 3089 return gen_rtx_REG (mode, fregno); 3090 3091 case MODE_COMPLEX_FLOAT: 3092 return riscv_pass_fpr_pair (mode, fregno, GET_MODE_INNER (mode), 0, 3093 fregno + 1, GET_MODE_INNER (mode), 3094 GET_MODE_UNIT_SIZE (mode)); 3095 3096 default: 3097 gcc_unreachable (); 3098 } 3099 3100 /* Pass structs with one float and one integer in an FPR and a GPR. */ 3101 if (riscv_pass_aggregate_in_fpr_and_gpr_p (type, fields) 3102 && info->gpr_offset < MAX_ARGS_IN_REGISTERS 3103 && info->fpr_offset < MAX_ARGS_IN_REGISTERS) 3104 { 3105 info->num_gprs = 1; 3106 info->num_fprs = 1; 3107 3108 if (!SCALAR_FLOAT_TYPE_P (fields[0].type)) 3109 std::swap (fregno, gregno); 3110 3111 return riscv_pass_fpr_pair (mode, fregno, TYPE_MODE (fields[0].type), 3112 fields[0].offset, 3113 gregno, TYPE_MODE (fields[1].type), 3114 fields[1].offset); 3115 } 3116 } 3117 3118 /* Work out the size of the argument. */ 3119 num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode); 3120 num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD; 3121 3122 /* Doubleword-aligned varargs start on an even register boundary. */ 3123 if (!named && num_bytes != 0 && alignment > BITS_PER_WORD) 3124 info->gpr_offset += info->gpr_offset & 1; 3125 3126 /* Partition the argument between registers and stack. */ 3127 info->num_fprs = 0; 3128 info->num_gprs = MIN (num_words, MAX_ARGS_IN_REGISTERS - info->gpr_offset); 3129 info->stack_p = (num_words - info->num_gprs) != 0; 3130 3131 if (info->num_gprs || return_p) 3132 return gen_rtx_REG (mode, gpr_base + info->gpr_offset); 3133 3134 return NULL_RTX; 3135 } 3136 3137 /* Implement TARGET_FUNCTION_ARG. */ 3138 3139 static rtx 3140 riscv_function_arg (cumulative_args_t cum_v, const function_arg_info &arg) 3141 { 3142 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); 3143 struct riscv_arg_info info; 3144 3145 if (arg.end_marker_p ()) 3146 return NULL; 3147 3148 return riscv_get_arg_info (&info, cum, arg.mode, arg.type, arg.named, false); 3149 } 3150 3151 /* Implement TARGET_FUNCTION_ARG_ADVANCE. */ 3152 3153 static void 3154 riscv_function_arg_advance (cumulative_args_t cum_v, 3155 const function_arg_info &arg) 3156 { 3157 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); 3158 struct riscv_arg_info info; 3159 3160 riscv_get_arg_info (&info, cum, arg.mode, arg.type, arg.named, false); 3161 3162 /* Advance the register count. This has the effect of setting 3163 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned 3164 argument required us to skip the final GPR and pass the whole 3165 argument on the stack. */ 3166 cum->num_fprs = info.fpr_offset + info.num_fprs; 3167 cum->num_gprs = info.gpr_offset + info.num_gprs; 3168 } 3169 3170 /* Implement TARGET_ARG_PARTIAL_BYTES. */ 3171 3172 static int 3173 riscv_arg_partial_bytes (cumulative_args_t cum, 3174 const function_arg_info &generic_arg) 3175 { 3176 struct riscv_arg_info arg; 3177 3178 riscv_get_arg_info (&arg, get_cumulative_args (cum), generic_arg.mode, 3179 generic_arg.type, generic_arg.named, false); 3180 return arg.stack_p ? arg.num_gprs * UNITS_PER_WORD : 0; 3181 } 3182 3183 /* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls, 3184 VALTYPE is the return type and MODE is VOIDmode. For libcalls, 3185 VALTYPE is null and MODE is the mode of the return value. */ 3186 3187 rtx 3188 riscv_function_value (const_tree type, const_tree func, machine_mode mode) 3189 { 3190 struct riscv_arg_info info; 3191 CUMULATIVE_ARGS args; 3192 3193 if (type) 3194 { 3195 int unsigned_p = TYPE_UNSIGNED (type); 3196 3197 mode = TYPE_MODE (type); 3198 3199 /* Since TARGET_PROMOTE_FUNCTION_MODE unconditionally promotes, 3200 return values, promote the mode here too. */ 3201 mode = promote_function_mode (type, mode, &unsigned_p, func, 1); 3202 } 3203 3204 memset (&args, 0, sizeof args); 3205 return riscv_get_arg_info (&info, &args, mode, type, true, true); 3206 } 3207 3208 /* Implement TARGET_PASS_BY_REFERENCE. */ 3209 3210 static bool 3211 riscv_pass_by_reference (cumulative_args_t cum_v, const function_arg_info &arg) 3212 { 3213 HOST_WIDE_INT size = arg.type_size_in_bytes (); 3214 struct riscv_arg_info info; 3215 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); 3216 3217 /* ??? std_gimplify_va_arg_expr passes NULL for cum. Fortunately, we 3218 never pass variadic arguments in floating-point registers, so we can 3219 avoid the call to riscv_get_arg_info in this case. */ 3220 if (cum != NULL) 3221 { 3222 /* Don't pass by reference if we can use a floating-point register. */ 3223 riscv_get_arg_info (&info, cum, arg.mode, arg.type, arg.named, false); 3224 if (info.num_fprs) 3225 return false; 3226 } 3227 3228 /* Pass by reference if the data do not fit in two integer registers. */ 3229 return !IN_RANGE (size, 0, 2 * UNITS_PER_WORD); 3230 } 3231 3232 /* Implement TARGET_RETURN_IN_MEMORY. */ 3233 3234 static bool 3235 riscv_return_in_memory (const_tree type, const_tree fndecl ATTRIBUTE_UNUSED) 3236 { 3237 CUMULATIVE_ARGS args; 3238 cumulative_args_t cum = pack_cumulative_args (&args); 3239 3240 /* The rules for returning in memory are the same as for passing the 3241 first named argument by reference. */ 3242 memset (&args, 0, sizeof args); 3243 function_arg_info arg (const_cast<tree> (type), /*named=*/true); 3244 return riscv_pass_by_reference (cum, arg); 3245 } 3246 3247 /* Implement TARGET_SETUP_INCOMING_VARARGS. */ 3248 3249 static void 3250 riscv_setup_incoming_varargs (cumulative_args_t cum, 3251 const function_arg_info &arg, 3252 int *pretend_size ATTRIBUTE_UNUSED, int no_rtl) 3253 { 3254 CUMULATIVE_ARGS local_cum; 3255 int gp_saved; 3256 3257 /* The caller has advanced CUM up to, but not beyond, the last named 3258 argument. Advance a local copy of CUM past the last "real" named 3259 argument, to find out how many registers are left over. */ 3260 local_cum = *get_cumulative_args (cum); 3261 riscv_function_arg_advance (pack_cumulative_args (&local_cum), arg); 3262 3263 /* Found out how many registers we need to save. */ 3264 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs; 3265 3266 if (!no_rtl && gp_saved > 0) 3267 { 3268 rtx ptr = plus_constant (Pmode, virtual_incoming_args_rtx, 3269 REG_PARM_STACK_SPACE (cfun->decl) 3270 - gp_saved * UNITS_PER_WORD); 3271 rtx mem = gen_frame_mem (BLKmode, ptr); 3272 set_mem_alias_set (mem, get_varargs_alias_set ()); 3273 3274 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST, 3275 mem, gp_saved); 3276 } 3277 if (REG_PARM_STACK_SPACE (cfun->decl) == 0) 3278 cfun->machine->varargs_size = gp_saved * UNITS_PER_WORD; 3279 } 3280 3281 /* Handle an attribute requiring a FUNCTION_DECL; 3282 arguments as in struct attribute_spec.handler. */ 3283 static tree 3284 riscv_handle_fndecl_attribute (tree *node, tree name, 3285 tree args ATTRIBUTE_UNUSED, 3286 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs) 3287 { 3288 if (TREE_CODE (*node) != FUNCTION_DECL) 3289 { 3290 warning (OPT_Wattributes, "%qE attribute only applies to functions", 3291 name); 3292 *no_add_attrs = true; 3293 } 3294 3295 return NULL_TREE; 3296 } 3297 3298 /* Verify type based attributes. NODE is the what the attribute is being 3299 applied to. NAME is the attribute name. ARGS are the attribute args. 3300 FLAGS gives info about the context. NO_ADD_ATTRS should be set to true if 3301 the attribute should be ignored. */ 3302 3303 static tree 3304 riscv_handle_type_attribute (tree *node ATTRIBUTE_UNUSED, tree name, tree args, 3305 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs) 3306 { 3307 /* Check for an argument. */ 3308 if (is_attribute_p ("interrupt", name)) 3309 { 3310 if (args) 3311 { 3312 tree cst = TREE_VALUE (args); 3313 const char *string; 3314 3315 if (TREE_CODE (cst) != STRING_CST) 3316 { 3317 warning (OPT_Wattributes, 3318 "%qE attribute requires a string argument", 3319 name); 3320 *no_add_attrs = true; 3321 return NULL_TREE; 3322 } 3323 3324 string = TREE_STRING_POINTER (cst); 3325 if (strcmp (string, "user") && strcmp (string, "supervisor") 3326 && strcmp (string, "machine")) 3327 { 3328 warning (OPT_Wattributes, 3329 "argument to %qE attribute is not %<\"user\"%>, %<\"supervisor\"%>, " 3330 "or %<\"machine\"%>", name); 3331 *no_add_attrs = true; 3332 } 3333 } 3334 } 3335 3336 return NULL_TREE; 3337 } 3338 3339 /* Return true if function TYPE is an interrupt function. */ 3340 static bool 3341 riscv_interrupt_type_p (tree type) 3342 { 3343 return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type)) != NULL; 3344 } 3345 3346 /* Return true if FUNC is a naked function. */ 3347 static bool 3348 riscv_naked_function_p (tree func) 3349 { 3350 tree func_decl = func; 3351 if (func == NULL_TREE) 3352 func_decl = current_function_decl; 3353 return NULL_TREE != lookup_attribute ("naked", DECL_ATTRIBUTES (func_decl)); 3354 } 3355 3356 /* Implement TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS. */ 3357 static bool 3358 riscv_allocate_stack_slots_for_args () 3359 { 3360 /* Naked functions should not allocate stack slots for arguments. */ 3361 return !riscv_naked_function_p (current_function_decl); 3362 } 3363 3364 /* Implement TARGET_WARN_FUNC_RETURN. */ 3365 static bool 3366 riscv_warn_func_return (tree decl) 3367 { 3368 /* Naked functions are implemented entirely in assembly, including the 3369 return sequence, so suppress warnings about this. */ 3370 return !riscv_naked_function_p (decl); 3371 } 3372 3373 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */ 3374 3375 static void 3376 riscv_va_start (tree valist, rtx nextarg) 3377 { 3378 nextarg = plus_constant (Pmode, nextarg, -cfun->machine->varargs_size); 3379 std_expand_builtin_va_start (valist, nextarg); 3380 } 3381 3382 /* Make ADDR suitable for use as a call or sibcall target. */ 3383 3384 rtx 3385 riscv_legitimize_call_address (rtx addr) 3386 { 3387 if (!call_insn_operand (addr, VOIDmode)) 3388 { 3389 rtx reg = RISCV_CALL_ADDRESS_TEMP (Pmode); 3390 riscv_emit_move (reg, addr); 3391 return reg; 3392 } 3393 return addr; 3394 } 3395 3396 /* Emit straight-line code to move LENGTH bytes from SRC to DEST. 3397 Assume that the areas do not overlap. */ 3398 3399 static void 3400 riscv_block_move_straight (rtx dest, rtx src, unsigned HOST_WIDE_INT length) 3401 { 3402 unsigned HOST_WIDE_INT offset, delta; 3403 unsigned HOST_WIDE_INT bits; 3404 int i; 3405 enum machine_mode mode; 3406 rtx *regs; 3407 3408 bits = MAX (BITS_PER_UNIT, 3409 MIN (BITS_PER_WORD, MIN (MEM_ALIGN (src), MEM_ALIGN (dest)))); 3410 3411 mode = mode_for_size (bits, MODE_INT, 0).require (); 3412 delta = bits / BITS_PER_UNIT; 3413 3414 /* Allocate a buffer for the temporary registers. */ 3415 regs = XALLOCAVEC (rtx, length / delta); 3416 3417 /* Load as many BITS-sized chunks as possible. Use a normal load if 3418 the source has enough alignment, otherwise use left/right pairs. */ 3419 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++) 3420 { 3421 regs[i] = gen_reg_rtx (mode); 3422 riscv_emit_move (regs[i], adjust_address (src, mode, offset)); 3423 } 3424 3425 /* Copy the chunks to the destination. */ 3426 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++) 3427 riscv_emit_move (adjust_address (dest, mode, offset), regs[i]); 3428 3429 /* Mop up any left-over bytes. */ 3430 if (offset < length) 3431 { 3432 src = adjust_address (src, BLKmode, offset); 3433 dest = adjust_address (dest, BLKmode, offset); 3434 move_by_pieces (dest, src, length - offset, 3435 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), RETURN_BEGIN); 3436 } 3437 } 3438 3439 /* Helper function for doing a loop-based block operation on memory 3440 reference MEM. Each iteration of the loop will operate on LENGTH 3441 bytes of MEM. 3442 3443 Create a new base register for use within the loop and point it to 3444 the start of MEM. Create a new memory reference that uses this 3445 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */ 3446 3447 static void 3448 riscv_adjust_block_mem (rtx mem, unsigned HOST_WIDE_INT length, 3449 rtx *loop_reg, rtx *loop_mem) 3450 { 3451 *loop_reg = copy_addr_to_reg (XEXP (mem, 0)); 3452 3453 /* Although the new mem does not refer to a known location, 3454 it does keep up to LENGTH bytes of alignment. */ 3455 *loop_mem = change_address (mem, BLKmode, *loop_reg); 3456 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT)); 3457 } 3458 3459 /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER 3460 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that 3461 the memory regions do not overlap. */ 3462 3463 static void 3464 riscv_block_move_loop (rtx dest, rtx src, unsigned HOST_WIDE_INT length, 3465 unsigned HOST_WIDE_INT bytes_per_iter) 3466 { 3467 rtx label, src_reg, dest_reg, final_src, test; 3468 unsigned HOST_WIDE_INT leftover; 3469 3470 leftover = length % bytes_per_iter; 3471 length -= leftover; 3472 3473 /* Create registers and memory references for use within the loop. */ 3474 riscv_adjust_block_mem (src, bytes_per_iter, &src_reg, &src); 3475 riscv_adjust_block_mem (dest, bytes_per_iter, &dest_reg, &dest); 3476 3477 /* Calculate the value that SRC_REG should have after the last iteration 3478 of the loop. */ 3479 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length), 3480 0, 0, OPTAB_WIDEN); 3481 3482 /* Emit the start of the loop. */ 3483 label = gen_label_rtx (); 3484 emit_label (label); 3485 3486 /* Emit the loop body. */ 3487 riscv_block_move_straight (dest, src, bytes_per_iter); 3488 3489 /* Move on to the next block. */ 3490 riscv_emit_move (src_reg, plus_constant (Pmode, src_reg, bytes_per_iter)); 3491 riscv_emit_move (dest_reg, plus_constant (Pmode, dest_reg, bytes_per_iter)); 3492 3493 /* Emit the loop condition. */ 3494 test = gen_rtx_NE (VOIDmode, src_reg, final_src); 3495 emit_jump_insn (gen_cbranch4 (Pmode, test, src_reg, final_src, label)); 3496 3497 /* Mop up any left-over bytes. */ 3498 if (leftover) 3499 riscv_block_move_straight (dest, src, leftover); 3500 else 3501 emit_insn(gen_nop ()); 3502 } 3503 3504 /* Expand a cpymemsi instruction, which copies LENGTH bytes from 3505 memory reference SRC to memory reference DEST. */ 3506 3507 bool 3508 riscv_expand_block_move (rtx dest, rtx src, rtx length) 3509 { 3510 if (CONST_INT_P (length)) 3511 { 3512 unsigned HOST_WIDE_INT hwi_length = UINTVAL (length); 3513 unsigned HOST_WIDE_INT factor, align; 3514 3515 align = MIN (MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), BITS_PER_WORD); 3516 factor = BITS_PER_WORD / align; 3517 3518 if (optimize_function_for_size_p (cfun) 3519 && hwi_length * factor * UNITS_PER_WORD > MOVE_RATIO (false)) 3520 return false; 3521 3522 if (hwi_length <= (RISCV_MAX_MOVE_BYTES_STRAIGHT / factor)) 3523 { 3524 riscv_block_move_straight (dest, src, INTVAL (length)); 3525 return true; 3526 } 3527 else if (optimize && align >= BITS_PER_WORD) 3528 { 3529 unsigned min_iter_words 3530 = RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER / UNITS_PER_WORD; 3531 unsigned iter_words = min_iter_words; 3532 unsigned HOST_WIDE_INT bytes = hwi_length; 3533 unsigned HOST_WIDE_INT words = bytes / UNITS_PER_WORD; 3534 3535 /* Lengthen the loop body if it shortens the tail. */ 3536 for (unsigned i = min_iter_words; i < min_iter_words * 2 - 1; i++) 3537 { 3538 unsigned cur_cost = iter_words + words % iter_words; 3539 unsigned new_cost = i + words % i; 3540 if (new_cost <= cur_cost) 3541 iter_words = i; 3542 } 3543 3544 riscv_block_move_loop (dest, src, bytes, iter_words * UNITS_PER_WORD); 3545 return true; 3546 } 3547 } 3548 return false; 3549 } 3550 3551 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM 3552 in context CONTEXT. HI_RELOC indicates a high-part reloc. */ 3553 3554 static void 3555 riscv_print_operand_reloc (FILE *file, rtx op, bool hi_reloc) 3556 { 3557 const char *reloc; 3558 3559 switch (riscv_classify_symbolic_expression (op)) 3560 { 3561 case SYMBOL_ABSOLUTE: 3562 reloc = hi_reloc ? "%hi" : "%lo"; 3563 break; 3564 3565 case SYMBOL_PCREL: 3566 reloc = hi_reloc ? "%pcrel_hi" : "%pcrel_lo"; 3567 break; 3568 3569 case SYMBOL_TLS_LE: 3570 reloc = hi_reloc ? "%tprel_hi" : "%tprel_lo"; 3571 break; 3572 3573 default: 3574 output_operand_lossage ("invalid use of '%%%c'", hi_reloc ? 'h' : 'R'); 3575 return; 3576 } 3577 3578 fprintf (file, "%s(", reloc); 3579 output_addr_const (file, riscv_strip_unspec_address (op)); 3580 fputc (')', file); 3581 } 3582 3583 /* Return true if the .AQ suffix should be added to an AMO to implement the 3584 acquire portion of memory model MODEL. */ 3585 3586 static bool 3587 riscv_memmodel_needs_amo_acquire (enum memmodel model) 3588 { 3589 switch (model) 3590 { 3591 case MEMMODEL_ACQ_REL: 3592 case MEMMODEL_SEQ_CST: 3593 case MEMMODEL_SYNC_SEQ_CST: 3594 case MEMMODEL_ACQUIRE: 3595 case MEMMODEL_CONSUME: 3596 case MEMMODEL_SYNC_ACQUIRE: 3597 return true; 3598 3599 case MEMMODEL_RELEASE: 3600 case MEMMODEL_SYNC_RELEASE: 3601 case MEMMODEL_RELAXED: 3602 return false; 3603 3604 default: 3605 gcc_unreachable (); 3606 } 3607 } 3608 3609 /* Return true if a FENCE should be emitted to before a memory access to 3610 implement the release portion of memory model MODEL. */ 3611 3612 static bool 3613 riscv_memmodel_needs_release_fence (enum memmodel model) 3614 { 3615 switch (model) 3616 { 3617 case MEMMODEL_ACQ_REL: 3618 case MEMMODEL_SEQ_CST: 3619 case MEMMODEL_SYNC_SEQ_CST: 3620 case MEMMODEL_RELEASE: 3621 case MEMMODEL_SYNC_RELEASE: 3622 return true; 3623 3624 case MEMMODEL_ACQUIRE: 3625 case MEMMODEL_CONSUME: 3626 case MEMMODEL_SYNC_ACQUIRE: 3627 case MEMMODEL_RELAXED: 3628 return false; 3629 3630 default: 3631 gcc_unreachable (); 3632 } 3633 } 3634 3635 /* Implement TARGET_PRINT_OPERAND. The RISCV-specific operand codes are: 3636 3637 'h' Print the high-part relocation associated with OP, after stripping 3638 any outermost HIGH. 3639 'R' Print the low-part relocation associated with OP. 3640 'C' Print the integer branch condition for comparison OP. 3641 'A' Print the atomic operation suffix for memory model OP. 3642 'F' Print a FENCE if the memory model requires a release. 3643 'z' Print x0 if OP is zero, otherwise print OP normally. 3644 'i' Print i if the operand is not a register. 3645 'S' Print shift-index of single-bit mask OP. 3646 'T' Print shift-index of inverted single-bit mask OP. */ 3647 3648 static void 3649 riscv_print_operand (FILE *file, rtx op, int letter) 3650 { 3651 machine_mode mode = GET_MODE (op); 3652 enum rtx_code code = GET_CODE (op); 3653 3654 switch (letter) 3655 { 3656 case 'h': 3657 if (code == HIGH) 3658 op = XEXP (op, 0); 3659 riscv_print_operand_reloc (file, op, true); 3660 break; 3661 3662 case 'R': 3663 riscv_print_operand_reloc (file, op, false); 3664 break; 3665 3666 case 'C': 3667 /* The RTL names match the instruction names. */ 3668 fputs (GET_RTX_NAME (code), file); 3669 break; 3670 3671 case 'A': 3672 if (riscv_memmodel_needs_amo_acquire ((enum memmodel) INTVAL (op))) 3673 fputs (".aq", file); 3674 break; 3675 3676 case 'F': 3677 if (riscv_memmodel_needs_release_fence ((enum memmodel) INTVAL (op))) 3678 fputs ("fence iorw,ow; ", file); 3679 break; 3680 3681 case 'i': 3682 if (code != REG) 3683 fputs ("i", file); 3684 break; 3685 3686 case 'S': 3687 { 3688 rtx newop = GEN_INT (ctz_hwi (INTVAL (op))); 3689 output_addr_const (file, newop); 3690 break; 3691 } 3692 case 'T': 3693 { 3694 rtx newop = GEN_INT (ctz_hwi (~INTVAL (op))); 3695 output_addr_const (file, newop); 3696 break; 3697 } 3698 default: 3699 switch (code) 3700 { 3701 case REG: 3702 if (letter && letter != 'z') 3703 output_operand_lossage ("invalid use of '%%%c'", letter); 3704 fprintf (file, "%s", reg_names[REGNO (op)]); 3705 break; 3706 3707 case MEM: 3708 if (letter && letter != 'z') 3709 output_operand_lossage ("invalid use of '%%%c'", letter); 3710 else 3711 output_address (mode, XEXP (op, 0)); 3712 break; 3713 3714 default: 3715 if (letter == 'z' && op == CONST0_RTX (GET_MODE (op))) 3716 fputs (reg_names[GP_REG_FIRST], file); 3717 else if (letter && letter != 'z') 3718 output_operand_lossage ("invalid use of '%%%c'", letter); 3719 else 3720 output_addr_const (file, riscv_strip_unspec_address (op)); 3721 break; 3722 } 3723 } 3724 } 3725 3726 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */ 3727 3728 static void 3729 riscv_print_operand_address (FILE *file, machine_mode mode ATTRIBUTE_UNUSED, rtx x) 3730 { 3731 struct riscv_address_info addr; 3732 3733 if (riscv_classify_address (&addr, x, word_mode, true)) 3734 switch (addr.type) 3735 { 3736 case ADDRESS_REG: 3737 riscv_print_operand (file, addr.offset, 0); 3738 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]); 3739 return; 3740 3741 case ADDRESS_LO_SUM: 3742 riscv_print_operand_reloc (file, addr.offset, false); 3743 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]); 3744 return; 3745 3746 case ADDRESS_CONST_INT: 3747 output_addr_const (file, x); 3748 fprintf (file, "(%s)", reg_names[GP_REG_FIRST]); 3749 return; 3750 3751 case ADDRESS_SYMBOLIC: 3752 output_addr_const (file, riscv_strip_unspec_address (x)); 3753 return; 3754 } 3755 gcc_unreachable (); 3756 } 3757 3758 static bool 3759 riscv_size_ok_for_small_data_p (int size) 3760 { 3761 return g_switch_value && IN_RANGE (size, 1, g_switch_value); 3762 } 3763 3764 /* Return true if EXP should be placed in the small data section. */ 3765 3766 static bool 3767 riscv_in_small_data_p (const_tree x) 3768 { 3769 if (TREE_CODE (x) == STRING_CST || TREE_CODE (x) == FUNCTION_DECL) 3770 return false; 3771 3772 if (TREE_CODE (x) == VAR_DECL && DECL_SECTION_NAME (x)) 3773 { 3774 const char *sec = DECL_SECTION_NAME (x); 3775 return strcmp (sec, ".sdata") == 0 || strcmp (sec, ".sbss") == 0; 3776 } 3777 3778 return riscv_size_ok_for_small_data_p (int_size_in_bytes (TREE_TYPE (x))); 3779 } 3780 3781 /* Switch to the appropriate section for output of DECL. */ 3782 3783 static section * 3784 riscv_select_section (tree decl, int reloc, 3785 unsigned HOST_WIDE_INT align) 3786 { 3787 switch (categorize_decl_for_section (decl, reloc)) 3788 { 3789 case SECCAT_SRODATA: 3790 return get_named_section (decl, ".srodata", reloc); 3791 3792 default: 3793 return default_elf_select_section (decl, reloc, align); 3794 } 3795 } 3796 3797 /* Switch to the appropriate section for output of DECL. */ 3798 3799 static void 3800 riscv_unique_section (tree decl, int reloc) 3801 { 3802 const char *prefix = NULL; 3803 bool one_only = DECL_ONE_ONLY (decl) && !HAVE_COMDAT_GROUP; 3804 3805 switch (categorize_decl_for_section (decl, reloc)) 3806 { 3807 case SECCAT_SRODATA: 3808 prefix = one_only ? ".sr" : ".srodata"; 3809 break; 3810 3811 default: 3812 break; 3813 } 3814 if (prefix) 3815 { 3816 const char *name, *linkonce; 3817 char *string; 3818 3819 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl)); 3820 name = targetm.strip_name_encoding (name); 3821 3822 /* If we're using one_only, then there needs to be a .gnu.linkonce 3823 prefix to the section name. */ 3824 linkonce = one_only ? ".gnu.linkonce" : ""; 3825 3826 string = ACONCAT ((linkonce, prefix, ".", name, NULL)); 3827 3828 set_decl_section_name (decl, string); 3829 return; 3830 } 3831 default_unique_section (decl, reloc); 3832 } 3833 3834 /* Return a section for X, handling small data. */ 3835 3836 static section * 3837 riscv_elf_select_rtx_section (machine_mode mode, rtx x, 3838 unsigned HOST_WIDE_INT align) 3839 { 3840 section *s = default_elf_select_rtx_section (mode, x, align); 3841 3842 if (riscv_size_ok_for_small_data_p (GET_MODE_SIZE (mode))) 3843 { 3844 if (startswith (s->named.name, ".rodata.cst")) 3845 { 3846 /* Rename .rodata.cst* to .srodata.cst*. */ 3847 char *name = (char *) alloca (strlen (s->named.name) + 2); 3848 sprintf (name, ".s%s", s->named.name + 1); 3849 return get_section (name, s->named.common.flags, NULL); 3850 } 3851 3852 if (s == data_section) 3853 return sdata_section; 3854 } 3855 3856 return s; 3857 } 3858 3859 /* Make the last instruction frame-related and note that it performs 3860 the operation described by FRAME_PATTERN. */ 3861 3862 static void 3863 riscv_set_frame_expr (rtx frame_pattern) 3864 { 3865 rtx insn; 3866 3867 insn = get_last_insn (); 3868 RTX_FRAME_RELATED_P (insn) = 1; 3869 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR, 3870 frame_pattern, 3871 REG_NOTES (insn)); 3872 } 3873 3874 /* Return a frame-related rtx that stores REG at MEM. 3875 REG must be a single register. */ 3876 3877 static rtx 3878 riscv_frame_set (rtx mem, rtx reg) 3879 { 3880 rtx set = gen_rtx_SET (mem, reg); 3881 RTX_FRAME_RELATED_P (set) = 1; 3882 return set; 3883 } 3884 3885 /* Return true if the current function must save register REGNO. */ 3886 3887 static bool 3888 riscv_save_reg_p (unsigned int regno) 3889 { 3890 bool call_saved = !global_regs[regno] && !call_used_or_fixed_reg_p (regno); 3891 bool might_clobber = crtl->saves_all_registers 3892 || df_regs_ever_live_p (regno); 3893 3894 if (call_saved && might_clobber) 3895 return true; 3896 3897 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) 3898 return true; 3899 3900 if (regno == RETURN_ADDR_REGNUM && crtl->calls_eh_return) 3901 return true; 3902 3903 /* If this is an interrupt handler, then must save extra registers. */ 3904 if (cfun->machine->interrupt_handler_p) 3905 { 3906 /* zero register is always zero. */ 3907 if (regno == GP_REG_FIRST) 3908 return false; 3909 3910 /* The function will return the stack pointer to its original value. */ 3911 if (regno == STACK_POINTER_REGNUM) 3912 return false; 3913 3914 /* By convention, we assume that gp and tp are safe. */ 3915 if (regno == GP_REGNUM || regno == THREAD_POINTER_REGNUM) 3916 return false; 3917 3918 /* We must save every register used in this function. If this is not a 3919 leaf function, then we must save all temporary registers. */ 3920 if (df_regs_ever_live_p (regno) 3921 || (!crtl->is_leaf && call_used_or_fixed_reg_p (regno))) 3922 return true; 3923 } 3924 3925 return false; 3926 } 3927 3928 /* Determine whether to call GPR save/restore routines. */ 3929 static bool 3930 riscv_use_save_libcall (const struct riscv_frame_info *frame) 3931 { 3932 if (!TARGET_SAVE_RESTORE || crtl->calls_eh_return || frame_pointer_needed 3933 || cfun->machine->interrupt_handler_p) 3934 return false; 3935 3936 return frame->save_libcall_adjustment != 0; 3937 } 3938 3939 /* Determine which GPR save/restore routine to call. */ 3940 3941 static unsigned 3942 riscv_save_libcall_count (unsigned mask) 3943 { 3944 for (unsigned n = GP_REG_LAST; n > GP_REG_FIRST; n--) 3945 if (BITSET_P (mask, n)) 3946 return CALLEE_SAVED_REG_NUMBER (n) + 1; 3947 abort (); 3948 } 3949 3950 /* Populate the current function's riscv_frame_info structure. 3951 3952 RISC-V stack frames grown downward. High addresses are at the top. 3953 3954 +-------------------------------+ 3955 | | 3956 | incoming stack arguments | 3957 | | 3958 +-------------------------------+ <-- incoming stack pointer 3959 | | 3960 | callee-allocated save area | 3961 | for arguments that are | 3962 | split between registers and | 3963 | the stack | 3964 | | 3965 +-------------------------------+ <-- arg_pointer_rtx 3966 | | 3967 | callee-allocated save area | 3968 | for register varargs | 3969 | | 3970 +-------------------------------+ <-- hard_frame_pointer_rtx; 3971 | | stack_pointer_rtx + gp_sp_offset 3972 | GPR save area | + UNITS_PER_WORD 3973 | | 3974 +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset 3975 | | + UNITS_PER_HWVALUE 3976 | FPR save area | 3977 | | 3978 +-------------------------------+ <-- frame_pointer_rtx (virtual) 3979 | | 3980 | local variables | 3981 | | 3982 P +-------------------------------+ 3983 | | 3984 | outgoing stack arguments | 3985 | | 3986 +-------------------------------+ <-- stack_pointer_rtx 3987 3988 Dynamic stack allocations such as alloca insert data at point P. 3989 They decrease stack_pointer_rtx but leave frame_pointer_rtx and 3990 hard_frame_pointer_rtx unchanged. */ 3991 3992 static HOST_WIDE_INT riscv_first_stack_step (struct riscv_frame_info *frame); 3993 3994 static void 3995 riscv_compute_frame_info (void) 3996 { 3997 struct riscv_frame_info *frame; 3998 HOST_WIDE_INT offset; 3999 bool interrupt_save_prologue_temp = false; 4000 unsigned int regno, i, num_x_saved = 0, num_f_saved = 0; 4001 4002 frame = &cfun->machine->frame; 4003 4004 /* In an interrupt function, if we have a large frame, then we need to 4005 save/restore t0. We check for this before clearing the frame struct. */ 4006 if (cfun->machine->interrupt_handler_p) 4007 { 4008 HOST_WIDE_INT step1 = riscv_first_stack_step (frame); 4009 if (! SMALL_OPERAND (frame->total_size - step1)) 4010 interrupt_save_prologue_temp = true; 4011 } 4012 4013 memset (frame, 0, sizeof (*frame)); 4014 4015 if (!cfun->machine->naked_p) 4016 { 4017 /* Find out which GPRs we need to save. */ 4018 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++) 4019 if (riscv_save_reg_p (regno) 4020 || (interrupt_save_prologue_temp 4021 && (regno == RISCV_PROLOGUE_TEMP_REGNUM))) 4022 frame->mask |= 1 << (regno - GP_REG_FIRST), num_x_saved++; 4023 4024 /* If this function calls eh_return, we must also save and restore the 4025 EH data registers. */ 4026 if (crtl->calls_eh_return) 4027 for (i = 0; (regno = EH_RETURN_DATA_REGNO (i)) != INVALID_REGNUM; i++) 4028 frame->mask |= 1 << (regno - GP_REG_FIRST), num_x_saved++; 4029 4030 /* Find out which FPRs we need to save. This loop must iterate over 4031 the same space as its companion in riscv_for_each_saved_reg. */ 4032 if (TARGET_HARD_FLOAT) 4033 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++) 4034 if (riscv_save_reg_p (regno)) 4035 frame->fmask |= 1 << (regno - FP_REG_FIRST), num_f_saved++; 4036 } 4037 4038 /* At the bottom of the frame are any outgoing stack arguments. */ 4039 offset = RISCV_STACK_ALIGN (crtl->outgoing_args_size); 4040 /* Next are local stack variables. */ 4041 offset += RISCV_STACK_ALIGN (get_frame_size ()); 4042 /* The virtual frame pointer points above the local variables. */ 4043 frame->frame_pointer_offset = offset; 4044 /* Next are the callee-saved FPRs. */ 4045 if (frame->fmask) 4046 offset += RISCV_STACK_ALIGN (num_f_saved * UNITS_PER_FP_REG); 4047 frame->fp_sp_offset = offset - UNITS_PER_FP_REG; 4048 /* Next are the callee-saved GPRs. */ 4049 if (frame->mask) 4050 { 4051 unsigned x_save_size = RISCV_STACK_ALIGN (num_x_saved * UNITS_PER_WORD); 4052 unsigned num_save_restore = 1 + riscv_save_libcall_count (frame->mask); 4053 4054 /* Only use save/restore routines if they don't alter the stack size. */ 4055 if (RISCV_STACK_ALIGN (num_save_restore * UNITS_PER_WORD) == x_save_size) 4056 { 4057 /* Libcall saves/restores 3 registers at once, so we need to 4058 allocate 12 bytes for callee-saved register. */ 4059 if (TARGET_RVE) 4060 x_save_size = 3 * UNITS_PER_WORD; 4061 4062 frame->save_libcall_adjustment = x_save_size; 4063 } 4064 4065 offset += x_save_size; 4066 } 4067 frame->gp_sp_offset = offset - UNITS_PER_WORD; 4068 /* The hard frame pointer points above the callee-saved GPRs. */ 4069 frame->hard_frame_pointer_offset = offset; 4070 /* Above the hard frame pointer is the callee-allocated varags save area. */ 4071 offset += RISCV_STACK_ALIGN (cfun->machine->varargs_size); 4072 /* Next is the callee-allocated area for pretend stack arguments. */ 4073 offset += RISCV_STACK_ALIGN (crtl->args.pretend_args_size); 4074 /* Arg pointer must be below pretend args, but must be above alignment 4075 padding. */ 4076 frame->arg_pointer_offset = offset - crtl->args.pretend_args_size; 4077 frame->total_size = offset; 4078 /* Next points the incoming stack pointer and any incoming arguments. */ 4079 4080 /* Only use save/restore routines when the GPRs are atop the frame. */ 4081 if (frame->hard_frame_pointer_offset != frame->total_size) 4082 frame->save_libcall_adjustment = 0; 4083 } 4084 4085 /* Make sure that we're not trying to eliminate to the wrong hard frame 4086 pointer. */ 4087 4088 static bool 4089 riscv_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to) 4090 { 4091 return (to == HARD_FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM); 4092 } 4093 4094 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer 4095 or argument pointer. TO is either the stack pointer or hard frame 4096 pointer. */ 4097 4098 HOST_WIDE_INT 4099 riscv_initial_elimination_offset (int from, int to) 4100 { 4101 HOST_WIDE_INT src, dest; 4102 4103 riscv_compute_frame_info (); 4104 4105 if (to == HARD_FRAME_POINTER_REGNUM) 4106 dest = cfun->machine->frame.hard_frame_pointer_offset; 4107 else if (to == STACK_POINTER_REGNUM) 4108 dest = 0; /* The stack pointer is the base of all offsets, hence 0. */ 4109 else 4110 gcc_unreachable (); 4111 4112 if (from == FRAME_POINTER_REGNUM) 4113 src = cfun->machine->frame.frame_pointer_offset; 4114 else if (from == ARG_POINTER_REGNUM) 4115 src = cfun->machine->frame.arg_pointer_offset; 4116 else 4117 gcc_unreachable (); 4118 4119 return src - dest; 4120 } 4121 4122 /* Implement RETURN_ADDR_RTX. We do not support moving back to a 4123 previous frame. */ 4124 4125 rtx 4126 riscv_return_addr (int count, rtx frame ATTRIBUTE_UNUSED) 4127 { 4128 if (count != 0) 4129 return const0_rtx; 4130 4131 return get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM); 4132 } 4133 4134 /* Emit code to change the current function's return address to 4135 ADDRESS. SCRATCH is available as a scratch register, if needed. 4136 ADDRESS and SCRATCH are both word-mode GPRs. */ 4137 4138 void 4139 riscv_set_return_address (rtx address, rtx scratch) 4140 { 4141 rtx slot_address; 4142 4143 gcc_assert (BITSET_P (cfun->machine->frame.mask, RETURN_ADDR_REGNUM)); 4144 slot_address = riscv_add_offset (scratch, stack_pointer_rtx, 4145 cfun->machine->frame.gp_sp_offset); 4146 riscv_emit_move (gen_frame_mem (GET_MODE (address), slot_address), address); 4147 } 4148 4149 /* A function to save or store a register. The first argument is the 4150 register and the second is the stack slot. */ 4151 typedef void (*riscv_save_restore_fn) (rtx, rtx); 4152 4153 /* Use FN to save or restore register REGNO. MODE is the register's 4154 mode and OFFSET is the offset of its save slot from the current 4155 stack pointer. */ 4156 4157 static void 4158 riscv_save_restore_reg (machine_mode mode, int regno, 4159 HOST_WIDE_INT offset, riscv_save_restore_fn fn) 4160 { 4161 rtx mem; 4162 4163 mem = gen_frame_mem (mode, plus_constant (Pmode, stack_pointer_rtx, offset)); 4164 fn (gen_rtx_REG (mode, regno), mem); 4165 } 4166 4167 /* Call FN for each register that is saved by the current function. 4168 SP_OFFSET is the offset of the current stack pointer from the start 4169 of the frame. */ 4170 4171 static void 4172 riscv_for_each_saved_reg (HOST_WIDE_INT sp_offset, riscv_save_restore_fn fn, 4173 bool epilogue, bool maybe_eh_return) 4174 { 4175 HOST_WIDE_INT offset; 4176 4177 /* Save the link register and s-registers. */ 4178 offset = cfun->machine->frame.gp_sp_offset - sp_offset; 4179 for (unsigned int regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++) 4180 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST)) 4181 { 4182 bool handle_reg = TRUE; 4183 4184 /* If this is a normal return in a function that calls the eh_return 4185 builtin, then do not restore the eh return data registers as that 4186 would clobber the return value. But we do still need to save them 4187 in the prologue, and restore them for an exception return, so we 4188 need special handling here. */ 4189 if (epilogue && !maybe_eh_return && crtl->calls_eh_return) 4190 { 4191 unsigned int i, regnum; 4192 4193 for (i = 0; (regnum = EH_RETURN_DATA_REGNO (i)) != INVALID_REGNUM; 4194 i++) 4195 if (regno == regnum) 4196 { 4197 handle_reg = FALSE; 4198 break; 4199 } 4200 } 4201 4202 if (handle_reg) 4203 riscv_save_restore_reg (word_mode, regno, offset, fn); 4204 offset -= UNITS_PER_WORD; 4205 } 4206 4207 /* This loop must iterate over the same space as its companion in 4208 riscv_compute_frame_info. */ 4209 offset = cfun->machine->frame.fp_sp_offset - sp_offset; 4210 for (unsigned int regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++) 4211 if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST)) 4212 { 4213 machine_mode mode = TARGET_DOUBLE_FLOAT ? DFmode : SFmode; 4214 4215 riscv_save_restore_reg (mode, regno, offset, fn); 4216 offset -= GET_MODE_SIZE (mode); 4217 } 4218 } 4219 4220 /* Save register REG to MEM. Make the instruction frame-related. */ 4221 4222 static void 4223 riscv_save_reg (rtx reg, rtx mem) 4224 { 4225 riscv_emit_move (mem, reg); 4226 riscv_set_frame_expr (riscv_frame_set (mem, reg)); 4227 } 4228 4229 /* Restore register REG from MEM. */ 4230 4231 static void 4232 riscv_restore_reg (rtx reg, rtx mem) 4233 { 4234 rtx insn = riscv_emit_move (reg, mem); 4235 rtx dwarf = NULL_RTX; 4236 dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf); 4237 4238 if (epilogue_cfa_sp_offset && REGNO (reg) == HARD_FRAME_POINTER_REGNUM) 4239 { 4240 rtx cfa_adjust_rtx = gen_rtx_PLUS (Pmode, stack_pointer_rtx, 4241 GEN_INT (epilogue_cfa_sp_offset)); 4242 dwarf = alloc_reg_note (REG_CFA_DEF_CFA, cfa_adjust_rtx, dwarf); 4243 } 4244 4245 REG_NOTES (insn) = dwarf; 4246 RTX_FRAME_RELATED_P (insn) = 1; 4247 } 4248 4249 /* For stack frames that can't be allocated with a single ADDI instruction, 4250 compute the best value to initially allocate. It must at a minimum 4251 allocate enough space to spill the callee-saved registers. If TARGET_RVC, 4252 try to pick a value that will allow compression of the register saves 4253 without adding extra instructions. */ 4254 4255 static HOST_WIDE_INT 4256 riscv_first_stack_step (struct riscv_frame_info *frame) 4257 { 4258 if (SMALL_OPERAND (frame->total_size)) 4259 return frame->total_size; 4260 4261 HOST_WIDE_INT min_first_step = 4262 RISCV_STACK_ALIGN (frame->total_size - frame->fp_sp_offset); 4263 HOST_WIDE_INT max_first_step = IMM_REACH / 2 - PREFERRED_STACK_BOUNDARY / 8; 4264 HOST_WIDE_INT min_second_step = frame->total_size - max_first_step; 4265 gcc_assert (min_first_step <= max_first_step); 4266 4267 /* As an optimization, use the least-significant bits of the total frame 4268 size, so that the second adjustment step is just LUI + ADD. */ 4269 if (!SMALL_OPERAND (min_second_step) 4270 && frame->total_size % IMM_REACH < IMM_REACH / 2 4271 && frame->total_size % IMM_REACH >= min_first_step) 4272 return frame->total_size % IMM_REACH; 4273 4274 if (TARGET_RVC) 4275 { 4276 /* If we need two subtracts, and one is small enough to allow compressed 4277 loads and stores, then put that one first. */ 4278 if (IN_RANGE (min_second_step, 0, 4279 (TARGET_64BIT ? SDSP_REACH : SWSP_REACH))) 4280 return MAX (min_second_step, min_first_step); 4281 4282 /* If we need LUI + ADDI + ADD for the second adjustment step, then start 4283 with the minimum first step, so that we can get compressed loads and 4284 stores. */ 4285 else if (!SMALL_OPERAND (min_second_step)) 4286 return min_first_step; 4287 } 4288 4289 return max_first_step; 4290 } 4291 4292 static rtx 4293 riscv_adjust_libcall_cfi_prologue () 4294 { 4295 rtx dwarf = NULL_RTX; 4296 rtx adjust_sp_rtx, reg, mem, insn; 4297 int saved_size = cfun->machine->frame.save_libcall_adjustment; 4298 int offset; 4299 4300 for (int regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++) 4301 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST)) 4302 { 4303 /* The save order is ra, s0, s1, s2 to s11. */ 4304 if (regno == RETURN_ADDR_REGNUM) 4305 offset = saved_size - UNITS_PER_WORD; 4306 else if (regno == S0_REGNUM) 4307 offset = saved_size - UNITS_PER_WORD * 2; 4308 else if (regno == S1_REGNUM) 4309 offset = saved_size - UNITS_PER_WORD * 3; 4310 else 4311 offset = saved_size - ((regno - S2_REGNUM + 4) * UNITS_PER_WORD); 4312 4313 reg = gen_rtx_REG (SImode, regno); 4314 mem = gen_frame_mem (SImode, plus_constant (Pmode, 4315 stack_pointer_rtx, 4316 offset)); 4317 4318 insn = gen_rtx_SET (mem, reg); 4319 dwarf = alloc_reg_note (REG_CFA_OFFSET, insn, dwarf); 4320 } 4321 4322 /* Debug info for adjust sp. */ 4323 adjust_sp_rtx = gen_add3_insn (stack_pointer_rtx, 4324 stack_pointer_rtx, GEN_INT (-saved_size)); 4325 dwarf = alloc_reg_note (REG_CFA_ADJUST_CFA, adjust_sp_rtx, 4326 dwarf); 4327 return dwarf; 4328 } 4329 4330 static void 4331 riscv_emit_stack_tie (void) 4332 { 4333 if (Pmode == SImode) 4334 emit_insn (gen_stack_tiesi (stack_pointer_rtx, hard_frame_pointer_rtx)); 4335 else 4336 emit_insn (gen_stack_tiedi (stack_pointer_rtx, hard_frame_pointer_rtx)); 4337 } 4338 4339 /* Expand the "prologue" pattern. */ 4340 4341 void 4342 riscv_expand_prologue (void) 4343 { 4344 struct riscv_frame_info *frame = &cfun->machine->frame; 4345 HOST_WIDE_INT size = frame->total_size; 4346 unsigned mask = frame->mask; 4347 rtx insn; 4348 4349 if (flag_stack_usage_info) 4350 current_function_static_stack_size = size; 4351 4352 if (cfun->machine->naked_p) 4353 return; 4354 4355 /* When optimizing for size, call a subroutine to save the registers. */ 4356 if (riscv_use_save_libcall (frame)) 4357 { 4358 rtx dwarf = NULL_RTX; 4359 dwarf = riscv_adjust_libcall_cfi_prologue (); 4360 4361 size -= frame->save_libcall_adjustment; 4362 insn = emit_insn (riscv_gen_gpr_save_insn (frame)); 4363 frame->mask = 0; /* Temporarily fib that we need not save GPRs. */ 4364 4365 RTX_FRAME_RELATED_P (insn) = 1; 4366 REG_NOTES (insn) = dwarf; 4367 } 4368 4369 /* Save the registers. */ 4370 if ((frame->mask | frame->fmask) != 0) 4371 { 4372 HOST_WIDE_INT step1 = MIN (size, riscv_first_stack_step (frame)); 4373 4374 insn = gen_add3_insn (stack_pointer_rtx, 4375 stack_pointer_rtx, 4376 GEN_INT (-step1)); 4377 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1; 4378 size -= step1; 4379 riscv_for_each_saved_reg (size, riscv_save_reg, false, false); 4380 } 4381 4382 frame->mask = mask; /* Undo the above fib. */ 4383 4384 /* Set up the frame pointer, if we're using one. */ 4385 if (frame_pointer_needed) 4386 { 4387 insn = gen_add3_insn (hard_frame_pointer_rtx, stack_pointer_rtx, 4388 GEN_INT (frame->hard_frame_pointer_offset - size)); 4389 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1; 4390 4391 riscv_emit_stack_tie (); 4392 } 4393 4394 /* Allocate the rest of the frame. */ 4395 if (size > 0) 4396 { 4397 if (SMALL_OPERAND (-size)) 4398 { 4399 insn = gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx, 4400 GEN_INT (-size)); 4401 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1; 4402 } 4403 else 4404 { 4405 riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode), GEN_INT (-size)); 4406 emit_insn (gen_add3_insn (stack_pointer_rtx, 4407 stack_pointer_rtx, 4408 RISCV_PROLOGUE_TEMP (Pmode))); 4409 4410 /* Describe the effect of the previous instructions. */ 4411 insn = plus_constant (Pmode, stack_pointer_rtx, -size); 4412 insn = gen_rtx_SET (stack_pointer_rtx, insn); 4413 riscv_set_frame_expr (insn); 4414 } 4415 } 4416 } 4417 4418 static rtx 4419 riscv_adjust_libcall_cfi_epilogue () 4420 { 4421 rtx dwarf = NULL_RTX; 4422 rtx adjust_sp_rtx, reg; 4423 int saved_size = cfun->machine->frame.save_libcall_adjustment; 4424 4425 /* Debug info for adjust sp. */ 4426 adjust_sp_rtx = gen_add3_insn (stack_pointer_rtx, 4427 stack_pointer_rtx, GEN_INT (saved_size)); 4428 dwarf = alloc_reg_note (REG_CFA_ADJUST_CFA, adjust_sp_rtx, 4429 dwarf); 4430 4431 for (int regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++) 4432 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST)) 4433 { 4434 reg = gen_rtx_REG (SImode, regno); 4435 dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf); 4436 } 4437 4438 return dwarf; 4439 } 4440 4441 /* Expand an "epilogue", "sibcall_epilogue", or "eh_return_internal" pattern; 4442 style says which. */ 4443 4444 void 4445 riscv_expand_epilogue (int style) 4446 { 4447 /* Split the frame into two. STEP1 is the amount of stack we should 4448 deallocate before restoring the registers. STEP2 is the amount we 4449 should deallocate afterwards. 4450 4451 Start off by assuming that no registers need to be restored. */ 4452 struct riscv_frame_info *frame = &cfun->machine->frame; 4453 unsigned mask = frame->mask; 4454 HOST_WIDE_INT step1 = frame->total_size; 4455 HOST_WIDE_INT step2 = 0; 4456 bool use_restore_libcall = ((style == NORMAL_RETURN) 4457 && riscv_use_save_libcall (frame)); 4458 rtx ra = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM); 4459 rtx insn; 4460 4461 /* We need to add memory barrier to prevent read from deallocated stack. */ 4462 bool need_barrier_p = (get_frame_size () 4463 + cfun->machine->frame.arg_pointer_offset) != 0; 4464 4465 if (cfun->machine->naked_p) 4466 { 4467 gcc_assert (style == NORMAL_RETURN); 4468 4469 emit_jump_insn (gen_return ()); 4470 4471 return; 4472 } 4473 4474 if ((style == NORMAL_RETURN) && riscv_can_use_return_insn ()) 4475 { 4476 emit_jump_insn (gen_return ()); 4477 return; 4478 } 4479 4480 /* Reset the epilogue cfa info before starting to emit the epilogue. */ 4481 epilogue_cfa_sp_offset = 0; 4482 4483 /* Move past any dynamic stack allocations. */ 4484 if (cfun->calls_alloca) 4485 { 4486 /* Emit a barrier to prevent loads from a deallocated stack. */ 4487 riscv_emit_stack_tie (); 4488 need_barrier_p = false; 4489 4490 rtx adjust = GEN_INT (-frame->hard_frame_pointer_offset); 4491 if (!SMALL_OPERAND (INTVAL (adjust))) 4492 { 4493 riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode), adjust); 4494 adjust = RISCV_PROLOGUE_TEMP (Pmode); 4495 } 4496 4497 insn = emit_insn ( 4498 gen_add3_insn (stack_pointer_rtx, hard_frame_pointer_rtx, 4499 adjust)); 4500 4501 rtx dwarf = NULL_RTX; 4502 rtx cfa_adjust_value = gen_rtx_PLUS ( 4503 Pmode, hard_frame_pointer_rtx, 4504 GEN_INT (-frame->hard_frame_pointer_offset)); 4505 rtx cfa_adjust_rtx = gen_rtx_SET (stack_pointer_rtx, cfa_adjust_value); 4506 dwarf = alloc_reg_note (REG_CFA_ADJUST_CFA, cfa_adjust_rtx, dwarf); 4507 RTX_FRAME_RELATED_P (insn) = 1; 4508 4509 REG_NOTES (insn) = dwarf; 4510 } 4511 4512 /* If we need to restore registers, deallocate as much stack as 4513 possible in the second step without going out of range. */ 4514 if ((frame->mask | frame->fmask) != 0) 4515 { 4516 step2 = riscv_first_stack_step (frame); 4517 step1 -= step2; 4518 } 4519 4520 /* Set TARGET to BASE + STEP1. */ 4521 if (step1 > 0) 4522 { 4523 /* Emit a barrier to prevent loads from a deallocated stack. */ 4524 riscv_emit_stack_tie (); 4525 need_barrier_p = false; 4526 4527 /* Get an rtx for STEP1 that we can add to BASE. */ 4528 rtx adjust = GEN_INT (step1); 4529 if (!SMALL_OPERAND (step1)) 4530 { 4531 riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode), adjust); 4532 adjust = RISCV_PROLOGUE_TEMP (Pmode); 4533 } 4534 4535 insn = emit_insn ( 4536 gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx, adjust)); 4537 4538 rtx dwarf = NULL_RTX; 4539 rtx cfa_adjust_rtx = gen_rtx_PLUS (Pmode, stack_pointer_rtx, 4540 GEN_INT (step2)); 4541 4542 dwarf = alloc_reg_note (REG_CFA_DEF_CFA, cfa_adjust_rtx, dwarf); 4543 RTX_FRAME_RELATED_P (insn) = 1; 4544 4545 REG_NOTES (insn) = dwarf; 4546 } 4547 else if (frame_pointer_needed) 4548 { 4549 /* Tell riscv_restore_reg to emit dwarf to redefine CFA when restoring 4550 old value of FP. */ 4551 epilogue_cfa_sp_offset = step2; 4552 } 4553 4554 if (use_restore_libcall) 4555 frame->mask = 0; /* Temporarily fib that we need not save GPRs. */ 4556 4557 /* Restore the registers. */ 4558 riscv_for_each_saved_reg (frame->total_size - step2, riscv_restore_reg, 4559 true, style == EXCEPTION_RETURN); 4560 4561 if (use_restore_libcall) 4562 { 4563 frame->mask = mask; /* Undo the above fib. */ 4564 gcc_assert (step2 >= frame->save_libcall_adjustment); 4565 step2 -= frame->save_libcall_adjustment; 4566 } 4567 4568 if (need_barrier_p) 4569 riscv_emit_stack_tie (); 4570 4571 /* Deallocate the final bit of the frame. */ 4572 if (step2 > 0) 4573 { 4574 insn = emit_insn (gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx, 4575 GEN_INT (step2))); 4576 4577 rtx dwarf = NULL_RTX; 4578 rtx cfa_adjust_rtx = gen_rtx_PLUS (Pmode, stack_pointer_rtx, 4579 const0_rtx); 4580 dwarf = alloc_reg_note (REG_CFA_DEF_CFA, cfa_adjust_rtx, dwarf); 4581 RTX_FRAME_RELATED_P (insn) = 1; 4582 4583 REG_NOTES (insn) = dwarf; 4584 } 4585 4586 if (use_restore_libcall) 4587 { 4588 rtx dwarf = riscv_adjust_libcall_cfi_epilogue (); 4589 insn = emit_insn (gen_gpr_restore (GEN_INT (riscv_save_libcall_count (mask)))); 4590 RTX_FRAME_RELATED_P (insn) = 1; 4591 REG_NOTES (insn) = dwarf; 4592 4593 emit_jump_insn (gen_gpr_restore_return (ra)); 4594 return; 4595 } 4596 4597 /* Add in the __builtin_eh_return stack adjustment. */ 4598 if ((style == EXCEPTION_RETURN) && crtl->calls_eh_return) 4599 emit_insn (gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx, 4600 EH_RETURN_STACKADJ_RTX)); 4601 4602 /* Return from interrupt. */ 4603 if (cfun->machine->interrupt_handler_p) 4604 { 4605 enum riscv_privilege_levels mode = cfun->machine->interrupt_mode; 4606 4607 gcc_assert (mode != UNKNOWN_MODE); 4608 4609 if (mode == MACHINE_MODE) 4610 emit_jump_insn (gen_riscv_mret ()); 4611 else if (mode == SUPERVISOR_MODE) 4612 emit_jump_insn (gen_riscv_sret ()); 4613 else 4614 emit_jump_insn (gen_riscv_uret ()); 4615 } 4616 else if (style != SIBCALL_RETURN) 4617 emit_jump_insn (gen_simple_return_internal (ra)); 4618 } 4619 4620 /* Implement EPILOGUE_USES. */ 4621 4622 bool 4623 riscv_epilogue_uses (unsigned int regno) 4624 { 4625 if (regno == RETURN_ADDR_REGNUM) 4626 return true; 4627 4628 if (epilogue_completed && cfun->machine->interrupt_handler_p) 4629 { 4630 /* An interrupt function restores temp regs, so we must indicate that 4631 they are live at function end. */ 4632 if (df_regs_ever_live_p (regno) 4633 || (!crtl->is_leaf && call_used_or_fixed_reg_p (regno))) 4634 return true; 4635 } 4636 4637 return false; 4638 } 4639 4640 /* Return nonzero if this function is known to have a null epilogue. 4641 This allows the optimizer to omit jumps to jumps if no stack 4642 was created. */ 4643 4644 bool 4645 riscv_can_use_return_insn (void) 4646 { 4647 return (reload_completed && cfun->machine->frame.total_size == 0 4648 && ! cfun->machine->interrupt_handler_p); 4649 } 4650 4651 /* Given that there exists at least one variable that is set (produced) 4652 by OUT_INSN and read (consumed) by IN_INSN, return true iff 4653 IN_INSN represents one or more memory store operations and none of 4654 the variables set by OUT_INSN is used by IN_INSN as the address of a 4655 store operation. If either IN_INSN or OUT_INSN does not represent 4656 a "single" RTL SET expression (as loosely defined by the 4657 implementation of the single_set function) or a PARALLEL with only 4658 SETs, CLOBBERs, and USEs inside, this function returns false. 4659 4660 Borrowed from rs6000, riscv_store_data_bypass_p checks for certain 4661 conditions that result in assertion failures in the generic 4662 store_data_bypass_p function and returns FALSE in such cases. 4663 4664 This is required to make -msave-restore work with the sifive-7 4665 pipeline description. */ 4666 4667 bool 4668 riscv_store_data_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn) 4669 { 4670 rtx out_set, in_set; 4671 rtx out_pat, in_pat; 4672 rtx out_exp, in_exp; 4673 int i, j; 4674 4675 in_set = single_set (in_insn); 4676 if (in_set) 4677 { 4678 if (MEM_P (SET_DEST (in_set))) 4679 { 4680 out_set = single_set (out_insn); 4681 if (!out_set) 4682 { 4683 out_pat = PATTERN (out_insn); 4684 if (GET_CODE (out_pat) == PARALLEL) 4685 { 4686 for (i = 0; i < XVECLEN (out_pat, 0); i++) 4687 { 4688 out_exp = XVECEXP (out_pat, 0, i); 4689 if ((GET_CODE (out_exp) == CLOBBER) 4690 || (GET_CODE (out_exp) == USE)) 4691 continue; 4692 else if (GET_CODE (out_exp) != SET) 4693 return false; 4694 } 4695 } 4696 } 4697 } 4698 } 4699 else 4700 { 4701 in_pat = PATTERN (in_insn); 4702 if (GET_CODE (in_pat) != PARALLEL) 4703 return false; 4704 4705 for (i = 0; i < XVECLEN (in_pat, 0); i++) 4706 { 4707 in_exp = XVECEXP (in_pat, 0, i); 4708 if ((GET_CODE (in_exp) == CLOBBER) || (GET_CODE (in_exp) == USE)) 4709 continue; 4710 else if (GET_CODE (in_exp) != SET) 4711 return false; 4712 4713 if (MEM_P (SET_DEST (in_exp))) 4714 { 4715 out_set = single_set (out_insn); 4716 if (!out_set) 4717 { 4718 out_pat = PATTERN (out_insn); 4719 if (GET_CODE (out_pat) != PARALLEL) 4720 return false; 4721 for (j = 0; j < XVECLEN (out_pat, 0); j++) 4722 { 4723 out_exp = XVECEXP (out_pat, 0, j); 4724 if ((GET_CODE (out_exp) == CLOBBER) 4725 || (GET_CODE (out_exp) == USE)) 4726 continue; 4727 else if (GET_CODE (out_exp) != SET) 4728 return false; 4729 } 4730 } 4731 } 4732 } 4733 } 4734 4735 return store_data_bypass_p (out_insn, in_insn); 4736 } 4737 4738 /* Implement TARGET_SECONDARY_MEMORY_NEEDED. 4739 4740 When floating-point registers are wider than integer ones, moves between 4741 them must go through memory. */ 4742 4743 static bool 4744 riscv_secondary_memory_needed (machine_mode mode, reg_class_t class1, 4745 reg_class_t class2) 4746 { 4747 return (GET_MODE_SIZE (mode) > UNITS_PER_WORD 4748 && (class1 == FP_REGS) != (class2 == FP_REGS)); 4749 } 4750 4751 /* Implement TARGET_REGISTER_MOVE_COST. */ 4752 4753 static int 4754 riscv_register_move_cost (machine_mode mode, 4755 reg_class_t from, reg_class_t to) 4756 { 4757 if ((from == FP_REGS && to == GR_REGS) || 4758 (from == GR_REGS && to == FP_REGS)) 4759 return tune_param->fmv_cost; 4760 4761 return riscv_secondary_memory_needed (mode, from, to) ? 8 : 2; 4762 } 4763 4764 /* Implement TARGET_HARD_REGNO_NREGS. */ 4765 4766 static unsigned int 4767 riscv_hard_regno_nregs (unsigned int regno, machine_mode mode) 4768 { 4769 if (FP_REG_P (regno)) 4770 return (GET_MODE_SIZE (mode) + UNITS_PER_FP_REG - 1) / UNITS_PER_FP_REG; 4771 4772 /* All other registers are word-sized. */ 4773 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; 4774 } 4775 4776 /* Implement TARGET_HARD_REGNO_MODE_OK. */ 4777 4778 static bool 4779 riscv_hard_regno_mode_ok (unsigned int regno, machine_mode mode) 4780 { 4781 unsigned int nregs = riscv_hard_regno_nregs (regno, mode); 4782 4783 if (GP_REG_P (regno)) 4784 { 4785 if (!GP_REG_P (regno + nregs - 1)) 4786 return false; 4787 } 4788 else if (FP_REG_P (regno)) 4789 { 4790 if (!FP_REG_P (regno + nregs - 1)) 4791 return false; 4792 4793 if (GET_MODE_CLASS (mode) != MODE_FLOAT 4794 && GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT) 4795 return false; 4796 4797 /* Only use callee-saved registers if a potential callee is guaranteed 4798 to spill the requisite width. */ 4799 if (GET_MODE_UNIT_SIZE (mode) > UNITS_PER_FP_REG 4800 || (!call_used_or_fixed_reg_p (regno) 4801 && GET_MODE_UNIT_SIZE (mode) > UNITS_PER_FP_ARG)) 4802 return false; 4803 } 4804 else 4805 return false; 4806 4807 /* Require same callee-savedness for all registers. */ 4808 for (unsigned i = 1; i < nregs; i++) 4809 if (call_used_or_fixed_reg_p (regno) 4810 != call_used_or_fixed_reg_p (regno + i)) 4811 return false; 4812 4813 return true; 4814 } 4815 4816 /* Implement TARGET_MODES_TIEABLE_P. 4817 4818 Don't allow floating-point modes to be tied, since type punning of 4819 single-precision and double-precision is implementation defined. */ 4820 4821 static bool 4822 riscv_modes_tieable_p (machine_mode mode1, machine_mode mode2) 4823 { 4824 return (mode1 == mode2 4825 || !(GET_MODE_CLASS (mode1) == MODE_FLOAT 4826 && GET_MODE_CLASS (mode2) == MODE_FLOAT)); 4827 } 4828 4829 /* Implement CLASS_MAX_NREGS. */ 4830 4831 static unsigned char 4832 riscv_class_max_nregs (reg_class_t rclass, machine_mode mode) 4833 { 4834 if (reg_class_subset_p (rclass, FP_REGS)) 4835 return riscv_hard_regno_nregs (FP_REG_FIRST, mode); 4836 4837 if (reg_class_subset_p (rclass, GR_REGS)) 4838 return riscv_hard_regno_nregs (GP_REG_FIRST, mode); 4839 4840 return 0; 4841 } 4842 4843 /* Implement TARGET_MEMORY_MOVE_COST. */ 4844 4845 static int 4846 riscv_memory_move_cost (machine_mode mode, reg_class_t rclass, bool in) 4847 { 4848 return (tune_param->memory_cost 4849 + memory_move_secondary_cost (mode, rclass, in)); 4850 } 4851 4852 /* Return the number of instructions that can be issued per cycle. */ 4853 4854 static int 4855 riscv_issue_rate (void) 4856 { 4857 return tune_param->issue_rate; 4858 } 4859 4860 /* Auxiliary function to emit RISC-V ELF attribute. */ 4861 static void 4862 riscv_emit_attribute () 4863 { 4864 fprintf (asm_out_file, "\t.attribute arch, \"%s\"\n", 4865 riscv_arch_str ().c_str ()); 4866 4867 fprintf (asm_out_file, "\t.attribute unaligned_access, %d\n", 4868 TARGET_STRICT_ALIGN ? 0 : 1); 4869 4870 fprintf (asm_out_file, "\t.attribute stack_align, %d\n", 4871 riscv_stack_boundary / 8); 4872 } 4873 4874 /* Implement TARGET_ASM_FILE_START. */ 4875 4876 static void 4877 riscv_file_start (void) 4878 { 4879 default_file_start (); 4880 4881 /* Instruct GAS to generate position-[in]dependent code. */ 4882 fprintf (asm_out_file, "\t.option %spic\n", (flag_pic ? "" : "no")); 4883 4884 /* If the user specifies "-mno-relax" on the command line then disable linker 4885 relaxation in the assembler. */ 4886 if (! riscv_mrelax) 4887 fprintf (asm_out_file, "\t.option norelax\n"); 4888 4889 if (riscv_emit_attribute_p) 4890 riscv_emit_attribute (); 4891 } 4892 4893 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text 4894 in order to avoid duplicating too much logic from elsewhere. */ 4895 4896 static void 4897 riscv_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, 4898 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset, 4899 tree function) 4900 { 4901 const char *fnname = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (thunk_fndecl)); 4902 rtx this_rtx, temp1, temp2, fnaddr; 4903 rtx_insn *insn; 4904 4905 /* Pretend to be a post-reload pass while generating rtl. */ 4906 reload_completed = 1; 4907 4908 /* Mark the end of the (empty) prologue. */ 4909 emit_note (NOTE_INSN_PROLOGUE_END); 4910 4911 /* Determine if we can use a sibcall to call FUNCTION directly. */ 4912 fnaddr = gen_rtx_MEM (FUNCTION_MODE, XEXP (DECL_RTL (function), 0)); 4913 4914 /* We need two temporary registers in some cases. */ 4915 temp1 = gen_rtx_REG (Pmode, RISCV_PROLOGUE_TEMP_REGNUM); 4916 temp2 = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM); 4917 4918 /* Find out which register contains the "this" pointer. */ 4919 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)) 4920 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1); 4921 else 4922 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST); 4923 4924 /* Add DELTA to THIS_RTX. */ 4925 if (delta != 0) 4926 { 4927 rtx offset = GEN_INT (delta); 4928 if (!SMALL_OPERAND (delta)) 4929 { 4930 riscv_emit_move (temp1, offset); 4931 offset = temp1; 4932 } 4933 emit_insn (gen_add3_insn (this_rtx, this_rtx, offset)); 4934 } 4935 4936 /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */ 4937 if (vcall_offset != 0) 4938 { 4939 rtx addr; 4940 4941 /* Set TEMP1 to *THIS_RTX. */ 4942 riscv_emit_move (temp1, gen_rtx_MEM (Pmode, this_rtx)); 4943 4944 /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */ 4945 addr = riscv_add_offset (temp2, temp1, vcall_offset); 4946 4947 /* Load the offset and add it to THIS_RTX. */ 4948 riscv_emit_move (temp1, gen_rtx_MEM (Pmode, addr)); 4949 emit_insn (gen_add3_insn (this_rtx, this_rtx, temp1)); 4950 } 4951 4952 /* Jump to the target function. */ 4953 insn = emit_call_insn (gen_sibcall (fnaddr, const0_rtx, NULL, const0_rtx)); 4954 SIBLING_CALL_P (insn) = 1; 4955 4956 /* Run just enough of rest_of_compilation. This sequence was 4957 "borrowed" from alpha.cc. */ 4958 insn = get_insns (); 4959 split_all_insns_noflow (); 4960 shorten_branches (insn); 4961 assemble_start_function (thunk_fndecl, fnname); 4962 final_start_function (insn, file, 1); 4963 final (insn, file, 1); 4964 final_end_function (); 4965 assemble_end_function (thunk_fndecl, fnname); 4966 4967 /* Clean up the vars set above. Note that final_end_function resets 4968 the global pointer for us. */ 4969 reload_completed = 0; 4970 } 4971 4972 /* Allocate a chunk of memory for per-function machine-dependent data. */ 4973 4974 static struct machine_function * 4975 riscv_init_machine_status (void) 4976 { 4977 return ggc_cleared_alloc<machine_function> (); 4978 } 4979 4980 /* Implement TARGET_OPTION_OVERRIDE. */ 4981 4982 static void 4983 riscv_option_override (void) 4984 { 4985 const struct riscv_tune_info *cpu; 4986 4987 #ifdef SUBTARGET_OVERRIDE_OPTIONS 4988 SUBTARGET_OVERRIDE_OPTIONS; 4989 #endif 4990 4991 flag_pcc_struct_return = 0; 4992 4993 if (flag_pic) 4994 g_switch_value = 0; 4995 4996 /* The presence of the M extension implies that division instructions 4997 are present, so include them unless explicitly disabled. */ 4998 if (TARGET_MUL && (target_flags_explicit & MASK_DIV) == 0) 4999 target_flags |= MASK_DIV; 5000 else if (!TARGET_MUL && TARGET_DIV) 5001 error ("%<-mdiv%> requires %<-march%> to subsume the %<M%> extension"); 5002 5003 /* Likewise floating-point division and square root. */ 5004 if (TARGET_HARD_FLOAT && (target_flags_explicit & MASK_FDIV) == 0) 5005 target_flags |= MASK_FDIV; 5006 5007 /* Handle -mtune, use -mcpu if -mtune is not given, and use default -mtune 5008 if -mtune and -mcpu both not given. */ 5009 cpu = riscv_parse_tune (riscv_tune_string ? riscv_tune_string : 5010 (riscv_cpu_string ? riscv_cpu_string : 5011 RISCV_TUNE_STRING_DEFAULT)); 5012 riscv_microarchitecture = cpu->microarchitecture; 5013 tune_param = optimize_size ? &optimize_size_tune_info : cpu->tune_param; 5014 5015 /* Use -mtune's setting for slow_unaligned_access, even when optimizing 5016 for size. For architectures that trap and emulate unaligned accesses, 5017 the performance cost is too great, even for -Os. Similarly, if 5018 -m[no-]strict-align is left unspecified, heed -mtune's advice. */ 5019 riscv_slow_unaligned_access_p = (cpu->tune_param->slow_unaligned_access 5020 || TARGET_STRICT_ALIGN); 5021 if ((target_flags_explicit & MASK_STRICT_ALIGN) == 0 5022 && cpu->tune_param->slow_unaligned_access) 5023 target_flags |= MASK_STRICT_ALIGN; 5024 5025 /* If the user hasn't specified a branch cost, use the processor's 5026 default. */ 5027 if (riscv_branch_cost == 0) 5028 riscv_branch_cost = tune_param->branch_cost; 5029 5030 /* Function to allocate machine-dependent function status. */ 5031 init_machine_status = &riscv_init_machine_status; 5032 5033 if (flag_pic) 5034 riscv_cmodel = CM_PIC; 5035 5036 /* We get better code with explicit relocs for CM_MEDLOW, but 5037 worse code for the others (for now). Pick the best default. */ 5038 if ((target_flags_explicit & MASK_EXPLICIT_RELOCS) == 0) 5039 if (riscv_cmodel == CM_MEDLOW) 5040 target_flags |= MASK_EXPLICIT_RELOCS; 5041 5042 /* Require that the ISA supports the requested floating-point ABI. */ 5043 if (UNITS_PER_FP_ARG > (TARGET_HARD_FLOAT ? UNITS_PER_FP_REG : 0)) 5044 error ("requested ABI requires %<-march%> to subsume the %qc extension", 5045 UNITS_PER_FP_ARG > 8 ? 'Q' : (UNITS_PER_FP_ARG > 4 ? 'D' : 'F')); 5046 5047 if (TARGET_RVE && riscv_abi != ABI_ILP32E) 5048 error ("rv32e requires ilp32e ABI"); 5049 5050 /* We do not yet support ILP32 on RV64. */ 5051 if (BITS_PER_WORD != POINTER_SIZE) 5052 error ("ABI requires %<-march=rv%d%>", POINTER_SIZE); 5053 5054 /* Validate -mpreferred-stack-boundary= value. */ 5055 riscv_stack_boundary = ABI_STACK_BOUNDARY; 5056 if (riscv_preferred_stack_boundary_arg) 5057 { 5058 int min = ctz_hwi (STACK_BOUNDARY / 8); 5059 int max = 8; 5060 5061 if (!IN_RANGE (riscv_preferred_stack_boundary_arg, min, max)) 5062 error ("%<-mpreferred-stack-boundary=%d%> must be between %d and %d", 5063 riscv_preferred_stack_boundary_arg, min, max); 5064 5065 riscv_stack_boundary = 8 << riscv_preferred_stack_boundary_arg; 5066 } 5067 5068 if (riscv_emit_attribute_p < 0) 5069 #ifdef HAVE_AS_RISCV_ATTRIBUTE 5070 riscv_emit_attribute_p = TARGET_RISCV_ATTRIBUTE; 5071 #else 5072 riscv_emit_attribute_p = 0; 5073 5074 if (riscv_emit_attribute_p) 5075 error ("%<-mriscv-attribute%> RISC-V ELF attribute requires GNU as 2.32" 5076 " [%<-mriscv-attribute%>]"); 5077 #endif 5078 5079 if (riscv_stack_protector_guard == SSP_GLOBAL 5080 && OPTION_SET_P (riscv_stack_protector_guard_offset_str)) 5081 { 5082 error ("incompatible options %<-mstack-protector-guard=global%> and " 5083 "%<-mstack-protector-guard-offset=%s%>", 5084 riscv_stack_protector_guard_offset_str); 5085 } 5086 5087 if (riscv_stack_protector_guard == SSP_TLS 5088 && !(OPTION_SET_P (riscv_stack_protector_guard_offset_str) 5089 && OPTION_SET_P (riscv_stack_protector_guard_reg_str))) 5090 { 5091 error ("both %<-mstack-protector-guard-offset%> and " 5092 "%<-mstack-protector-guard-reg%> must be used " 5093 "with %<-mstack-protector-guard=sysreg%>"); 5094 } 5095 5096 if (OPTION_SET_P (riscv_stack_protector_guard_reg_str)) 5097 { 5098 const char *str = riscv_stack_protector_guard_reg_str; 5099 int reg = decode_reg_name (str); 5100 5101 if (!IN_RANGE (reg, GP_REG_FIRST + 1, GP_REG_LAST)) 5102 error ("%qs is not a valid base register in %qs", str, 5103 "-mstack-protector-guard-reg="); 5104 5105 riscv_stack_protector_guard_reg = reg; 5106 } 5107 5108 if (OPTION_SET_P (riscv_stack_protector_guard_offset_str)) 5109 { 5110 char *end; 5111 const char *str = riscv_stack_protector_guard_offset_str; 5112 errno = 0; 5113 long offs = strtol (riscv_stack_protector_guard_offset_str, &end, 0); 5114 5115 if (!*str || *end || errno) 5116 error ("%qs is not a valid number in %qs", str, 5117 "-mstack-protector-guard-offset="); 5118 5119 if (!SMALL_OPERAND (offs)) 5120 error ("%qs is not a valid offset in %qs", str, 5121 "-mstack-protector-guard-offset="); 5122 5123 riscv_stack_protector_guard_offset = offs; 5124 } 5125 5126 } 5127 5128 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */ 5129 5130 static void 5131 riscv_conditional_register_usage (void) 5132 { 5133 /* We have only x0~x15 on RV32E. */ 5134 if (TARGET_RVE) 5135 { 5136 for (int r = 16; r <= 31; r++) 5137 fixed_regs[r] = 1; 5138 } 5139 5140 if (riscv_abi == ABI_ILP32E) 5141 { 5142 for (int r = 16; r <= 31; r++) 5143 call_used_regs[r] = 1; 5144 } 5145 5146 if (!TARGET_HARD_FLOAT) 5147 { 5148 for (int regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++) 5149 fixed_regs[regno] = call_used_regs[regno] = 1; 5150 } 5151 5152 /* In the soft-float ABI, there are no callee-saved FP registers. */ 5153 if (UNITS_PER_FP_ARG == 0) 5154 { 5155 for (int regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++) 5156 call_used_regs[regno] = 1; 5157 } 5158 } 5159 5160 /* Return a register priority for hard reg REGNO. */ 5161 5162 static int 5163 riscv_register_priority (int regno) 5164 { 5165 /* Favor compressed registers to improve the odds of RVC instruction 5166 selection. */ 5167 if (riscv_compressed_reg_p (regno)) 5168 return 1; 5169 5170 return 0; 5171 } 5172 5173 /* Implement TARGET_TRAMPOLINE_INIT. */ 5174 5175 static void 5176 riscv_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) 5177 { 5178 rtx addr, end_addr, mem; 5179 uint32_t trampoline[4]; 5180 unsigned int i; 5181 HOST_WIDE_INT static_chain_offset, target_function_offset; 5182 5183 /* Work out the offsets of the pointers from the start of the 5184 trampoline code. */ 5185 gcc_assert (ARRAY_SIZE (trampoline) * 4 == TRAMPOLINE_CODE_SIZE); 5186 5187 /* Get pointers to the beginning and end of the code block. */ 5188 addr = force_reg (Pmode, XEXP (m_tramp, 0)); 5189 end_addr = riscv_force_binary (Pmode, PLUS, addr, 5190 GEN_INT (TRAMPOLINE_CODE_SIZE)); 5191 5192 5193 if (Pmode == SImode) 5194 { 5195 chain_value = force_reg (Pmode, chain_value); 5196 5197 rtx target_function = force_reg (Pmode, XEXP (DECL_RTL (fndecl), 0)); 5198 /* lui t2, hi(chain) 5199 lui t0, hi(func) 5200 addi t2, t2, lo(chain) 5201 jr t0, lo(func) 5202 */ 5203 unsigned HOST_WIDE_INT lui_hi_chain_code, lui_hi_func_code; 5204 unsigned HOST_WIDE_INT lo_chain_code, lo_func_code; 5205 5206 rtx uimm_mask = force_reg (SImode, gen_int_mode (-IMM_REACH, SImode)); 5207 5208 /* 0xfff. */ 5209 rtx imm12_mask = gen_reg_rtx (SImode); 5210 emit_insn (gen_one_cmplsi2 (imm12_mask, uimm_mask)); 5211 5212 rtx fixup_value = force_reg (SImode, gen_int_mode (IMM_REACH/2, SImode)); 5213 5214 /* Gen lui t2, hi(chain). */ 5215 rtx hi_chain = riscv_force_binary (SImode, PLUS, chain_value, 5216 fixup_value); 5217 hi_chain = riscv_force_binary (SImode, AND, hi_chain, 5218 uimm_mask); 5219 lui_hi_chain_code = OPCODE_LUI | (STATIC_CHAIN_REGNUM << SHIFT_RD); 5220 rtx lui_hi_chain = riscv_force_binary (SImode, IOR, hi_chain, 5221 gen_int_mode (lui_hi_chain_code, SImode)); 5222 5223 mem = adjust_address (m_tramp, SImode, 0); 5224 riscv_emit_move (mem, riscv_swap_instruction (lui_hi_chain)); 5225 5226 /* Gen lui t0, hi(func). */ 5227 rtx hi_func = riscv_force_binary (SImode, PLUS, target_function, 5228 fixup_value); 5229 hi_func = riscv_force_binary (SImode, AND, hi_func, 5230 uimm_mask); 5231 lui_hi_func_code = OPCODE_LUI | (RISCV_PROLOGUE_TEMP_REGNUM << SHIFT_RD); 5232 rtx lui_hi_func = riscv_force_binary (SImode, IOR, hi_func, 5233 gen_int_mode (lui_hi_func_code, SImode)); 5234 5235 mem = adjust_address (m_tramp, SImode, 1 * GET_MODE_SIZE (SImode)); 5236 riscv_emit_move (mem, riscv_swap_instruction (lui_hi_func)); 5237 5238 /* Gen addi t2, t2, lo(chain). */ 5239 rtx lo_chain = riscv_force_binary (SImode, AND, chain_value, 5240 imm12_mask); 5241 lo_chain = riscv_force_binary (SImode, ASHIFT, lo_chain, GEN_INT (20)); 5242 5243 lo_chain_code = OPCODE_ADDI 5244 | (STATIC_CHAIN_REGNUM << SHIFT_RD) 5245 | (STATIC_CHAIN_REGNUM << SHIFT_RS1); 5246 5247 rtx addi_lo_chain = riscv_force_binary (SImode, IOR, lo_chain, 5248 force_reg (SImode, GEN_INT (lo_chain_code))); 5249 5250 mem = adjust_address (m_tramp, SImode, 2 * GET_MODE_SIZE (SImode)); 5251 riscv_emit_move (mem, riscv_swap_instruction (addi_lo_chain)); 5252 5253 /* Gen jr t0, lo(func). */ 5254 rtx lo_func = riscv_force_binary (SImode, AND, target_function, 5255 imm12_mask); 5256 lo_func = riscv_force_binary (SImode, ASHIFT, lo_func, GEN_INT (20)); 5257 5258 lo_func_code = OPCODE_JALR | (RISCV_PROLOGUE_TEMP_REGNUM << SHIFT_RS1); 5259 5260 rtx jr_lo_func = riscv_force_binary (SImode, IOR, lo_func, 5261 force_reg (SImode, GEN_INT (lo_func_code))); 5262 5263 mem = adjust_address (m_tramp, SImode, 3 * GET_MODE_SIZE (SImode)); 5264 riscv_emit_move (mem, riscv_swap_instruction (jr_lo_func)); 5265 } 5266 else 5267 { 5268 static_chain_offset = TRAMPOLINE_CODE_SIZE; 5269 target_function_offset = static_chain_offset + GET_MODE_SIZE (ptr_mode); 5270 5271 /* auipc t2, 0 5272 l[wd] t0, target_function_offset(t2) 5273 l[wd] t2, static_chain_offset(t2) 5274 jr t0 5275 */ 5276 trampoline[0] = OPCODE_AUIPC | (STATIC_CHAIN_REGNUM << SHIFT_RD); 5277 trampoline[1] = (Pmode == DImode ? OPCODE_LD : OPCODE_LW) 5278 | (RISCV_PROLOGUE_TEMP_REGNUM << SHIFT_RD) 5279 | (STATIC_CHAIN_REGNUM << SHIFT_RS1) 5280 | (target_function_offset << SHIFT_IMM); 5281 trampoline[2] = (Pmode == DImode ? OPCODE_LD : OPCODE_LW) 5282 | (STATIC_CHAIN_REGNUM << SHIFT_RD) 5283 | (STATIC_CHAIN_REGNUM << SHIFT_RS1) 5284 | (static_chain_offset << SHIFT_IMM); 5285 trampoline[3] = OPCODE_JALR | (RISCV_PROLOGUE_TEMP_REGNUM << SHIFT_RS1); 5286 5287 /* Copy the trampoline code. */ 5288 for (i = 0; i < ARRAY_SIZE (trampoline); i++) 5289 { 5290 if (BYTES_BIG_ENDIAN) 5291 trampoline[i] = __builtin_bswap32(trampoline[i]); 5292 mem = adjust_address (m_tramp, SImode, i * GET_MODE_SIZE (SImode)); 5293 riscv_emit_move (mem, gen_int_mode (trampoline[i], SImode)); 5294 } 5295 5296 /* Set up the static chain pointer field. */ 5297 mem = adjust_address (m_tramp, ptr_mode, static_chain_offset); 5298 riscv_emit_move (mem, chain_value); 5299 5300 /* Set up the target function field. */ 5301 mem = adjust_address (m_tramp, ptr_mode, target_function_offset); 5302 riscv_emit_move (mem, XEXP (DECL_RTL (fndecl), 0)); 5303 } 5304 5305 /* Flush the code part of the trampoline. */ 5306 emit_insn (gen_add3_insn (end_addr, addr, GEN_INT (TRAMPOLINE_SIZE))); 5307 emit_insn (gen_clear_cache (addr, end_addr)); 5308 } 5309 5310 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */ 5311 5312 static bool 5313 riscv_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED, 5314 tree exp ATTRIBUTE_UNUSED) 5315 { 5316 /* Don't use sibcalls when use save-restore routine. */ 5317 if (TARGET_SAVE_RESTORE) 5318 return false; 5319 5320 /* Don't use sibcall for naked functions. */ 5321 if (cfun->machine->naked_p) 5322 return false; 5323 5324 /* Don't use sibcall for interrupt functions. */ 5325 if (cfun->machine->interrupt_handler_p) 5326 return false; 5327 5328 return true; 5329 } 5330 5331 /* Get the interrupt type, return UNKNOWN_MODE if it's not 5332 interrupt function. */ 5333 static enum riscv_privilege_levels 5334 riscv_get_interrupt_type (tree decl) 5335 { 5336 gcc_assert (decl != NULL_TREE); 5337 5338 if ((TREE_CODE(decl) != FUNCTION_DECL) 5339 || (!riscv_interrupt_type_p (TREE_TYPE (decl)))) 5340 return UNKNOWN_MODE; 5341 5342 tree attr_args 5343 = TREE_VALUE (lookup_attribute ("interrupt", 5344 TYPE_ATTRIBUTES (TREE_TYPE (decl)))); 5345 5346 if (attr_args && TREE_CODE (TREE_VALUE (attr_args)) != VOID_TYPE) 5347 { 5348 const char *string = TREE_STRING_POINTER (TREE_VALUE (attr_args)); 5349 5350 if (!strcmp (string, "user")) 5351 return USER_MODE; 5352 else if (!strcmp (string, "supervisor")) 5353 return SUPERVISOR_MODE; 5354 else /* Must be "machine". */ 5355 return MACHINE_MODE; 5356 } 5357 else 5358 /* Interrupt attributes are machine mode by default. */ 5359 return MACHINE_MODE; 5360 } 5361 5362 /* Implement `TARGET_SET_CURRENT_FUNCTION'. */ 5363 /* Sanity cheching for above function attributes. */ 5364 static void 5365 riscv_set_current_function (tree decl) 5366 { 5367 if (decl == NULL_TREE 5368 || current_function_decl == NULL_TREE 5369 || current_function_decl == error_mark_node 5370 || ! cfun->machine 5371 || cfun->machine->attributes_checked_p) 5372 return; 5373 5374 cfun->machine->naked_p = riscv_naked_function_p (decl); 5375 cfun->machine->interrupt_handler_p 5376 = riscv_interrupt_type_p (TREE_TYPE (decl)); 5377 5378 if (cfun->machine->naked_p && cfun->machine->interrupt_handler_p) 5379 error ("function attributes %qs and %qs are mutually exclusive", 5380 "interrupt", "naked"); 5381 5382 if (cfun->machine->interrupt_handler_p) 5383 { 5384 tree ret = TREE_TYPE (TREE_TYPE (decl)); 5385 tree args = TYPE_ARG_TYPES (TREE_TYPE (decl)); 5386 5387 if (TREE_CODE (ret) != VOID_TYPE) 5388 error ("%qs function cannot return a value", "interrupt"); 5389 5390 if (args && TREE_CODE (TREE_VALUE (args)) != VOID_TYPE) 5391 error ("%qs function cannot have arguments", "interrupt"); 5392 5393 cfun->machine->interrupt_mode = riscv_get_interrupt_type (decl); 5394 5395 gcc_assert (cfun->machine->interrupt_mode != UNKNOWN_MODE); 5396 } 5397 5398 /* Don't print the above diagnostics more than once. */ 5399 cfun->machine->attributes_checked_p = 1; 5400 } 5401 5402 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */ 5403 static tree 5404 riscv_merge_decl_attributes (tree olddecl, tree newdecl) 5405 { 5406 tree combined_attrs; 5407 5408 enum riscv_privilege_levels old_interrupt_type 5409 = riscv_get_interrupt_type (olddecl); 5410 enum riscv_privilege_levels new_interrupt_type 5411 = riscv_get_interrupt_type (newdecl); 5412 5413 /* Check old and new has same interrupt type. */ 5414 if ((old_interrupt_type != UNKNOWN_MODE) 5415 && (new_interrupt_type != UNKNOWN_MODE) 5416 && (old_interrupt_type != new_interrupt_type)) 5417 error ("%qs function cannot have different interrupt type", "interrupt"); 5418 5419 /* Create combined attributes. */ 5420 combined_attrs = merge_attributes (DECL_ATTRIBUTES (olddecl), 5421 DECL_ATTRIBUTES (newdecl)); 5422 5423 return combined_attrs; 5424 } 5425 5426 /* Implement TARGET_CANNOT_COPY_INSN_P. */ 5427 5428 static bool 5429 riscv_cannot_copy_insn_p (rtx_insn *insn) 5430 { 5431 return recog_memoized (insn) >= 0 && get_attr_cannot_copy (insn); 5432 } 5433 5434 /* Implement TARGET_SLOW_UNALIGNED_ACCESS. */ 5435 5436 static bool 5437 riscv_slow_unaligned_access (machine_mode, unsigned int) 5438 { 5439 return riscv_slow_unaligned_access_p; 5440 } 5441 5442 /* Implement TARGET_CAN_CHANGE_MODE_CLASS. */ 5443 5444 static bool 5445 riscv_can_change_mode_class (machine_mode, machine_mode, reg_class_t rclass) 5446 { 5447 return !reg_classes_intersect_p (FP_REGS, rclass); 5448 } 5449 5450 5451 /* Implement TARGET_CONSTANT_ALIGNMENT. */ 5452 5453 static HOST_WIDE_INT 5454 riscv_constant_alignment (const_tree exp, HOST_WIDE_INT align) 5455 { 5456 if ((TREE_CODE (exp) == STRING_CST || TREE_CODE (exp) == CONSTRUCTOR) 5457 && (riscv_align_data_type == riscv_align_data_type_xlen)) 5458 return MAX (align, BITS_PER_WORD); 5459 return align; 5460 } 5461 5462 /* Implement TARGET_PROMOTE_FUNCTION_MODE. */ 5463 5464 /* This function is equivalent to default_promote_function_mode_always_promote 5465 except that it returns a promoted mode even if type is NULL_TREE. This is 5466 needed by libcalls which have no type (only a mode) such as fixed conversion 5467 routines that take a signed or unsigned char/short/int argument and convert 5468 it to a fixed type. */ 5469 5470 static machine_mode 5471 riscv_promote_function_mode (const_tree type ATTRIBUTE_UNUSED, 5472 machine_mode mode, 5473 int *punsignedp ATTRIBUTE_UNUSED, 5474 const_tree fntype ATTRIBUTE_UNUSED, 5475 int for_return ATTRIBUTE_UNUSED) 5476 { 5477 int unsignedp; 5478 5479 if (type != NULL_TREE) 5480 return promote_mode (type, mode, punsignedp); 5481 5482 unsignedp = *punsignedp; 5483 PROMOTE_MODE (mode, unsignedp, type); 5484 *punsignedp = unsignedp; 5485 return mode; 5486 } 5487 5488 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */ 5489 5490 static void 5491 riscv_reorg (void) 5492 { 5493 /* Do nothing unless we have -msave-restore */ 5494 if (TARGET_SAVE_RESTORE) 5495 riscv_remove_unneeded_save_restore_calls (); 5496 } 5497 5498 /* Return nonzero if register FROM_REGNO can be renamed to register 5499 TO_REGNO. */ 5500 5501 bool 5502 riscv_hard_regno_rename_ok (unsigned from_regno ATTRIBUTE_UNUSED, 5503 unsigned to_regno) 5504 { 5505 /* Interrupt functions can only use registers that have already been 5506 saved by the prologue, even if they would normally be 5507 call-clobbered. */ 5508 return !cfun->machine->interrupt_handler_p || df_regs_ever_live_p (to_regno); 5509 } 5510 5511 /* Implement TARGET_NEW_ADDRESS_PROFITABLE_P. */ 5512 5513 bool 5514 riscv_new_address_profitable_p (rtx memref, rtx_insn *insn, rtx new_addr) 5515 { 5516 /* Prefer old address if it is less expensive. */ 5517 addr_space_t as = MEM_ADDR_SPACE (memref); 5518 bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)); 5519 int old_cost = address_cost (XEXP (memref, 0), GET_MODE (memref), as, speed); 5520 int new_cost = address_cost (new_addr, GET_MODE (memref), as, speed); 5521 return new_cost <= old_cost; 5522 } 5523 5524 /* Helper function for generating gpr_save pattern. */ 5525 5526 rtx 5527 riscv_gen_gpr_save_insn (struct riscv_frame_info *frame) 5528 { 5529 unsigned count = riscv_save_libcall_count (frame->mask); 5530 /* 1 for unspec 2 for clobber t0/t1 and 1 for ra. */ 5531 unsigned veclen = 1 + 2 + 1 + count; 5532 rtvec vec = rtvec_alloc (veclen); 5533 5534 gcc_assert (veclen <= ARRAY_SIZE (gpr_save_reg_order)); 5535 5536 RTVEC_ELT (vec, 0) = 5537 gen_rtx_UNSPEC_VOLATILE (VOIDmode, 5538 gen_rtvec (1, GEN_INT (count)), UNSPECV_GPR_SAVE); 5539 5540 for (unsigned i = 1; i < veclen; ++i) 5541 { 5542 unsigned regno = gpr_save_reg_order[i]; 5543 rtx reg = gen_rtx_REG (Pmode, regno); 5544 rtx elt; 5545 5546 /* t0 and t1 are CLOBBERs, others are USEs. */ 5547 if (i < 3) 5548 elt = gen_rtx_CLOBBER (Pmode, reg); 5549 else 5550 elt = gen_rtx_USE (Pmode, reg); 5551 5552 RTVEC_ELT (vec, i) = elt; 5553 } 5554 5555 /* Largest number of caller-save register must set in mask if we are 5556 not using __riscv_save_0. */ 5557 gcc_assert ((count == 0) || 5558 BITSET_P (frame->mask, gpr_save_reg_order[veclen - 1])); 5559 5560 return gen_rtx_PARALLEL (VOIDmode, vec); 5561 } 5562 5563 /* Return true if it's valid gpr_save pattern. */ 5564 5565 bool 5566 riscv_gpr_save_operation_p (rtx op) 5567 { 5568 unsigned len = XVECLEN (op, 0); 5569 5570 if (len > ARRAY_SIZE (gpr_save_reg_order)) 5571 return false; 5572 5573 for (unsigned i = 0; i < len; i++) 5574 { 5575 rtx elt = XVECEXP (op, 0, i); 5576 if (i == 0) 5577 { 5578 /* First element in parallel is unspec. */ 5579 if (GET_CODE (elt) != UNSPEC_VOLATILE 5580 || GET_CODE (XVECEXP (elt, 0, 0)) != CONST_INT 5581 || XINT (elt, 1) != UNSPECV_GPR_SAVE) 5582 return false; 5583 } 5584 else 5585 { 5586 /* Two CLOBBER and USEs, must check the order. */ 5587 unsigned expect_code = i < 3 ? CLOBBER : USE; 5588 if (GET_CODE (elt) != expect_code 5589 || !REG_P (XEXP (elt, 1)) 5590 || (REGNO (XEXP (elt, 1)) != gpr_save_reg_order[i])) 5591 return false; 5592 } 5593 break; 5594 } 5595 return true; 5596 } 5597 5598 /* Implement TARGET_ASAN_SHADOW_OFFSET. */ 5599 5600 static unsigned HOST_WIDE_INT 5601 riscv_asan_shadow_offset (void) 5602 { 5603 /* We only have libsanitizer support for RV64 at present. 5604 5605 This number must match kRiscv*_ShadowOffset* in the file 5606 libsanitizer/asan/asan_mapping.h. */ 5607 return TARGET_64BIT ? HOST_WIDE_INT_UC (0xd55550000) : 0; 5608 } 5609 5610 /* Initialize the GCC target structure. */ 5611 #undef TARGET_ASM_ALIGNED_HI_OP 5612 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t" 5613 #undef TARGET_ASM_ALIGNED_SI_OP 5614 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t" 5615 #undef TARGET_ASM_ALIGNED_DI_OP 5616 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t" 5617 5618 #undef TARGET_OPTION_OVERRIDE 5619 #define TARGET_OPTION_OVERRIDE riscv_option_override 5620 5621 #undef TARGET_LEGITIMIZE_ADDRESS 5622 #define TARGET_LEGITIMIZE_ADDRESS riscv_legitimize_address 5623 5624 #undef TARGET_SCHED_ISSUE_RATE 5625 #define TARGET_SCHED_ISSUE_RATE riscv_issue_rate 5626 5627 #undef TARGET_FUNCTION_OK_FOR_SIBCALL 5628 #define TARGET_FUNCTION_OK_FOR_SIBCALL riscv_function_ok_for_sibcall 5629 5630 #undef TARGET_SET_CURRENT_FUNCTION 5631 #define TARGET_SET_CURRENT_FUNCTION riscv_set_current_function 5632 5633 #undef TARGET_REGISTER_MOVE_COST 5634 #define TARGET_REGISTER_MOVE_COST riscv_register_move_cost 5635 #undef TARGET_MEMORY_MOVE_COST 5636 #define TARGET_MEMORY_MOVE_COST riscv_memory_move_cost 5637 #undef TARGET_RTX_COSTS 5638 #define TARGET_RTX_COSTS riscv_rtx_costs 5639 #undef TARGET_ADDRESS_COST 5640 #define TARGET_ADDRESS_COST riscv_address_cost 5641 5642 #undef TARGET_ASM_FILE_START 5643 #define TARGET_ASM_FILE_START riscv_file_start 5644 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE 5645 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true 5646 5647 #undef TARGET_EXPAND_BUILTIN_VA_START 5648 #define TARGET_EXPAND_BUILTIN_VA_START riscv_va_start 5649 5650 #undef TARGET_PROMOTE_FUNCTION_MODE 5651 #define TARGET_PROMOTE_FUNCTION_MODE riscv_promote_function_mode 5652 5653 #undef TARGET_RETURN_IN_MEMORY 5654 #define TARGET_RETURN_IN_MEMORY riscv_return_in_memory 5655 5656 #undef TARGET_ASM_OUTPUT_MI_THUNK 5657 #define TARGET_ASM_OUTPUT_MI_THUNK riscv_output_mi_thunk 5658 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK 5659 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true 5660 5661 #undef TARGET_PRINT_OPERAND 5662 #define TARGET_PRINT_OPERAND riscv_print_operand 5663 #undef TARGET_PRINT_OPERAND_ADDRESS 5664 #define TARGET_PRINT_OPERAND_ADDRESS riscv_print_operand_address 5665 5666 #undef TARGET_SETUP_INCOMING_VARARGS 5667 #define TARGET_SETUP_INCOMING_VARARGS riscv_setup_incoming_varargs 5668 #undef TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS 5669 #define TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS riscv_allocate_stack_slots_for_args 5670 #undef TARGET_STRICT_ARGUMENT_NAMING 5671 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true 5672 #undef TARGET_MUST_PASS_IN_STACK 5673 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size 5674 #undef TARGET_PASS_BY_REFERENCE 5675 #define TARGET_PASS_BY_REFERENCE riscv_pass_by_reference 5676 #undef TARGET_ARG_PARTIAL_BYTES 5677 #define TARGET_ARG_PARTIAL_BYTES riscv_arg_partial_bytes 5678 #undef TARGET_FUNCTION_ARG 5679 #define TARGET_FUNCTION_ARG riscv_function_arg 5680 #undef TARGET_FUNCTION_ARG_ADVANCE 5681 #define TARGET_FUNCTION_ARG_ADVANCE riscv_function_arg_advance 5682 #undef TARGET_FUNCTION_ARG_BOUNDARY 5683 #define TARGET_FUNCTION_ARG_BOUNDARY riscv_function_arg_boundary 5684 5685 /* The generic ELF target does not always have TLS support. */ 5686 #ifdef HAVE_AS_TLS 5687 #undef TARGET_HAVE_TLS 5688 #define TARGET_HAVE_TLS true 5689 #endif 5690 5691 #undef TARGET_CANNOT_FORCE_CONST_MEM 5692 #define TARGET_CANNOT_FORCE_CONST_MEM riscv_cannot_force_const_mem 5693 5694 #undef TARGET_LEGITIMATE_CONSTANT_P 5695 #define TARGET_LEGITIMATE_CONSTANT_P riscv_legitimate_constant_p 5696 5697 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P 5698 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true 5699 5700 #undef TARGET_LEGITIMATE_ADDRESS_P 5701 #define TARGET_LEGITIMATE_ADDRESS_P riscv_legitimate_address_p 5702 5703 #undef TARGET_CAN_ELIMINATE 5704 #define TARGET_CAN_ELIMINATE riscv_can_eliminate 5705 5706 #undef TARGET_CONDITIONAL_REGISTER_USAGE 5707 #define TARGET_CONDITIONAL_REGISTER_USAGE riscv_conditional_register_usage 5708 5709 #undef TARGET_CLASS_MAX_NREGS 5710 #define TARGET_CLASS_MAX_NREGS riscv_class_max_nregs 5711 5712 #undef TARGET_TRAMPOLINE_INIT 5713 #define TARGET_TRAMPOLINE_INIT riscv_trampoline_init 5714 5715 #undef TARGET_IN_SMALL_DATA_P 5716 #define TARGET_IN_SMALL_DATA_P riscv_in_small_data_p 5717 5718 #undef TARGET_HAVE_SRODATA_SECTION 5719 #define TARGET_HAVE_SRODATA_SECTION true 5720 5721 #undef TARGET_ASM_SELECT_SECTION 5722 #define TARGET_ASM_SELECT_SECTION riscv_select_section 5723 5724 #undef TARGET_ASM_UNIQUE_SECTION 5725 #define TARGET_ASM_UNIQUE_SECTION riscv_unique_section 5726 5727 #undef TARGET_ASM_SELECT_RTX_SECTION 5728 #define TARGET_ASM_SELECT_RTX_SECTION riscv_elf_select_rtx_section 5729 5730 #undef TARGET_MIN_ANCHOR_OFFSET 5731 #define TARGET_MIN_ANCHOR_OFFSET (-IMM_REACH/2) 5732 5733 #undef TARGET_MAX_ANCHOR_OFFSET 5734 #define TARGET_MAX_ANCHOR_OFFSET (IMM_REACH/2-1) 5735 5736 #undef TARGET_REGISTER_PRIORITY 5737 #define TARGET_REGISTER_PRIORITY riscv_register_priority 5738 5739 #undef TARGET_CANNOT_COPY_INSN_P 5740 #define TARGET_CANNOT_COPY_INSN_P riscv_cannot_copy_insn_p 5741 5742 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV 5743 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV riscv_atomic_assign_expand_fenv 5744 5745 #undef TARGET_INIT_BUILTINS 5746 #define TARGET_INIT_BUILTINS riscv_init_builtins 5747 5748 #undef TARGET_BUILTIN_DECL 5749 #define TARGET_BUILTIN_DECL riscv_builtin_decl 5750 5751 #undef TARGET_EXPAND_BUILTIN 5752 #define TARGET_EXPAND_BUILTIN riscv_expand_builtin 5753 5754 #undef TARGET_HARD_REGNO_NREGS 5755 #define TARGET_HARD_REGNO_NREGS riscv_hard_regno_nregs 5756 #undef TARGET_HARD_REGNO_MODE_OK 5757 #define TARGET_HARD_REGNO_MODE_OK riscv_hard_regno_mode_ok 5758 5759 #undef TARGET_MODES_TIEABLE_P 5760 #define TARGET_MODES_TIEABLE_P riscv_modes_tieable_p 5761 5762 #undef TARGET_SLOW_UNALIGNED_ACCESS 5763 #define TARGET_SLOW_UNALIGNED_ACCESS riscv_slow_unaligned_access 5764 5765 #undef TARGET_SECONDARY_MEMORY_NEEDED 5766 #define TARGET_SECONDARY_MEMORY_NEEDED riscv_secondary_memory_needed 5767 5768 #undef TARGET_CAN_CHANGE_MODE_CLASS 5769 #define TARGET_CAN_CHANGE_MODE_CLASS riscv_can_change_mode_class 5770 5771 #undef TARGET_CONSTANT_ALIGNMENT 5772 #define TARGET_CONSTANT_ALIGNMENT riscv_constant_alignment 5773 5774 #undef TARGET_MERGE_DECL_ATTRIBUTES 5775 #define TARGET_MERGE_DECL_ATTRIBUTES riscv_merge_decl_attributes 5776 5777 #undef TARGET_ATTRIBUTE_TABLE 5778 #define TARGET_ATTRIBUTE_TABLE riscv_attribute_table 5779 5780 #undef TARGET_WARN_FUNC_RETURN 5781 #define TARGET_WARN_FUNC_RETURN riscv_warn_func_return 5782 5783 /* The low bit is ignored by jump instructions so is safe to use. */ 5784 #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS 5785 #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 1 5786 5787 #undef TARGET_MACHINE_DEPENDENT_REORG 5788 #define TARGET_MACHINE_DEPENDENT_REORG riscv_reorg 5789 5790 #undef TARGET_NEW_ADDRESS_PROFITABLE_P 5791 #define TARGET_NEW_ADDRESS_PROFITABLE_P riscv_new_address_profitable_p 5792 5793 #undef TARGET_ASAN_SHADOW_OFFSET 5794 #define TARGET_ASAN_SHADOW_OFFSET riscv_asan_shadow_offset 5795 5796 #ifdef TARGET_BIG_ENDIAN_DEFAULT 5797 #undef TARGET_DEFAULT_TARGET_FLAGS 5798 #define TARGET_DEFAULT_TARGET_FLAGS (MASK_BIG_ENDIAN) 5799 #endif 5800 5801 struct gcc_target targetm = TARGET_INITIALIZER; 5802 5803 #include "gt-riscv.h" 5804
Indexes created Thu Jun 25 00:25:11 UTC 2026