1 /* $NetBSD: amdgpu_dcn20_hubbub.c,v 1.2 2021/12/18 23:45:03 riastradh Exp $ */ 2 3 /* 4 * Copyright 2016 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: AMD 25 * 26 */ 27 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: amdgpu_dcn20_hubbub.c,v 1.2 2021/12/18 23:45:03 riastradh Exp $"); 31 32 #include "dcn20_hubbub.h" 33 #include "reg_helper.h" 34 #include "clk_mgr.h" 35 36 #define REG(reg)\ 37 hubbub1->regs->reg 38 39 #define CTX \ 40 hubbub1->base.ctx 41 42 #undef FN 43 #define FN(reg_name, field_name) \ 44 hubbub1->shifts->field_name, hubbub1->masks->field_name 45 46 #define REG(reg)\ 47 hubbub1->regs->reg 48 49 #define CTX \ 50 hubbub1->base.ctx 51 52 #undef FN 53 #define FN(reg_name, field_name) \ 54 hubbub1->shifts->field_name, hubbub1->masks->field_name 55 56 #ifdef NUM_VMID 57 #undef NUM_VMID 58 #endif 59 #define NUM_VMID 16 60 61 bool hubbub2_dcc_support_swizzle( 62 enum swizzle_mode_values swizzle, 63 unsigned int bytes_per_element, 64 enum segment_order *segment_order_horz, 65 enum segment_order *segment_order_vert) 66 { 67 bool standard_swizzle = false; 68 bool display_swizzle = false; 69 bool render_swizzle = false; 70 71 switch (swizzle) { 72 case DC_SW_4KB_S: 73 case DC_SW_64KB_S: 74 case DC_SW_VAR_S: 75 case DC_SW_4KB_S_X: 76 case DC_SW_64KB_S_X: 77 case DC_SW_VAR_S_X: 78 standard_swizzle = true; 79 break; 80 case DC_SW_64KB_R_X: 81 render_swizzle = true; 82 break; 83 case DC_SW_4KB_D: 84 case DC_SW_64KB_D: 85 case DC_SW_VAR_D: 86 case DC_SW_4KB_D_X: 87 case DC_SW_64KB_D_X: 88 case DC_SW_VAR_D_X: 89 display_swizzle = true; 90 break; 91 default: 92 break; 93 } 94 95 if (standard_swizzle) { 96 if (bytes_per_element == 1) { 97 *segment_order_horz = segment_order__contiguous; 98 *segment_order_vert = segment_order__na; 99 return true; 100 } 101 if (bytes_per_element == 2) { 102 *segment_order_horz = segment_order__non_contiguous; 103 *segment_order_vert = segment_order__contiguous; 104 return true; 105 } 106 if (bytes_per_element == 4) { 107 *segment_order_horz = segment_order__non_contiguous; 108 *segment_order_vert = segment_order__contiguous; 109 return true; 110 } 111 if (bytes_per_element == 8) { 112 *segment_order_horz = segment_order__na; 113 *segment_order_vert = segment_order__contiguous; 114 return true; 115 } 116 } 117 if (render_swizzle) { 118 if (bytes_per_element == 2) { 119 *segment_order_horz = segment_order__contiguous; 120 *segment_order_vert = segment_order__contiguous; 121 return true; 122 } 123 if (bytes_per_element == 4) { 124 *segment_order_horz = segment_order__non_contiguous; 125 *segment_order_vert = segment_order__contiguous; 126 return true; 127 } 128 if (bytes_per_element == 8) { 129 *segment_order_horz = segment_order__contiguous; 130 *segment_order_vert = segment_order__non_contiguous; 131 return true; 132 } 133 } 134 if (display_swizzle && bytes_per_element == 8) { 135 *segment_order_horz = segment_order__contiguous; 136 *segment_order_vert = segment_order__non_contiguous; 137 return true; 138 } 139 140 return false; 141 } 142 143 bool hubbub2_dcc_support_pixel_format( 144 enum surface_pixel_format format, 145 unsigned int *bytes_per_element) 146 { 147 /* DML: get_bytes_per_element */ 148 switch (format) { 149 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: 150 case SURFACE_PIXEL_FORMAT_GRPH_RGB565: 151 *bytes_per_element = 2; 152 return true; 153 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 154 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 155 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: 156 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: 157 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX: 158 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX: 159 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT: 160 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT: 161 *bytes_per_element = 4; 162 return true; 163 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 164 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: 165 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: 166 *bytes_per_element = 8; 167 return true; 168 default: 169 return false; 170 } 171 } 172 173 static void hubbub2_get_blk256_size(unsigned int *blk256_width, unsigned int *blk256_height, 174 unsigned int bytes_per_element) 175 { 176 /* copied from DML. might want to refactor DML to leverage from DML */ 177 /* DML : get_blk256_size */ 178 if (bytes_per_element == 1) { 179 *blk256_width = 16; 180 *blk256_height = 16; 181 } else if (bytes_per_element == 2) { 182 *blk256_width = 16; 183 *blk256_height = 8; 184 } else if (bytes_per_element == 4) { 185 *blk256_width = 8; 186 *blk256_height = 8; 187 } else if (bytes_per_element == 8) { 188 *blk256_width = 8; 189 *blk256_height = 4; 190 } 191 } 192 193 static void hubbub2_det_request_size( 194 unsigned int detile_buf_size, 195 unsigned int height, 196 unsigned int width, 197 unsigned int bpe, 198 bool *req128_horz_wc, 199 bool *req128_vert_wc) 200 { 201 unsigned int blk256_height = 0; 202 unsigned int blk256_width = 0; 203 unsigned int swath_bytes_horz_wc, swath_bytes_vert_wc; 204 205 hubbub2_get_blk256_size(&blk256_width, &blk256_height, bpe); 206 207 swath_bytes_horz_wc = width * blk256_height * bpe; 208 swath_bytes_vert_wc = height * blk256_width * bpe; 209 210 *req128_horz_wc = (2 * swath_bytes_horz_wc <= detile_buf_size) ? 211 false : /* full 256B request */ 212 true; /* half 128b request */ 213 214 *req128_vert_wc = (2 * swath_bytes_vert_wc <= detile_buf_size) ? 215 false : /* full 256B request */ 216 true; /* half 128b request */ 217 } 218 219 bool hubbub2_get_dcc_compression_cap(struct hubbub *hubbub, 220 const struct dc_dcc_surface_param *input, 221 struct dc_surface_dcc_cap *output) 222 { 223 struct dc *dc = hubbub->ctx->dc; 224 /* implement section 1.6.2.1 of DCN1_Programming_Guide.docx */ 225 enum dcc_control dcc_control; 226 unsigned int bpe; 227 enum segment_order segment_order_horz, segment_order_vert; 228 bool req128_horz_wc, req128_vert_wc; 229 230 memset(output, 0, sizeof(*output)); 231 232 if (dc->debug.disable_dcc == DCC_DISABLE) 233 return false; 234 235 if (!hubbub->funcs->dcc_support_pixel_format(input->format, 236 &bpe)) 237 return false; 238 239 if (!hubbub->funcs->dcc_support_swizzle(input->swizzle_mode, bpe, 240 &segment_order_horz, &segment_order_vert)) 241 return false; 242 243 hubbub2_det_request_size(TO_DCN20_HUBBUB(hubbub)->detile_buf_size, 244 input->surface_size.height, input->surface_size.width, 245 bpe, &req128_horz_wc, &req128_vert_wc); 246 247 if (!req128_horz_wc && !req128_vert_wc) { 248 dcc_control = dcc_control__256_256_xxx; 249 } else if (input->scan == SCAN_DIRECTION_HORIZONTAL) { 250 if (!req128_horz_wc) 251 dcc_control = dcc_control__256_256_xxx; 252 else if (segment_order_horz == segment_order__contiguous) 253 dcc_control = dcc_control__128_128_xxx; 254 else 255 dcc_control = dcc_control__256_64_64; 256 } else if (input->scan == SCAN_DIRECTION_VERTICAL) { 257 if (!req128_vert_wc) 258 dcc_control = dcc_control__256_256_xxx; 259 else if (segment_order_vert == segment_order__contiguous) 260 dcc_control = dcc_control__128_128_xxx; 261 else 262 dcc_control = dcc_control__256_64_64; 263 } else { 264 if ((req128_horz_wc && 265 segment_order_horz == segment_order__non_contiguous) || 266 (req128_vert_wc && 267 segment_order_vert == segment_order__non_contiguous)) 268 /* access_dir not known, must use most constraining */ 269 dcc_control = dcc_control__256_64_64; 270 else 271 /* reg128 is true for either horz and vert 272 * but segment_order is contiguous 273 */ 274 dcc_control = dcc_control__128_128_xxx; 275 } 276 277 /* Exception for 64KB_R_X */ 278 if ((bpe == 2) && (input->swizzle_mode == DC_SW_64KB_R_X)) 279 dcc_control = dcc_control__128_128_xxx; 280 281 if (dc->debug.disable_dcc == DCC_HALF_REQ_DISALBE && 282 dcc_control != dcc_control__256_256_xxx) 283 return false; 284 285 switch (dcc_control) { 286 case dcc_control__256_256_xxx: 287 output->grph.rgb.max_uncompressed_blk_size = 256; 288 output->grph.rgb.max_compressed_blk_size = 256; 289 output->grph.rgb.independent_64b_blks = false; 290 break; 291 case dcc_control__128_128_xxx: 292 output->grph.rgb.max_uncompressed_blk_size = 128; 293 output->grph.rgb.max_compressed_blk_size = 128; 294 output->grph.rgb.independent_64b_blks = false; 295 break; 296 case dcc_control__256_64_64: 297 output->grph.rgb.max_uncompressed_blk_size = 256; 298 output->grph.rgb.max_compressed_blk_size = 64; 299 output->grph.rgb.independent_64b_blks = true; 300 break; 301 default: 302 ASSERT(false); 303 break; 304 } 305 output->capable = true; 306 output->const_color_support = true; 307 308 return true; 309 } 310 311 static enum dcn_hubbub_page_table_depth page_table_depth_to_hw(unsigned int page_table_depth) 312 { 313 enum dcn_hubbub_page_table_depth depth = 0; 314 315 switch (page_table_depth) { 316 case 1: 317 depth = DCN_PAGE_TABLE_DEPTH_1_LEVEL; 318 break; 319 case 2: 320 depth = DCN_PAGE_TABLE_DEPTH_2_LEVEL; 321 break; 322 case 3: 323 depth = DCN_PAGE_TABLE_DEPTH_3_LEVEL; 324 break; 325 case 4: 326 depth = DCN_PAGE_TABLE_DEPTH_4_LEVEL; 327 break; 328 default: 329 ASSERT(false); 330 break; 331 } 332 333 return depth; 334 } 335 336 static enum dcn_hubbub_page_table_block_size page_table_block_size_to_hw(unsigned int page_table_block_size) 337 { 338 enum dcn_hubbub_page_table_block_size block_size = 0; 339 340 switch (page_table_block_size) { 341 case 4096: 342 block_size = DCN_PAGE_TABLE_BLOCK_SIZE_4KB; 343 break; 344 case 65536: 345 block_size = DCN_PAGE_TABLE_BLOCK_SIZE_64KB; 346 break; 347 default: 348 ASSERT(false); 349 block_size = page_table_block_size; 350 break; 351 } 352 353 return block_size; 354 } 355 356 void hubbub2_init_vm_ctx(struct hubbub *hubbub, 357 struct dcn_hubbub_virt_addr_config *va_config, 358 int vmid) 359 { 360 struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub); 361 struct dcn_vmid_page_table_config virt_config; 362 363 virt_config.page_table_start_addr = va_config->page_table_start_addr >> 12; 364 virt_config.page_table_end_addr = va_config->page_table_end_addr >> 12; 365 virt_config.depth = page_table_depth_to_hw(va_config->page_table_depth); 366 virt_config.block_size = page_table_block_size_to_hw(va_config->page_table_block_size); 367 virt_config.page_table_base_addr = va_config->page_table_base_addr; 368 369 dcn20_vmid_setup(&hubbub1->vmid[vmid], &virt_config); 370 } 371 372 int hubbub2_init_dchub_sys_ctx(struct hubbub *hubbub, 373 struct dcn_hubbub_phys_addr_config *pa_config) 374 { 375 struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub); 376 struct dcn_vmid_page_table_config phys_config; 377 378 REG_SET(DCN_VM_FB_LOCATION_BASE, 0, 379 FB_BASE, pa_config->system_aperture.fb_base >> 24); 380 REG_SET(DCN_VM_FB_LOCATION_TOP, 0, 381 FB_TOP, pa_config->system_aperture.fb_top >> 24); 382 REG_SET(DCN_VM_FB_OFFSET, 0, 383 FB_OFFSET, pa_config->system_aperture.fb_offset >> 24); 384 REG_SET(DCN_VM_AGP_BOT, 0, 385 AGP_BOT, pa_config->system_aperture.agp_bot >> 24); 386 REG_SET(DCN_VM_AGP_TOP, 0, 387 AGP_TOP, pa_config->system_aperture.agp_top >> 24); 388 REG_SET(DCN_VM_AGP_BASE, 0, 389 AGP_BASE, pa_config->system_aperture.agp_base >> 24); 390 391 REG_SET(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB, 0, 392 DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB, (pa_config->page_table_default_page_addr >> 44) & 0xF); 393 REG_SET(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB, 0, 394 DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB, (pa_config->page_table_default_page_addr >> 12) & 0xFFFFFFFF); 395 396 if (pa_config->gart_config.page_table_start_addr != pa_config->gart_config.page_table_end_addr) { 397 phys_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr >> 12; 398 phys_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr >> 12; 399 phys_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr; 400 phys_config.depth = 0; 401 phys_config.block_size = 0; 402 // Init VMID 0 based on PA config 403 dcn20_vmid_setup(&hubbub1->vmid[0], &phys_config); 404 } 405 406 return NUM_VMID; 407 } 408 409 void hubbub2_update_dchub(struct hubbub *hubbub, 410 struct dchub_init_data *dh_data) 411 { 412 struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub); 413 414 if (REG(DCN_VM_FB_LOCATION_TOP) == 0) 415 return; 416 417 switch (dh_data->fb_mode) { 418 case FRAME_BUFFER_MODE_ZFB_ONLY: 419 /*For ZFB case need to put DCHUB FB BASE and TOP upside down to indicate ZFB mode*/ 420 REG_UPDATE(DCN_VM_FB_LOCATION_TOP, 421 FB_TOP, 0); 422 423 REG_UPDATE(DCN_VM_FB_LOCATION_BASE, 424 FB_BASE, 0xFFFFFF); 425 426 /*This field defines the 24 MSBs, bits [47:24] of the 48 bit AGP Base*/ 427 REG_UPDATE(DCN_VM_AGP_BASE, 428 AGP_BASE, dh_data->zfb_phys_addr_base >> 24); 429 430 /*This field defines the bottom range of the AGP aperture and represents the 24*/ 431 /*MSBs, bits [47:24] of the 48 address bits*/ 432 REG_UPDATE(DCN_VM_AGP_BOT, 433 AGP_BOT, dh_data->zfb_mc_base_addr >> 24); 434 435 /*This field defines the top range of the AGP aperture and represents the 24*/ 436 /*MSBs, bits [47:24] of the 48 address bits*/ 437 REG_UPDATE(DCN_VM_AGP_TOP, 438 AGP_TOP, (dh_data->zfb_mc_base_addr + 439 dh_data->zfb_size_in_byte - 1) >> 24); 440 break; 441 case FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL: 442 /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/ 443 444 /*This field defines the 24 MSBs, bits [47:24] of the 48 bit AGP Base*/ 445 REG_UPDATE(DCN_VM_AGP_BASE, 446 AGP_BASE, dh_data->zfb_phys_addr_base >> 24); 447 448 /*This field defines the bottom range of the AGP aperture and represents the 24*/ 449 /*MSBs, bits [47:24] of the 48 address bits*/ 450 REG_UPDATE(DCN_VM_AGP_BOT, 451 AGP_BOT, dh_data->zfb_mc_base_addr >> 24); 452 453 /*This field defines the top range of the AGP aperture and represents the 24*/ 454 /*MSBs, bits [47:24] of the 48 address bits*/ 455 REG_UPDATE(DCN_VM_AGP_TOP, 456 AGP_TOP, (dh_data->zfb_mc_base_addr + 457 dh_data->zfb_size_in_byte - 1) >> 24); 458 break; 459 case FRAME_BUFFER_MODE_LOCAL_ONLY: 460 /*Should not touch FB LOCATION (should be done by VBIOS)*/ 461 462 /*This field defines the 24 MSBs, bits [47:24] of the 48 bit AGP Base*/ 463 REG_UPDATE(DCN_VM_AGP_BASE, 464 AGP_BASE, 0); 465 466 /*This field defines the bottom range of the AGP aperture and represents the 24*/ 467 /*MSBs, bits [47:24] of the 48 address bits*/ 468 REG_UPDATE(DCN_VM_AGP_BOT, 469 AGP_BOT, 0xFFFFFF); 470 471 /*This field defines the top range of the AGP aperture and represents the 24*/ 472 /*MSBs, bits [47:24] of the 48 address bits*/ 473 REG_UPDATE(DCN_VM_AGP_TOP, 474 AGP_TOP, 0); 475 break; 476 default: 477 break; 478 } 479 480 dh_data->dchub_initialzied = true; 481 dh_data->dchub_info_valid = false; 482 } 483 484 void hubbub2_wm_read_state(struct hubbub *hubbub, 485 struct dcn_hubbub_wm *wm) 486 { 487 struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub); 488 489 struct dcn_hubbub_wm_set *s; 490 491 memset(wm, 0, sizeof(struct dcn_hubbub_wm)); 492 493 s = &wm->sets[0]; 494 s->wm_set = 0; 495 s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A); 496 if (REG(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A)) 497 s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A); 498 if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A)) { 499 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A); 500 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A); 501 } 502 s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A); 503 504 s = &wm->sets[1]; 505 s->wm_set = 1; 506 s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B); 507 if (REG(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B)) 508 s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B); 509 if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B)) { 510 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B); 511 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B); 512 } 513 s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B); 514 515 s = &wm->sets[2]; 516 s->wm_set = 2; 517 s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C); 518 if (REG(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C)) 519 s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C); 520 if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C)) { 521 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C); 522 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C); 523 } 524 s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C); 525 526 s = &wm->sets[3]; 527 s->wm_set = 3; 528 s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D); 529 if (REG(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D)) 530 s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D); 531 if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D)) { 532 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D); 533 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D); 534 } 535 s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D); 536 } 537 538 void hubbub2_get_dchub_ref_freq(struct hubbub *hubbub, 539 unsigned int dccg_ref_freq_inKhz, 540 unsigned int *dchub_ref_freq_inKhz) 541 { 542 struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub); 543 uint32_t ref_div = 0; 544 uint32_t ref_en = 0; 545 546 REG_GET_2(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, &ref_div, 547 DCHUBBUB_GLOBAL_TIMER_ENABLE, &ref_en); 548 549 if (ref_en) { 550 if (ref_div == 2) 551 *dchub_ref_freq_inKhz = dccg_ref_freq_inKhz / 2; 552 else 553 *dchub_ref_freq_inKhz = dccg_ref_freq_inKhz; 554 555 // DC hub reference frequency must be around 50Mhz, otherwise there may be 556 // overflow/underflow issues when doing HUBBUB programming 557 if (*dchub_ref_freq_inKhz < 40000 || *dchub_ref_freq_inKhz > 60000) 558 ASSERT_CRITICAL(false); 559 560 return; 561 } else { 562 *dchub_ref_freq_inKhz = dccg_ref_freq_inKhz; 563 564 // HUBBUB global timer must be enabled. 565 ASSERT_CRITICAL(false); 566 return; 567 } 568 } 569 570 static void hubbub2_program_watermarks( 571 struct hubbub *hubbub, 572 struct dcn_watermark_set *watermarks, 573 unsigned int refclk_mhz, 574 bool safe_to_lower) 575 { 576 struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub); 577 /* 578 * Need to clamp to max of the register values (i.e. no wrap) 579 * for dcn1, all wm registers are 21-bit wide 580 */ 581 hubbub1_program_urgent_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower); 582 hubbub1_program_stutter_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower); 583 584 /* 585 * There's a special case when going from p-state support to p-state unsupported 586 * here we are going to LOWER watermarks to go to dummy p-state only, but this has 587 * to be done prepare_bandwidth, not optimize 588 */ 589 if (hubbub1->base.ctx->dc->clk_mgr->clks.prev_p_state_change_support == true && 590 hubbub1->base.ctx->dc->clk_mgr->clks.p_state_change_support == false) 591 safe_to_lower = true; 592 593 hubbub1_program_pstate_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower); 594 595 REG_SET(DCHUBBUB_ARB_SAT_LEVEL, 0, 596 DCHUBBUB_ARB_SAT_LEVEL, 60 * refclk_mhz); 597 REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 180); 598 599 hubbub->funcs->allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter); 600 } 601 602 static const struct hubbub_funcs hubbub2_funcs = { 603 .update_dchub = hubbub2_update_dchub, 604 .init_dchub_sys_ctx = hubbub2_init_dchub_sys_ctx, 605 .init_vm_ctx = hubbub2_init_vm_ctx, 606 .dcc_support_swizzle = hubbub2_dcc_support_swizzle, 607 .dcc_support_pixel_format = hubbub2_dcc_support_pixel_format, 608 .get_dcc_compression_cap = hubbub2_get_dcc_compression_cap, 609 .wm_read_state = hubbub2_wm_read_state, 610 .get_dchub_ref_freq = hubbub2_get_dchub_ref_freq, 611 .program_watermarks = hubbub2_program_watermarks, 612 .is_allow_self_refresh_enabled = hubbub1_is_allow_self_refresh_enabled, 613 .allow_self_refresh_control = hubbub1_allow_self_refresh_control, 614 }; 615 616 void hubbub2_construct(struct dcn20_hubbub *hubbub, 617 struct dc_context *ctx, 618 const struct dcn_hubbub_registers *hubbub_regs, 619 const struct dcn_hubbub_shift *hubbub_shift, 620 const struct dcn_hubbub_mask *hubbub_mask) 621 { 622 hubbub->base.ctx = ctx; 623 624 hubbub->base.funcs = &hubbub2_funcs; 625 626 hubbub->regs = hubbub_regs; 627 hubbub->shifts = hubbub_shift; 628 hubbub->masks = hubbub_mask; 629 630 hubbub->debug_test_index_pstate = 0xB; 631 hubbub->detile_buf_size = 164 * 1024; /* 164KB for DCN2.0 */ 632 } 633
Indexes created Tue Sep 23 14:10:03 GMT 2025