1 /* $NetBSD: amdgpu_dcn21_hubp.c,v 1.3 2021/12/19 11:35:07 riastradh Exp $ */ 2 3 /* 4 * Copyright 2018 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: AMD 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: amdgpu_dcn21_hubp.c,v 1.3 2021/12/19 11:35:07 riastradh Exp $"); 30 31 #include "dcn10/dcn10_hubp.h" 32 #include "dcn21_hubp.h" 33 34 #include "dm_services.h" 35 #include "reg_helper.h" 36 37 #include "dc_dmub_srv.h" 38 39 #define DC_LOGGER_INIT(logger) 40 41 #define REG(reg)\ 42 hubp21->hubp_regs->reg 43 44 #define CTX \ 45 hubp21->base.ctx 46 47 #undef FN 48 #define FN(reg_name, field_name) \ 49 hubp21->hubp_shift->field_name, hubp21->hubp_mask->field_name 50 51 /* 52 * In DCN2.1, the non-double buffered version of the following 4 DLG registers are used in RTL. 53 * As a result, if S/W updates any of these registers during a mode change, 54 * the current frame before the mode change will use the new value right away 55 * and can lead to generating incorrect request deadlines and incorrect TTU/QoS behavior. 56 * 57 * REFCYC_PER_VM_GROUP_FLIP[22:0] 58 * REFCYC_PER_VM_GROUP_VBLANK[22:0] 59 * REFCYC_PER_VM_REQ_FLIP[22:0] 60 * REFCYC_PER_VM_REQ_VBLANK[22:0] 61 * 62 * REFCYC_PER_VM_*_FLIP affects the deadline of the VM requests generated 63 * when flipping to a new surface 64 * 65 * REFCYC_PER_VM_*_VBLANK affects the deadline of the VM requests generated 66 * during prefetch period of a frame. The prefetch starts at a pre-determined 67 * number of lines before the display active per frame 68 * 69 * DCN may underflow due to incorrectly programming these registers 70 * during VM stage of prefetch/iflip. First lines of display active 71 * or a sub-region of active using a new surface will be corrupted 72 * until the VM data returns at flip/mode change transitions 73 * 74 * Work around: 75 * workaround is always opt to use the more aggressive settings. 76 * On any mode switch, if the new reg values are smaller than the current values, 77 * then update the regs with the new values. 78 * 79 * Link to the ticket: http://ontrack-internal.amd.com/browse/DEDCN21-142 80 * 81 */ 82 void apply_DEDCN21_142_wa_for_hostvm_deadline( 83 struct hubp *hubp, 84 struct _vcs_dpi_display_dlg_regs_st *dlg_attr) 85 { 86 struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 87 uint32_t cur_value; 88 89 REG_GET(VBLANK_PARAMETERS_5, REFCYC_PER_VM_GROUP_VBLANK, &cur_value); 90 if (cur_value > dlg_attr->refcyc_per_vm_group_vblank) 91 REG_SET(VBLANK_PARAMETERS_5, 0, 92 REFCYC_PER_VM_GROUP_VBLANK, dlg_attr->refcyc_per_vm_group_vblank); 93 94 REG_GET(VBLANK_PARAMETERS_6, 95 REFCYC_PER_VM_REQ_VBLANK, 96 &cur_value); 97 if (cur_value > dlg_attr->refcyc_per_vm_req_vblank) 98 REG_SET(VBLANK_PARAMETERS_6, 0, 99 REFCYC_PER_VM_REQ_VBLANK, dlg_attr->refcyc_per_vm_req_vblank); 100 101 REG_GET(FLIP_PARAMETERS_3, REFCYC_PER_VM_GROUP_FLIP, &cur_value); 102 if (cur_value > dlg_attr->refcyc_per_vm_group_flip) 103 REG_SET(FLIP_PARAMETERS_3, 0, 104 REFCYC_PER_VM_GROUP_FLIP, dlg_attr->refcyc_per_vm_group_flip); 105 106 REG_GET(FLIP_PARAMETERS_4, REFCYC_PER_VM_REQ_FLIP, &cur_value); 107 if (cur_value > dlg_attr->refcyc_per_vm_req_flip) 108 REG_SET(FLIP_PARAMETERS_4, 0, 109 REFCYC_PER_VM_REQ_FLIP, dlg_attr->refcyc_per_vm_req_flip); 110 111 REG_SET(FLIP_PARAMETERS_5, 0, 112 REFCYC_PER_PTE_GROUP_FLIP_C, dlg_attr->refcyc_per_pte_group_flip_c); 113 REG_SET(FLIP_PARAMETERS_6, 0, 114 REFCYC_PER_META_CHUNK_FLIP_C, dlg_attr->refcyc_per_meta_chunk_flip_c); 115 } 116 117 void hubp21_program_deadline( 118 struct hubp *hubp, 119 struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 120 struct _vcs_dpi_display_ttu_regs_st *ttu_attr) 121 { 122 hubp2_program_deadline(hubp, dlg_attr, ttu_attr); 123 124 apply_DEDCN21_142_wa_for_hostvm_deadline(hubp, dlg_attr); 125 } 126 127 void hubp21_program_requestor( 128 struct hubp *hubp, 129 struct _vcs_dpi_display_rq_regs_st *rq_regs) 130 { 131 struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 132 133 REG_UPDATE(HUBPRET_CONTROL, 134 DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address); 135 REG_SET_4(DCN_EXPANSION_MODE, 0, 136 DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode, 137 PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode, 138 MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode, 139 CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode); 140 REG_SET_8(DCHUBP_REQ_SIZE_CONFIG, 0, 141 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size, 142 MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size, 143 META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size, 144 MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size, 145 DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size, 146 VM_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size, 147 SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height, 148 PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear); 149 REG_SET_7(DCHUBP_REQ_SIZE_CONFIG_C, 0, 150 CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size, 151 MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size, 152 META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size, 153 MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size, 154 DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size, 155 SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height, 156 PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear); 157 } 158 159 static void hubp21_setup( 160 struct hubp *hubp, 161 struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 162 struct _vcs_dpi_display_ttu_regs_st *ttu_attr, 163 struct _vcs_dpi_display_rq_regs_st *rq_regs, 164 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest) 165 { 166 /* otg is locked when this func is called. Register are double buffered. 167 * disable the requestors is not needed 168 */ 169 170 hubp2_vready_at_or_After_vsync(hubp, pipe_dest); 171 hubp21_program_requestor(hubp, rq_regs); 172 hubp21_program_deadline(hubp, dlg_attr, ttu_attr); 173 174 } 175 176 void hubp21_set_viewport( 177 struct hubp *hubp, 178 const struct rect *viewport, 179 const struct rect *viewport_c) 180 { 181 struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 182 183 REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 0, 184 PRI_VIEWPORT_WIDTH, viewport->width, 185 PRI_VIEWPORT_HEIGHT, viewport->height); 186 187 REG_SET_2(DCSURF_PRI_VIEWPORT_START, 0, 188 PRI_VIEWPORT_X_START, viewport->x, 189 PRI_VIEWPORT_Y_START, viewport->y); 190 191 /*for stereo*/ 192 REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION, 0, 193 SEC_VIEWPORT_WIDTH, viewport->width, 194 SEC_VIEWPORT_HEIGHT, viewport->height); 195 196 REG_SET_2(DCSURF_SEC_VIEWPORT_START, 0, 197 SEC_VIEWPORT_X_START, viewport->x, 198 SEC_VIEWPORT_Y_START, viewport->y); 199 200 /* DC supports NV12 only at the moment */ 201 REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION_C, 0, 202 PRI_VIEWPORT_WIDTH_C, viewport_c->width, 203 PRI_VIEWPORT_HEIGHT_C, viewport_c->height); 204 205 REG_SET_2(DCSURF_PRI_VIEWPORT_START_C, 0, 206 PRI_VIEWPORT_X_START_C, viewport_c->x, 207 PRI_VIEWPORT_Y_START_C, viewport_c->y); 208 209 REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION_C, 0, 210 SEC_VIEWPORT_WIDTH_C, viewport_c->width, 211 SEC_VIEWPORT_HEIGHT_C, viewport_c->height); 212 213 REG_SET_2(DCSURF_SEC_VIEWPORT_START_C, 0, 214 SEC_VIEWPORT_X_START_C, viewport_c->x, 215 SEC_VIEWPORT_Y_START_C, viewport_c->y); 216 } 217 218 static void hubp21_apply_PLAT_54186_wa( 219 struct hubp *hubp, 220 const struct dc_plane_address *address) 221 { 222 struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 223 struct dc_debug_options *debug = &hubp->ctx->dc->debug; 224 unsigned int chroma_bpe = 2; 225 unsigned int luma_addr_high_part = 0; 226 unsigned int row_height = 0; 227 unsigned int chroma_pitch = 0; 228 unsigned int viewport_c_height = 0; 229 unsigned int viewport_c_width = 0; 230 unsigned int patched_viewport_height = 0; 231 unsigned int patched_viewport_width = 0; 232 unsigned int rotation_angle = 0; 233 unsigned int pix_format = 0; 234 unsigned int h_mirror_en = 0; 235 unsigned int tile_blk_size = 64 * 1024; /* 64KB for 64KB SW, 4KB for 4KB SW */ 236 237 238 if (!debug->nv12_iflip_vm_wa) 239 return; 240 241 REG_GET(DCHUBP_REQ_SIZE_CONFIG_C, 242 PTE_ROW_HEIGHT_LINEAR_C, &row_height); 243 244 REG_GET_2(DCSURF_PRI_VIEWPORT_DIMENSION_C, 245 PRI_VIEWPORT_WIDTH_C, &viewport_c_width, 246 PRI_VIEWPORT_HEIGHT_C, &viewport_c_height); 247 248 REG_GET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 249 PRIMARY_SURFACE_ADDRESS_HIGH_C, &luma_addr_high_part); 250 251 REG_GET(DCSURF_SURFACE_PITCH_C, 252 PITCH_C, &chroma_pitch); 253 254 chroma_pitch += 1; 255 256 REG_GET_3(DCSURF_SURFACE_CONFIG, 257 SURFACE_PIXEL_FORMAT, &pix_format, 258 ROTATION_ANGLE, &rotation_angle, 259 H_MIRROR_EN, &h_mirror_en); 260 261 /* reset persistent cached data */ 262 hubp21->PLAT_54186_wa_chroma_addr_offset = 0; 263 /* apply wa only for NV12 surface with scatter gather enabled with viewport > 512 along 264 * the vertical direction*/ 265 if (address->type != PLN_ADDR_TYPE_VIDEO_PROGRESSIVE || 266 address->video_progressive.luma_addr.high_part == 0xf4) 267 return; 268 269 if ((rotation_angle == ROTATION_ANGLE_0 || rotation_angle == ROTATION_ANGLE_180) 270 && viewport_c_height <= 512) 271 return; 272 273 if ((rotation_angle == ROTATION_ANGLE_90 || rotation_angle == ROTATION_ANGLE_270) 274 && viewport_c_width <= 512) 275 return; 276 277 switch (rotation_angle) { 278 case ROTATION_ANGLE_0: /* 0 degree rotation */ 279 row_height = 128; 280 patched_viewport_height = (viewport_c_height / row_height + 1) * row_height + 1; 281 patched_viewport_width = viewport_c_width; 282 hubp21->PLAT_54186_wa_chroma_addr_offset = 0; 283 break; 284 case ROTATION_ANGLE_180: /* 180 degree rotation */ 285 row_height = 128; 286 patched_viewport_height = viewport_c_height + row_height; 287 patched_viewport_width = viewport_c_width; 288 hubp21->PLAT_54186_wa_chroma_addr_offset = 0 - chroma_pitch * row_height * chroma_bpe; 289 break; 290 case ROTATION_ANGLE_90: /* 90 degree rotation */ 291 row_height = 256; 292 if (h_mirror_en) { 293 patched_viewport_height = viewport_c_height; 294 patched_viewport_width = viewport_c_width + row_height; 295 hubp21->PLAT_54186_wa_chroma_addr_offset = 0; 296 } else { 297 patched_viewport_height = viewport_c_height; 298 patched_viewport_width = viewport_c_width + row_height; 299 hubp21->PLAT_54186_wa_chroma_addr_offset = 0 - tile_blk_size; 300 } 301 break; 302 case ROTATION_ANGLE_270: /* 270 degree rotation */ 303 row_height = 256; 304 if (h_mirror_en) { 305 patched_viewport_height = viewport_c_height; 306 patched_viewport_width = viewport_c_width + row_height; 307 hubp21->PLAT_54186_wa_chroma_addr_offset = 0 - tile_blk_size; 308 } else { 309 patched_viewport_height = viewport_c_height; 310 patched_viewport_width = viewport_c_width + row_height; 311 hubp21->PLAT_54186_wa_chroma_addr_offset = 0; 312 } 313 break; 314 default: 315 ASSERT(0); 316 break; 317 } 318 319 /* catch cases where viewport keep growing */ 320 ASSERT(patched_viewport_height && patched_viewport_height < 5000); 321 ASSERT(patched_viewport_width && patched_viewport_width < 5000); 322 323 REG_UPDATE_2(DCSURF_PRI_VIEWPORT_DIMENSION_C, 324 PRI_VIEWPORT_WIDTH_C, patched_viewport_width, 325 PRI_VIEWPORT_HEIGHT_C, patched_viewport_height); 326 } 327 328 void hubp21_set_vm_system_aperture_settings(struct hubp *hubp, 329 struct vm_system_aperture_param *apt) 330 { 331 struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 332 333 PHYSICAL_ADDRESS_LOC mc_vm_apt_default __unused; 334 PHYSICAL_ADDRESS_LOC mc_vm_apt_low; 335 PHYSICAL_ADDRESS_LOC mc_vm_apt_high; 336 337 // The format of default addr is 48:12 of the 48 bit addr 338 mc_vm_apt_default.quad_part = apt->sys_default.quad_part >> 12; 339 340 // The format of high/low are 48:18 of the 48 bit addr 341 mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 18; 342 mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 18; 343 344 REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0, 345 MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.quad_part); 346 347 REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0, 348 MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.quad_part); 349 350 REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0, 351 ENABLE_L1_TLB, 1, 352 SYSTEM_ACCESS_MODE, 0x3); 353 } 354 355 void hubp21_validate_dml_output(struct hubp *hubp, 356 struct dc_context *ctx, 357 struct _vcs_dpi_display_rq_regs_st *dml_rq_regs, 358 struct _vcs_dpi_display_dlg_regs_st *dml_dlg_attr, 359 struct _vcs_dpi_display_ttu_regs_st *dml_ttu_attr) 360 { 361 struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 362 struct _vcs_dpi_display_rq_regs_st rq_regs = {0}; 363 struct _vcs_dpi_display_dlg_regs_st dlg_attr = {0}; 364 struct _vcs_dpi_display_ttu_regs_st ttu_attr = {0}; 365 DC_LOGGER_INIT(ctx->logger); 366 DC_LOG_DEBUG("DML Validation | Running Validation"); 367 368 /* Requester - Per hubp */ 369 REG_GET(HUBPRET_CONTROL, 370 DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs.plane1_base_address); 371 REG_GET_4(DCN_EXPANSION_MODE, 372 DRQ_EXPANSION_MODE, &rq_regs.drq_expansion_mode, 373 PRQ_EXPANSION_MODE, &rq_regs.prq_expansion_mode, 374 MRQ_EXPANSION_MODE, &rq_regs.mrq_expansion_mode, 375 CRQ_EXPANSION_MODE, &rq_regs.crq_expansion_mode); 376 REG_GET_8(DCHUBP_REQ_SIZE_CONFIG, 377 CHUNK_SIZE, &rq_regs.rq_regs_l.chunk_size, 378 MIN_CHUNK_SIZE, &rq_regs.rq_regs_l.min_chunk_size, 379 META_CHUNK_SIZE, &rq_regs.rq_regs_l.meta_chunk_size, 380 MIN_META_CHUNK_SIZE, &rq_regs.rq_regs_l.min_meta_chunk_size, 381 DPTE_GROUP_SIZE, &rq_regs.rq_regs_l.dpte_group_size, 382 VM_GROUP_SIZE, &rq_regs.rq_regs_l.mpte_group_size, 383 SWATH_HEIGHT, &rq_regs.rq_regs_l.swath_height, 384 PTE_ROW_HEIGHT_LINEAR, &rq_regs.rq_regs_l.pte_row_height_linear); 385 REG_GET_7(DCHUBP_REQ_SIZE_CONFIG_C, 386 CHUNK_SIZE_C, &rq_regs.rq_regs_c.chunk_size, 387 MIN_CHUNK_SIZE_C, &rq_regs.rq_regs_c.min_chunk_size, 388 META_CHUNK_SIZE_C, &rq_regs.rq_regs_c.meta_chunk_size, 389 MIN_META_CHUNK_SIZE_C, &rq_regs.rq_regs_c.min_meta_chunk_size, 390 DPTE_GROUP_SIZE_C, &rq_regs.rq_regs_c.dpte_group_size, 391 SWATH_HEIGHT_C, &rq_regs.rq_regs_c.swath_height, 392 PTE_ROW_HEIGHT_LINEAR_C, &rq_regs.rq_regs_c.pte_row_height_linear); 393 394 if (rq_regs.plane1_base_address != dml_rq_regs->plane1_base_address) 395 DC_LOG_DEBUG("DML Validation | HUBPRET_CONTROL:DET_BUF_PLANE1_BASE_ADDRESS - Expected: %u Actual: %u\n", 396 dml_rq_regs->plane1_base_address, rq_regs.plane1_base_address); 397 if (rq_regs.drq_expansion_mode != dml_rq_regs->drq_expansion_mode) 398 DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:DRQ_EXPANSION_MODE - Expected: %u Actual: %u\n", 399 dml_rq_regs->drq_expansion_mode, rq_regs.drq_expansion_mode); 400 if (rq_regs.prq_expansion_mode != dml_rq_regs->prq_expansion_mode) 401 DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:MRQ_EXPANSION_MODE - Expected: %u Actual: %u\n", 402 dml_rq_regs->prq_expansion_mode, rq_regs.prq_expansion_mode); 403 if (rq_regs.mrq_expansion_mode != dml_rq_regs->mrq_expansion_mode) 404 DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:DET_BUF_PLANE1_BASE_ADDRESS - Expected: %u Actual: %u\n", 405 dml_rq_regs->mrq_expansion_mode, rq_regs.mrq_expansion_mode); 406 if (rq_regs.crq_expansion_mode != dml_rq_regs->crq_expansion_mode) 407 DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:CRQ_EXPANSION_MODE - Expected: %u Actual: %u\n", 408 dml_rq_regs->crq_expansion_mode, rq_regs.crq_expansion_mode); 409 410 if (rq_regs.rq_regs_l.chunk_size != dml_rq_regs->rq_regs_l.chunk_size) 411 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:CHUNK_SIZE - Expected: %u Actual: %u\n", 412 dml_rq_regs->rq_regs_l.chunk_size, rq_regs.rq_regs_l.chunk_size); 413 if (rq_regs.rq_regs_l.min_chunk_size != dml_rq_regs->rq_regs_l.min_chunk_size) 414 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MIN_CHUNK_SIZE - Expected: %u Actual: %u\n", 415 dml_rq_regs->rq_regs_l.min_chunk_size, rq_regs.rq_regs_l.min_chunk_size); 416 if (rq_regs.rq_regs_l.meta_chunk_size != dml_rq_regs->rq_regs_l.meta_chunk_size) 417 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:META_CHUNK_SIZE - Expected: %u Actual: %u\n", 418 dml_rq_regs->rq_regs_l.meta_chunk_size, rq_regs.rq_regs_l.meta_chunk_size); 419 if (rq_regs.rq_regs_l.min_meta_chunk_size != dml_rq_regs->rq_regs_l.min_meta_chunk_size) 420 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MIN_META_CHUNK_SIZE - Expected: %u Actual: %u\n", 421 dml_rq_regs->rq_regs_l.min_meta_chunk_size, rq_regs.rq_regs_l.min_meta_chunk_size); 422 if (rq_regs.rq_regs_l.dpte_group_size != dml_rq_regs->rq_regs_l.dpte_group_size) 423 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:DPTE_GROUP_SIZE - Expected: %u Actual: %u\n", 424 dml_rq_regs->rq_regs_l.dpte_group_size, rq_regs.rq_regs_l.dpte_group_size); 425 if (rq_regs.rq_regs_l.mpte_group_size != dml_rq_regs->rq_regs_l.mpte_group_size) 426 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:VM_GROUP_SIZE - Expected: %u Actual: %u\n", 427 dml_rq_regs->rq_regs_l.mpte_group_size, rq_regs.rq_regs_l.mpte_group_size); 428 if (rq_regs.rq_regs_l.swath_height != dml_rq_regs->rq_regs_l.swath_height) 429 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:SWATH_HEIGHT - Expected: %u Actual: %u\n", 430 dml_rq_regs->rq_regs_l.swath_height, rq_regs.rq_regs_l.swath_height); 431 if (rq_regs.rq_regs_l.pte_row_height_linear != dml_rq_regs->rq_regs_l.pte_row_height_linear) 432 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:PTE_ROW_HEIGHT_LINEAR - Expected: %u Actual: %u\n", 433 dml_rq_regs->rq_regs_l.pte_row_height_linear, rq_regs.rq_regs_l.pte_row_height_linear); 434 435 if (rq_regs.rq_regs_c.chunk_size != dml_rq_regs->rq_regs_c.chunk_size) 436 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:CHUNK_SIZE_C - Expected: %u Actual: %u\n", 437 dml_rq_regs->rq_regs_c.chunk_size, rq_regs.rq_regs_c.chunk_size); 438 if (rq_regs.rq_regs_c.min_chunk_size != dml_rq_regs->rq_regs_c.min_chunk_size) 439 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MIN_CHUNK_SIZE_C - Expected: %u Actual: %u\n", 440 dml_rq_regs->rq_regs_c.min_chunk_size, rq_regs.rq_regs_c.min_chunk_size); 441 if (rq_regs.rq_regs_c.meta_chunk_size != dml_rq_regs->rq_regs_c.meta_chunk_size) 442 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:META_CHUNK_SIZE_C - Expected: %u Actual: %u\n", 443 dml_rq_regs->rq_regs_c.meta_chunk_size, rq_regs.rq_regs_c.meta_chunk_size); 444 if (rq_regs.rq_regs_c.min_meta_chunk_size != dml_rq_regs->rq_regs_c.min_meta_chunk_size) 445 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MIN_META_CHUNK_SIZE_C - Expected: %u Actual: %u\n", 446 dml_rq_regs->rq_regs_c.min_meta_chunk_size, rq_regs.rq_regs_c.min_meta_chunk_size); 447 if (rq_regs.rq_regs_c.dpte_group_size != dml_rq_regs->rq_regs_c.dpte_group_size) 448 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:DPTE_GROUP_SIZE_C - Expected: %u Actual: %u\n", 449 dml_rq_regs->rq_regs_c.dpte_group_size, rq_regs.rq_regs_c.dpte_group_size); 450 if (rq_regs.rq_regs_c.swath_height != dml_rq_regs->rq_regs_c.swath_height) 451 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:SWATH_HEIGHT_C - Expected: %u Actual: %u\n", 452 dml_rq_regs->rq_regs_c.swath_height, rq_regs.rq_regs_c.swath_height); 453 if (rq_regs.rq_regs_c.pte_row_height_linear != dml_rq_regs->rq_regs_c.pte_row_height_linear) 454 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:PTE_ROW_HEIGHT_LINEAR_C - Expected: %u Actual: %u\n", 455 dml_rq_regs->rq_regs_c.pte_row_height_linear, rq_regs.rq_regs_c.pte_row_height_linear); 456 457 458 /* DLG - Per hubp */ 459 REG_GET_2(BLANK_OFFSET_0, 460 REFCYC_H_BLANK_END, &dlg_attr.refcyc_h_blank_end, 461 DLG_V_BLANK_END, &dlg_attr.dlg_vblank_end); 462 REG_GET(BLANK_OFFSET_1, 463 MIN_DST_Y_NEXT_START, &dlg_attr.min_dst_y_next_start); 464 REG_GET(DST_DIMENSIONS, 465 REFCYC_PER_HTOTAL, &dlg_attr.refcyc_per_htotal); 466 REG_GET_2(DST_AFTER_SCALER, 467 REFCYC_X_AFTER_SCALER, &dlg_attr.refcyc_x_after_scaler, 468 DST_Y_AFTER_SCALER, &dlg_attr.dst_y_after_scaler); 469 REG_GET(REF_FREQ_TO_PIX_FREQ, 470 REF_FREQ_TO_PIX_FREQ, &dlg_attr.ref_freq_to_pix_freq); 471 472 if (dlg_attr.refcyc_h_blank_end != dml_dlg_attr->refcyc_h_blank_end) 473 DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_0:REFCYC_H_BLANK_END - Expected: %u Actual: %u\n", 474 dml_dlg_attr->refcyc_h_blank_end, dlg_attr.refcyc_h_blank_end); 475 if (dlg_attr.dlg_vblank_end != dml_dlg_attr->dlg_vblank_end) 476 DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_0:DLG_V_BLANK_END - Expected: %u Actual: %u\n", 477 dml_dlg_attr->dlg_vblank_end, dlg_attr.dlg_vblank_end); 478 if (dlg_attr.min_dst_y_next_start != dml_dlg_attr->min_dst_y_next_start) 479 DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_1:MIN_DST_Y_NEXT_START - Expected: %u Actual: %u\n", 480 dml_dlg_attr->min_dst_y_next_start, dlg_attr.min_dst_y_next_start); 481 if (dlg_attr.refcyc_per_htotal != dml_dlg_attr->refcyc_per_htotal) 482 DC_LOG_DEBUG("DML Validation | DST_DIMENSIONS:REFCYC_PER_HTOTAL - Expected: %u Actual: %u\n", 483 dml_dlg_attr->refcyc_per_htotal, dlg_attr.refcyc_per_htotal); 484 if (dlg_attr.refcyc_x_after_scaler != dml_dlg_attr->refcyc_x_after_scaler) 485 DC_LOG_DEBUG("DML Validation | DST_AFTER_SCALER:REFCYC_X_AFTER_SCALER - Expected: %u Actual: %u\n", 486 dml_dlg_attr->refcyc_x_after_scaler, dlg_attr.refcyc_x_after_scaler); 487 if (dlg_attr.dst_y_after_scaler != dml_dlg_attr->dst_y_after_scaler) 488 DC_LOG_DEBUG("DML Validation | DST_AFTER_SCALER:DST_Y_AFTER_SCALER - Expected: %u Actual: %u\n", 489 dml_dlg_attr->dst_y_after_scaler, dlg_attr.dst_y_after_scaler); 490 if (dlg_attr.ref_freq_to_pix_freq != dml_dlg_attr->ref_freq_to_pix_freq) 491 DC_LOG_DEBUG("DML Validation | REF_FREQ_TO_PIX_FREQ:REF_FREQ_TO_PIX_FREQ - Expected: %u Actual: %u\n", 492 dml_dlg_attr->ref_freq_to_pix_freq, dlg_attr.ref_freq_to_pix_freq); 493 494 /* DLG - Per luma/chroma */ 495 REG_GET(VBLANK_PARAMETERS_1, 496 REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr.refcyc_per_pte_group_vblank_l); 497 if (REG(NOM_PARAMETERS_0)) 498 REG_GET(NOM_PARAMETERS_0, 499 DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr.dst_y_per_pte_row_nom_l); 500 if (REG(NOM_PARAMETERS_1)) 501 REG_GET(NOM_PARAMETERS_1, 502 REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr.refcyc_per_pte_group_nom_l); 503 REG_GET(NOM_PARAMETERS_4, 504 DST_Y_PER_META_ROW_NOM_L, &dlg_attr.dst_y_per_meta_row_nom_l); 505 REG_GET(NOM_PARAMETERS_5, 506 REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr.refcyc_per_meta_chunk_nom_l); 507 REG_GET_2(PER_LINE_DELIVERY, 508 REFCYC_PER_LINE_DELIVERY_L, &dlg_attr.refcyc_per_line_delivery_l, 509 REFCYC_PER_LINE_DELIVERY_C, &dlg_attr.refcyc_per_line_delivery_c); 510 REG_GET_2(PER_LINE_DELIVERY_PRE, 511 REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr.refcyc_per_line_delivery_pre_l, 512 REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr.refcyc_per_line_delivery_pre_c); 513 REG_GET(VBLANK_PARAMETERS_2, 514 REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr.refcyc_per_pte_group_vblank_c); 515 if (REG(NOM_PARAMETERS_2)) 516 REG_GET(NOM_PARAMETERS_2, 517 DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr.dst_y_per_pte_row_nom_c); 518 if (REG(NOM_PARAMETERS_3)) 519 REG_GET(NOM_PARAMETERS_3, 520 REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr.refcyc_per_pte_group_nom_c); 521 REG_GET(NOM_PARAMETERS_6, 522 DST_Y_PER_META_ROW_NOM_C, &dlg_attr.dst_y_per_meta_row_nom_c); 523 REG_GET(NOM_PARAMETERS_7, 524 REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr.refcyc_per_meta_chunk_nom_c); 525 REG_GET(VBLANK_PARAMETERS_3, 526 REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr.refcyc_per_meta_chunk_vblank_l); 527 REG_GET(VBLANK_PARAMETERS_4, 528 REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr.refcyc_per_meta_chunk_vblank_c); 529 530 if (dlg_attr.refcyc_per_pte_group_vblank_l != dml_dlg_attr->refcyc_per_pte_group_vblank_l) 531 DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_1:REFCYC_PER_PTE_GROUP_VBLANK_L - Expected: %u Actual: %u\n", 532 dml_dlg_attr->refcyc_per_pte_group_vblank_l, dlg_attr.refcyc_per_pte_group_vblank_l); 533 if (dlg_attr.dst_y_per_pte_row_nom_l != dml_dlg_attr->dst_y_per_pte_row_nom_l) 534 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_0:DST_Y_PER_PTE_ROW_NOM_L - Expected: %u Actual: %u\n", 535 dml_dlg_attr->dst_y_per_pte_row_nom_l, dlg_attr.dst_y_per_pte_row_nom_l); 536 if (dlg_attr.refcyc_per_pte_group_nom_l != dml_dlg_attr->refcyc_per_pte_group_nom_l) 537 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_1:REFCYC_PER_PTE_GROUP_NOM_L - Expected: %u Actual: %u\n", 538 dml_dlg_attr->refcyc_per_pte_group_nom_l, dlg_attr.refcyc_per_pte_group_nom_l); 539 if (dlg_attr.dst_y_per_meta_row_nom_l != dml_dlg_attr->dst_y_per_meta_row_nom_l) 540 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_4:DST_Y_PER_META_ROW_NOM_L - Expected: %u Actual: %u\n", 541 dml_dlg_attr->dst_y_per_meta_row_nom_l, dlg_attr.dst_y_per_meta_row_nom_l); 542 if (dlg_attr.refcyc_per_meta_chunk_nom_l != dml_dlg_attr->refcyc_per_meta_chunk_nom_l) 543 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_5:REFCYC_PER_META_CHUNK_NOM_L - Expected: %u Actual: %u\n", 544 dml_dlg_attr->refcyc_per_meta_chunk_nom_l, dlg_attr.refcyc_per_meta_chunk_nom_l); 545 if (dlg_attr.refcyc_per_line_delivery_l != dml_dlg_attr->refcyc_per_line_delivery_l) 546 DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY:REFCYC_PER_LINE_DELIVERY_L - Expected: %u Actual: %u\n", 547 dml_dlg_attr->refcyc_per_line_delivery_l, dlg_attr.refcyc_per_line_delivery_l); 548 if (dlg_attr.refcyc_per_line_delivery_c != dml_dlg_attr->refcyc_per_line_delivery_c) 549 DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY:REFCYC_PER_LINE_DELIVERY_C - Expected: %u Actual: %u\n", 550 dml_dlg_attr->refcyc_per_line_delivery_c, dlg_attr.refcyc_per_line_delivery_c); 551 if (dlg_attr.refcyc_per_pte_group_vblank_c != dml_dlg_attr->refcyc_per_pte_group_vblank_c) 552 DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_2:REFCYC_PER_PTE_GROUP_VBLANK_C - Expected: %u Actual: %u\n", 553 dml_dlg_attr->refcyc_per_pte_group_vblank_c, dlg_attr.refcyc_per_pte_group_vblank_c); 554 if (dlg_attr.dst_y_per_pte_row_nom_c != dml_dlg_attr->dst_y_per_pte_row_nom_c) 555 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_2:DST_Y_PER_PTE_ROW_NOM_C - Expected: %u Actual: %u\n", 556 dml_dlg_attr->dst_y_per_pte_row_nom_c, dlg_attr.dst_y_per_pte_row_nom_c); 557 if (dlg_attr.refcyc_per_pte_group_nom_c != dml_dlg_attr->refcyc_per_pte_group_nom_c) 558 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_3:REFCYC_PER_PTE_GROUP_NOM_C - Expected: %u Actual: %u\n", 559 dml_dlg_attr->refcyc_per_pte_group_nom_c, dlg_attr.refcyc_per_pte_group_nom_c); 560 if (dlg_attr.dst_y_per_meta_row_nom_c != dml_dlg_attr->dst_y_per_meta_row_nom_c) 561 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_6:DST_Y_PER_META_ROW_NOM_C - Expected: %u Actual: %u\n", 562 dml_dlg_attr->dst_y_per_meta_row_nom_c, dlg_attr.dst_y_per_meta_row_nom_c); 563 if (dlg_attr.refcyc_per_meta_chunk_nom_c != dml_dlg_attr->refcyc_per_meta_chunk_nom_c) 564 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_7:REFCYC_PER_META_CHUNK_NOM_C - Expected: %u Actual: %u\n", 565 dml_dlg_attr->refcyc_per_meta_chunk_nom_c, dlg_attr.refcyc_per_meta_chunk_nom_c); 566 if (dlg_attr.refcyc_per_line_delivery_pre_l != dml_dlg_attr->refcyc_per_line_delivery_pre_l) 567 DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY_PRE:REFCYC_PER_LINE_DELIVERY_PRE_L - Expected: %u Actual: %u\n", 568 dml_dlg_attr->refcyc_per_line_delivery_pre_l, dlg_attr.refcyc_per_line_delivery_pre_l); 569 if (dlg_attr.refcyc_per_line_delivery_pre_c != dml_dlg_attr->refcyc_per_line_delivery_pre_c) 570 DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY_PRE:REFCYC_PER_LINE_DELIVERY_PRE_C - Expected: %u Actual: %u\n", 571 dml_dlg_attr->refcyc_per_line_delivery_pre_c, dlg_attr.refcyc_per_line_delivery_pre_c); 572 if (dlg_attr.refcyc_per_meta_chunk_vblank_l != dml_dlg_attr->refcyc_per_meta_chunk_vblank_l) 573 DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_3:REFCYC_PER_META_CHUNK_VBLANK_L - Expected: %u Actual: %u\n", 574 dml_dlg_attr->refcyc_per_meta_chunk_vblank_l, dlg_attr.refcyc_per_meta_chunk_vblank_l); 575 if (dlg_attr.refcyc_per_meta_chunk_vblank_c != dml_dlg_attr->refcyc_per_meta_chunk_vblank_c) 576 DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_4:REFCYC_PER_META_CHUNK_VBLANK_C - Expected: %u Actual: %u\n", 577 dml_dlg_attr->refcyc_per_meta_chunk_vblank_c, dlg_attr.refcyc_per_meta_chunk_vblank_c); 578 579 /* TTU - per hubp */ 580 REG_GET_2(DCN_TTU_QOS_WM, 581 QoS_LEVEL_LOW_WM, &ttu_attr.qos_level_low_wm, 582 QoS_LEVEL_HIGH_WM, &ttu_attr.qos_level_high_wm); 583 584 if (ttu_attr.qos_level_low_wm != dml_ttu_attr->qos_level_low_wm) 585 DC_LOG_DEBUG("DML Validation | DCN_TTU_QOS_WM:QoS_LEVEL_LOW_WM - Expected: %u Actual: %u\n", 586 dml_ttu_attr->qos_level_low_wm, ttu_attr.qos_level_low_wm); 587 if (ttu_attr.qos_level_high_wm != dml_ttu_attr->qos_level_high_wm) 588 DC_LOG_DEBUG("DML Validation | DCN_TTU_QOS_WM:QoS_LEVEL_HIGH_WM - Expected: %u Actual: %u\n", 589 dml_ttu_attr->qos_level_high_wm, ttu_attr.qos_level_high_wm); 590 591 /* TTU - per luma/chroma */ 592 /* Assumed surf0 is luma and 1 is chroma */ 593 REG_GET_3(DCN_SURF0_TTU_CNTL0, 594 REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_l, 595 QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_l, 596 QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_l); 597 REG_GET_3(DCN_SURF1_TTU_CNTL0, 598 REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_c, 599 QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_c, 600 QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_c); 601 REG_GET_3(DCN_CUR0_TTU_CNTL0, 602 REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_cur0, 603 QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_cur0, 604 QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_cur0); 605 REG_GET(FLIP_PARAMETERS_1, 606 REFCYC_PER_PTE_GROUP_FLIP_L, &dlg_attr.refcyc_per_pte_group_flip_l); 607 REG_GET(DCN_CUR0_TTU_CNTL1, 608 REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_cur0); 609 REG_GET(DCN_CUR1_TTU_CNTL1, 610 REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_cur1); 611 REG_GET(DCN_SURF0_TTU_CNTL1, 612 REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_l); 613 REG_GET(DCN_SURF1_TTU_CNTL1, 614 REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_c); 615 616 if (ttu_attr.refcyc_per_req_delivery_l != dml_ttu_attr->refcyc_per_req_delivery_l) 617 DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n", 618 dml_ttu_attr->refcyc_per_req_delivery_l, ttu_attr.refcyc_per_req_delivery_l); 619 if (ttu_attr.qos_level_fixed_l != dml_ttu_attr->qos_level_fixed_l) 620 DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n", 621 dml_ttu_attr->qos_level_fixed_l, ttu_attr.qos_level_fixed_l); 622 if (ttu_attr.qos_ramp_disable_l != dml_ttu_attr->qos_ramp_disable_l) 623 DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n", 624 dml_ttu_attr->qos_ramp_disable_l, ttu_attr.qos_ramp_disable_l); 625 if (ttu_attr.refcyc_per_req_delivery_c != dml_ttu_attr->refcyc_per_req_delivery_c) 626 DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n", 627 dml_ttu_attr->refcyc_per_req_delivery_c, ttu_attr.refcyc_per_req_delivery_c); 628 if (ttu_attr.qos_level_fixed_c != dml_ttu_attr->qos_level_fixed_c) 629 DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n", 630 dml_ttu_attr->qos_level_fixed_c, ttu_attr.qos_level_fixed_c); 631 if (ttu_attr.qos_ramp_disable_c != dml_ttu_attr->qos_ramp_disable_c) 632 DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n", 633 dml_ttu_attr->qos_ramp_disable_c, ttu_attr.qos_ramp_disable_c); 634 if (ttu_attr.refcyc_per_req_delivery_cur0 != dml_ttu_attr->refcyc_per_req_delivery_cur0) 635 DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n", 636 dml_ttu_attr->refcyc_per_req_delivery_cur0, ttu_attr.refcyc_per_req_delivery_cur0); 637 if (ttu_attr.qos_level_fixed_cur0 != dml_ttu_attr->qos_level_fixed_cur0) 638 DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n", 639 dml_ttu_attr->qos_level_fixed_cur0, ttu_attr.qos_level_fixed_cur0); 640 if (ttu_attr.qos_ramp_disable_cur0 != dml_ttu_attr->qos_ramp_disable_cur0) 641 DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n", 642 dml_ttu_attr->qos_ramp_disable_cur0, ttu_attr.qos_ramp_disable_cur0); 643 if (dlg_attr.refcyc_per_pte_group_flip_l != dml_dlg_attr->refcyc_per_pte_group_flip_l) 644 DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_1:REFCYC_PER_PTE_GROUP_FLIP_L - Expected: %u Actual: %u\n", 645 dml_dlg_attr->refcyc_per_pte_group_flip_l, dlg_attr.refcyc_per_pte_group_flip_l); 646 if (ttu_attr.refcyc_per_req_delivery_pre_cur0 != dml_ttu_attr->refcyc_per_req_delivery_pre_cur0) 647 DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", 648 dml_ttu_attr->refcyc_per_req_delivery_pre_cur0, ttu_attr.refcyc_per_req_delivery_pre_cur0); 649 if (ttu_attr.refcyc_per_req_delivery_pre_cur1 != dml_ttu_attr->refcyc_per_req_delivery_pre_cur1) 650 DC_LOG_DEBUG("DML Validation | DCN_CUR1_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", 651 dml_ttu_attr->refcyc_per_req_delivery_pre_cur1, ttu_attr.refcyc_per_req_delivery_pre_cur1); 652 if (ttu_attr.refcyc_per_req_delivery_pre_l != dml_ttu_attr->refcyc_per_req_delivery_pre_l) 653 DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", 654 dml_ttu_attr->refcyc_per_req_delivery_pre_l, ttu_attr.refcyc_per_req_delivery_pre_l); 655 if (ttu_attr.refcyc_per_req_delivery_pre_c != dml_ttu_attr->refcyc_per_req_delivery_pre_c) 656 DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", 657 dml_ttu_attr->refcyc_per_req_delivery_pre_c, ttu_attr.refcyc_per_req_delivery_pre_c); 658 659 /* Host VM deadline regs */ 660 REG_GET(VBLANK_PARAMETERS_5, 661 REFCYC_PER_VM_GROUP_VBLANK, &dlg_attr.refcyc_per_vm_group_vblank); 662 REG_GET(VBLANK_PARAMETERS_6, 663 REFCYC_PER_VM_REQ_VBLANK, &dlg_attr.refcyc_per_vm_req_vblank); 664 REG_GET(FLIP_PARAMETERS_3, 665 REFCYC_PER_VM_GROUP_FLIP, &dlg_attr.refcyc_per_vm_group_flip); 666 REG_GET(FLIP_PARAMETERS_4, 667 REFCYC_PER_VM_REQ_FLIP, &dlg_attr.refcyc_per_vm_req_flip); 668 REG_GET(FLIP_PARAMETERS_5, 669 REFCYC_PER_PTE_GROUP_FLIP_C, &dlg_attr.refcyc_per_pte_group_flip_c); 670 REG_GET(FLIP_PARAMETERS_6, 671 REFCYC_PER_META_CHUNK_FLIP_C, &dlg_attr.refcyc_per_meta_chunk_flip_c); 672 REG_GET(FLIP_PARAMETERS_2, 673 REFCYC_PER_META_CHUNK_FLIP_L, &dlg_attr.refcyc_per_meta_chunk_flip_l); 674 675 if (dlg_attr.refcyc_per_vm_group_vblank != dml_dlg_attr->refcyc_per_vm_group_vblank) 676 DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_5:REFCYC_PER_VM_GROUP_VBLANK - Expected: %u Actual: %u\n", 677 dml_dlg_attr->refcyc_per_vm_group_vblank, dlg_attr.refcyc_per_vm_group_vblank); 678 if (dlg_attr.refcyc_per_vm_req_vblank != dml_dlg_attr->refcyc_per_vm_req_vblank) 679 DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_6:REFCYC_PER_VM_REQ_VBLANK - Expected: %u Actual: %u\n", 680 dml_dlg_attr->refcyc_per_vm_req_vblank, dlg_attr.refcyc_per_vm_req_vblank); 681 if (dlg_attr.refcyc_per_vm_group_flip != dml_dlg_attr->refcyc_per_vm_group_flip) 682 DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_3:REFCYC_PER_VM_GROUP_FLIP - Expected: %u Actual: %u\n", 683 dml_dlg_attr->refcyc_per_vm_group_flip, dlg_attr.refcyc_per_vm_group_flip); 684 if (dlg_attr.refcyc_per_vm_req_flip != dml_dlg_attr->refcyc_per_vm_req_flip) 685 DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_4:REFCYC_PER_VM_REQ_FLIP - Expected: %u Actual: %u\n", 686 dml_dlg_attr->refcyc_per_vm_req_flip, dlg_attr.refcyc_per_vm_req_flip); 687 if (dlg_attr.refcyc_per_pte_group_flip_c != dml_dlg_attr->refcyc_per_pte_group_flip_c) 688 DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_5:REFCYC_PER_PTE_GROUP_FLIP_C - Expected: %u Actual: %u\n", 689 dml_dlg_attr->refcyc_per_pte_group_flip_c, dlg_attr.refcyc_per_pte_group_flip_c); 690 if (dlg_attr.refcyc_per_meta_chunk_flip_c != dml_dlg_attr->refcyc_per_meta_chunk_flip_c) 691 DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_6:REFCYC_PER_META_CHUNK_FLIP_C - Expected: %u Actual: %u\n", 692 dml_dlg_attr->refcyc_per_meta_chunk_flip_c, dlg_attr.refcyc_per_meta_chunk_flip_c); 693 if (dlg_attr.refcyc_per_meta_chunk_flip_l != dml_dlg_attr->refcyc_per_meta_chunk_flip_l) 694 DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_2:REFCYC_PER_META_CHUNK_FLIP_L - Expected: %u Actual: %u\n", 695 dml_dlg_attr->refcyc_per_meta_chunk_flip_l, dlg_attr.refcyc_per_meta_chunk_flip_l); 696 } 697 698 static void program_surface_flip_and_addr(struct hubp *hubp, struct surface_flip_registers *flip_regs) 699 { 700 struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 701 702 REG_UPDATE_3(DCSURF_FLIP_CONTROL, 703 SURFACE_FLIP_TYPE, flip_regs->immediate, 704 SURFACE_FLIP_MODE_FOR_STEREOSYNC, flip_regs->grph_stereo, 705 SURFACE_FLIP_IN_STEREOSYNC, flip_regs->grph_stereo); 706 707 REG_UPDATE(VMID_SETTINGS_0, 708 VMID, flip_regs->vmid); 709 710 REG_UPDATE_8(DCSURF_SURFACE_CONTROL, 711 PRIMARY_SURFACE_TMZ, flip_regs->tmz_surface, 712 PRIMARY_SURFACE_TMZ_C, flip_regs->tmz_surface, 713 PRIMARY_META_SURFACE_TMZ, flip_regs->tmz_surface, 714 PRIMARY_META_SURFACE_TMZ_C, flip_regs->tmz_surface, 715 SECONDARY_SURFACE_TMZ, flip_regs->tmz_surface, 716 SECONDARY_SURFACE_TMZ_C, flip_regs->tmz_surface, 717 SECONDARY_META_SURFACE_TMZ, flip_regs->tmz_surface, 718 SECONDARY_META_SURFACE_TMZ_C, flip_regs->tmz_surface); 719 720 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0, 721 PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 722 flip_regs->DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C); 723 724 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0, 725 PRIMARY_META_SURFACE_ADDRESS_C, 726 flip_regs->DCSURF_PRIMARY_META_SURFACE_ADDRESS_C); 727 728 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, 729 PRIMARY_META_SURFACE_ADDRESS_HIGH, 730 flip_regs->DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH); 731 732 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, 733 PRIMARY_META_SURFACE_ADDRESS, 734 flip_regs->DCSURF_PRIMARY_META_SURFACE_ADDRESS); 735 736 REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, 0, 737 SECONDARY_META_SURFACE_ADDRESS_HIGH, 738 flip_regs->DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH); 739 740 REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS, 0, 741 SECONDARY_META_SURFACE_ADDRESS, 742 flip_regs->DCSURF_SECONDARY_META_SURFACE_ADDRESS); 743 744 745 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, 0, 746 SECONDARY_SURFACE_ADDRESS_HIGH, 747 flip_regs->DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH); 748 749 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0, 750 SECONDARY_SURFACE_ADDRESS, 751 flip_regs->DCSURF_SECONDARY_SURFACE_ADDRESS); 752 753 754 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0, 755 PRIMARY_SURFACE_ADDRESS_HIGH_C, 756 flip_regs->DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C); 757 758 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0, 759 PRIMARY_SURFACE_ADDRESS_C, 760 flip_regs->DCSURF_PRIMARY_SURFACE_ADDRESS_C); 761 762 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, 763 PRIMARY_SURFACE_ADDRESS_HIGH, 764 flip_regs->DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH); 765 766 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, 767 PRIMARY_SURFACE_ADDRESS, 768 flip_regs->DCSURF_PRIMARY_SURFACE_ADDRESS); 769 } 770 771 void dmcub_PLAT_54186_wa(struct hubp *hubp, struct surface_flip_registers *flip_regs) 772 { 773 struct dc_dmub_srv *dmcub = hubp->ctx->dmub_srv; 774 struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 775 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa = { 0 }; 776 777 PLAT_54186_wa.header.type = DMUB_CMD__PLAT_54186_WA; 778 PLAT_54186_wa.flip.DCSURF_PRIMARY_SURFACE_ADDRESS = flip_regs->DCSURF_PRIMARY_SURFACE_ADDRESS; 779 PLAT_54186_wa.flip.DCSURF_PRIMARY_SURFACE_ADDRESS_C = flip_regs->DCSURF_PRIMARY_SURFACE_ADDRESS_C; 780 PLAT_54186_wa.flip.DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH = flip_regs->DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; 781 PLAT_54186_wa.flip.DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C = flip_regs->DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; 782 PLAT_54186_wa.flip.flip_params.grph_stereo = flip_regs->grph_stereo; 783 PLAT_54186_wa.flip.flip_params.hubp_inst = hubp->inst; 784 PLAT_54186_wa.flip.flip_params.immediate = flip_regs->immediate; 785 PLAT_54186_wa.flip.flip_params.tmz_surface = flip_regs->tmz_surface; 786 PLAT_54186_wa.flip.flip_params.vmid = flip_regs->vmid; 787 788 PERF_TRACE(); // TODO: remove after performance is stable. 789 dc_dmub_srv_cmd_queue(dmcub, &PLAT_54186_wa.header); 790 PERF_TRACE(); // TODO: remove after performance is stable. 791 dc_dmub_srv_cmd_execute(dmcub); 792 PERF_TRACE(); // TODO: remove after performance is stable. 793 dc_dmub_srv_wait_idle(dmcub); 794 PERF_TRACE(); // TODO: remove after performance is stable. 795 } 796 797 bool hubp21_program_surface_flip_and_addr( 798 struct hubp *hubp, 799 const struct dc_plane_address *address, 800 bool flip_immediate) 801 { 802 struct dc_debug_options *debug = &hubp->ctx->dc->debug; 803 struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 804 struct surface_flip_registers flip_regs = { 0 }; 805 806 flip_regs.vmid = address->vmid; 807 808 switch (address->type) { 809 case PLN_ADDR_TYPE_GRAPHICS: 810 if (address->grph.addr.quad_part == 0) { 811 BREAK_TO_DEBUGGER(); 812 break; 813 } 814 815 if (address->grph.meta_addr.quad_part != 0) { 816 flip_regs.DCSURF_PRIMARY_META_SURFACE_ADDRESS = 817 address->grph.meta_addr.low_part; 818 flip_regs.DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH = 819 address->grph.meta_addr.high_part; 820 } 821 822 flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS = 823 address->grph.addr.low_part; 824 flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH = 825 address->grph.addr.high_part; 826 break; 827 case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE: 828 if (address->video_progressive.luma_addr.quad_part == 0 829 || address->video_progressive.chroma_addr.quad_part == 0) 830 break; 831 832 if (address->video_progressive.luma_meta_addr.quad_part != 0) { 833 flip_regs.DCSURF_PRIMARY_META_SURFACE_ADDRESS = 834 address->video_progressive.luma_meta_addr.low_part; 835 flip_regs.DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH = 836 address->video_progressive.luma_meta_addr.high_part; 837 838 flip_regs.DCSURF_PRIMARY_META_SURFACE_ADDRESS_C = 839 address->video_progressive.chroma_meta_addr.low_part; 840 flip_regs.DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C = 841 address->video_progressive.chroma_meta_addr.high_part; 842 } 843 844 flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS = 845 address->video_progressive.luma_addr.low_part; 846 flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH = 847 address->video_progressive.luma_addr.high_part; 848 849 if (debug->nv12_iflip_vm_wa) { 850 flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS_C = 851 address->video_progressive.chroma_addr.low_part + hubp21->PLAT_54186_wa_chroma_addr_offset; 852 } else 853 flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS_C = 854 address->video_progressive.chroma_addr.low_part; 855 856 flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C = 857 address->video_progressive.chroma_addr.high_part; 858 859 break; 860 case PLN_ADDR_TYPE_GRPH_STEREO: 861 if (address->grph_stereo.left_addr.quad_part == 0) 862 break; 863 if (address->grph_stereo.right_addr.quad_part == 0) 864 break; 865 866 flip_regs.grph_stereo = true; 867 868 if (address->grph_stereo.right_meta_addr.quad_part != 0) { 869 flip_regs.DCSURF_SECONDARY_META_SURFACE_ADDRESS = 870 address->grph_stereo.right_meta_addr.low_part; 871 flip_regs.DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH = 872 address->grph_stereo.right_meta_addr.high_part; 873 } 874 875 if (address->grph_stereo.left_meta_addr.quad_part != 0) { 876 flip_regs.DCSURF_PRIMARY_META_SURFACE_ADDRESS = 877 address->grph_stereo.left_meta_addr.low_part; 878 flip_regs.DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH = 879 address->grph_stereo.left_meta_addr.high_part; 880 } 881 882 flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS = 883 address->grph_stereo.left_addr.low_part; 884 flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH = 885 address->grph_stereo.left_addr.high_part; 886 887 flip_regs.DCSURF_SECONDARY_SURFACE_ADDRESS = 888 address->grph_stereo.right_addr.low_part; 889 flip_regs.DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH = 890 address->grph_stereo.right_addr.high_part; 891 892 break; 893 default: 894 BREAK_TO_DEBUGGER(); 895 break; 896 } 897 898 flip_regs.tmz_surface = address->tmz_surface; 899 flip_regs.immediate = flip_immediate; 900 901 if (hubp->ctx->dc->debug.enable_dmcub_surface_flip && address->type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE) 902 dmcub_PLAT_54186_wa(hubp, &flip_regs); 903 else 904 program_surface_flip_and_addr(hubp, &flip_regs); 905 906 hubp->request_address = *address; 907 908 return true; 909 } 910 911 void hubp21_init(struct hubp *hubp) 912 { 913 // DEDCN21-133: Inconsistent row starting line for flip between DPTE and Meta 914 // This is a chicken bit to enable the ECO fix. 915 916 struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 917 //hubp[i].HUBPREQ_DEBUG.HUBPREQ_DEBUG[26] = 1; 918 REG_WRITE(HUBPREQ_DEBUG, 1 << 26); 919 } 920 static struct hubp_funcs dcn21_hubp_funcs = { 921 .hubp_enable_tripleBuffer = hubp2_enable_triplebuffer, 922 .hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled, 923 .hubp_program_surface_flip_and_addr = hubp21_program_surface_flip_and_addr, 924 .hubp_program_surface_config = hubp1_program_surface_config, 925 .hubp_is_flip_pending = hubp1_is_flip_pending, 926 .hubp_setup = hubp21_setup, 927 .hubp_setup_interdependent = hubp2_setup_interdependent, 928 .hubp_set_vm_system_aperture_settings = hubp21_set_vm_system_aperture_settings, 929 .set_blank = hubp1_set_blank, 930 .dcc_control = hubp1_dcc_control, 931 .mem_program_viewport = hubp21_set_viewport, 932 .apply_PLAT_54186_wa = hubp21_apply_PLAT_54186_wa, 933 .set_cursor_attributes = hubp2_cursor_set_attributes, 934 .set_cursor_position = hubp1_cursor_set_position, 935 .hubp_clk_cntl = hubp1_clk_cntl, 936 .hubp_vtg_sel = hubp1_vtg_sel, 937 .dmdata_set_attributes = hubp2_dmdata_set_attributes, 938 .dmdata_load = hubp2_dmdata_load, 939 .dmdata_status_done = hubp2_dmdata_status_done, 940 .hubp_read_state = hubp1_read_state, 941 .hubp_clear_underflow = hubp1_clear_underflow, 942 .hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl, 943 .hubp_init = hubp21_init, 944 .validate_dml_output = hubp21_validate_dml_output, 945 }; 946 947 bool hubp21_construct( 948 struct dcn21_hubp *hubp21, 949 struct dc_context *ctx, 950 uint32_t inst, 951 const struct dcn_hubp2_registers *hubp_regs, 952 const struct dcn_hubp2_shift *hubp_shift, 953 const struct dcn_hubp2_mask *hubp_mask) 954 { 955 hubp21->base.funcs = &dcn21_hubp_funcs; 956 hubp21->base.ctx = ctx; 957 hubp21->hubp_regs = hubp_regs; 958 hubp21->hubp_shift = hubp_shift; 959 hubp21->hubp_mask = hubp_mask; 960 hubp21->base.inst = inst; 961 hubp21->base.opp_id = OPP_ID_INVALID; 962 hubp21->base.mpcc_id = 0xf; 963 964 return true; 965 } 966
Indexes created Sat Sep 20 22:09:52 GMT 2025