1 /* $NetBSD: amdgpu_dcn20_hubp.c,v 1.2 2021/12/18 23:45:03 riastradh Exp $ */ 2 3 /* 4 * Copyright 2012-17 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: AMD 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: amdgpu_dcn20_hubp.c,v 1.2 2021/12/18 23:45:03 riastradh Exp $"); 30 31 #include "dcn20_hubp.h" 32 33 #include "dm_services.h" 34 #include "dce_calcs.h" 35 #include "reg_helper.h" 36 #include "basics/conversion.h" 37 38 #define DC_LOGGER_INIT(logger) 39 40 #define REG(reg)\ 41 hubp2->hubp_regs->reg 42 43 #define CTX \ 44 hubp2->base.ctx 45 46 #undef FN 47 #define FN(reg_name, field_name) \ 48 hubp2->hubp_shift->field_name, hubp2->hubp_mask->field_name 49 50 void hubp2_set_vm_system_aperture_settings(struct hubp *hubp, 51 struct vm_system_aperture_param *apt) 52 { 53 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 54 55 PHYSICAL_ADDRESS_LOC mc_vm_apt_default; 56 PHYSICAL_ADDRESS_LOC mc_vm_apt_low; 57 PHYSICAL_ADDRESS_LOC mc_vm_apt_high; 58 59 // The format of default addr is 48:12 of the 48 bit addr 60 mc_vm_apt_default.quad_part = apt->sys_default.quad_part >> 12; 61 62 // The format of high/low are 48:18 of the 48 bit addr 63 mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 18; 64 mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 18; 65 66 REG_UPDATE_2(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 67 DCN_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, 1, /* 1 = system physical memory */ 68 DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mc_vm_apt_default.high_part); 69 70 REG_SET(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 0, 71 DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mc_vm_apt_default.low_part); 72 73 REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0, 74 MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.quad_part); 75 76 REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0, 77 MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.quad_part); 78 79 REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0, 80 ENABLE_L1_TLB, 1, 81 SYSTEM_ACCESS_MODE, 0x3); 82 } 83 84 void hubp2_program_deadline( 85 struct hubp *hubp, 86 struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 87 struct _vcs_dpi_display_ttu_regs_st *ttu_attr) 88 { 89 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 90 91 /* DLG - Per hubp */ 92 REG_SET_2(BLANK_OFFSET_0, 0, 93 REFCYC_H_BLANK_END, dlg_attr->refcyc_h_blank_end, 94 DLG_V_BLANK_END, dlg_attr->dlg_vblank_end); 95 96 REG_SET(BLANK_OFFSET_1, 0, 97 MIN_DST_Y_NEXT_START, dlg_attr->min_dst_y_next_start); 98 99 REG_SET(DST_DIMENSIONS, 0, 100 REFCYC_PER_HTOTAL, dlg_attr->refcyc_per_htotal); 101 102 REG_SET_2(DST_AFTER_SCALER, 0, 103 REFCYC_X_AFTER_SCALER, dlg_attr->refcyc_x_after_scaler, 104 DST_Y_AFTER_SCALER, dlg_attr->dst_y_after_scaler); 105 106 REG_SET(REF_FREQ_TO_PIX_FREQ, 0, 107 REF_FREQ_TO_PIX_FREQ, dlg_attr->ref_freq_to_pix_freq); 108 109 /* DLG - Per luma/chroma */ 110 REG_SET(VBLANK_PARAMETERS_1, 0, 111 REFCYC_PER_PTE_GROUP_VBLANK_L, dlg_attr->refcyc_per_pte_group_vblank_l); 112 113 if (REG(NOM_PARAMETERS_0)) 114 REG_SET(NOM_PARAMETERS_0, 0, 115 DST_Y_PER_PTE_ROW_NOM_L, dlg_attr->dst_y_per_pte_row_nom_l); 116 117 if (REG(NOM_PARAMETERS_1)) 118 REG_SET(NOM_PARAMETERS_1, 0, 119 REFCYC_PER_PTE_GROUP_NOM_L, dlg_attr->refcyc_per_pte_group_nom_l); 120 121 REG_SET(NOM_PARAMETERS_4, 0, 122 DST_Y_PER_META_ROW_NOM_L, dlg_attr->dst_y_per_meta_row_nom_l); 123 124 REG_SET(NOM_PARAMETERS_5, 0, 125 REFCYC_PER_META_CHUNK_NOM_L, dlg_attr->refcyc_per_meta_chunk_nom_l); 126 127 REG_SET_2(PER_LINE_DELIVERY, 0, 128 REFCYC_PER_LINE_DELIVERY_L, dlg_attr->refcyc_per_line_delivery_l, 129 REFCYC_PER_LINE_DELIVERY_C, dlg_attr->refcyc_per_line_delivery_c); 130 131 REG_SET(VBLANK_PARAMETERS_2, 0, 132 REFCYC_PER_PTE_GROUP_VBLANK_C, dlg_attr->refcyc_per_pte_group_vblank_c); 133 134 if (REG(NOM_PARAMETERS_2)) 135 REG_SET(NOM_PARAMETERS_2, 0, 136 DST_Y_PER_PTE_ROW_NOM_C, dlg_attr->dst_y_per_pte_row_nom_c); 137 138 if (REG(NOM_PARAMETERS_3)) 139 REG_SET(NOM_PARAMETERS_3, 0, 140 REFCYC_PER_PTE_GROUP_NOM_C, dlg_attr->refcyc_per_pte_group_nom_c); 141 142 REG_SET(NOM_PARAMETERS_6, 0, 143 DST_Y_PER_META_ROW_NOM_C, dlg_attr->dst_y_per_meta_row_nom_c); 144 145 REG_SET(NOM_PARAMETERS_7, 0, 146 REFCYC_PER_META_CHUNK_NOM_C, dlg_attr->refcyc_per_meta_chunk_nom_c); 147 148 /* TTU - per hubp */ 149 REG_SET_2(DCN_TTU_QOS_WM, 0, 150 QoS_LEVEL_LOW_WM, ttu_attr->qos_level_low_wm, 151 QoS_LEVEL_HIGH_WM, ttu_attr->qos_level_high_wm); 152 153 /* TTU - per luma/chroma */ 154 /* Assumed surf0 is luma and 1 is chroma */ 155 156 REG_SET_3(DCN_SURF0_TTU_CNTL0, 0, 157 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_l, 158 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_l, 159 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_l); 160 161 REG_SET_3(DCN_SURF1_TTU_CNTL0, 0, 162 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_c, 163 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_c, 164 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_c); 165 166 REG_SET_3(DCN_CUR0_TTU_CNTL0, 0, 167 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_cur0, 168 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_cur0, 169 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_cur0); 170 171 REG_SET(FLIP_PARAMETERS_1, 0, 172 REFCYC_PER_PTE_GROUP_FLIP_L, dlg_attr->refcyc_per_pte_group_flip_l); 173 } 174 175 void hubp2_vready_at_or_After_vsync(struct hubp *hubp, 176 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest) 177 { 178 uint32_t value = 0; 179 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 180 /* disable_dlg_test_mode Set 9th bit to 1 to disable "dv" mode */ 181 REG_WRITE(HUBPREQ_DEBUG_DB, 1 << 8); 182 /* 183 if (VSTARTUP_START - (VREADY_OFFSET+VUPDATE_WIDTH+VUPDATE_OFFSET)/htotal) 184 <= OTG_V_BLANK_END 185 Set HUBP_VREADY_AT_OR_AFTER_VSYNC = 1 186 else 187 Set HUBP_VREADY_AT_OR_AFTER_VSYNC = 0 188 */ 189 if ((pipe_dest->vstartup_start - (pipe_dest->vready_offset+pipe_dest->vupdate_width 190 + pipe_dest->vupdate_offset) / pipe_dest->htotal) <= pipe_dest->vblank_end) { 191 value = 1; 192 } else 193 value = 0; 194 REG_UPDATE(DCHUBP_CNTL, HUBP_VREADY_AT_OR_AFTER_VSYNC, value); 195 } 196 197 void hubp2_program_requestor( 198 struct hubp *hubp, 199 struct _vcs_dpi_display_rq_regs_st *rq_regs) 200 { 201 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 202 203 REG_UPDATE(HUBPRET_CONTROL, 204 DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address); 205 REG_SET_4(DCN_EXPANSION_MODE, 0, 206 DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode, 207 PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode, 208 MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode, 209 CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode); 210 REG_SET_8(DCHUBP_REQ_SIZE_CONFIG, 0, 211 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size, 212 MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size, 213 META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size, 214 MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size, 215 DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size, 216 MPTE_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size, 217 SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height, 218 PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear); 219 REG_SET_8(DCHUBP_REQ_SIZE_CONFIG_C, 0, 220 CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size, 221 MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size, 222 META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size, 223 MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size, 224 DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size, 225 MPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.mpte_group_size, 226 SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height, 227 PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear); 228 } 229 230 static void hubp2_setup( 231 struct hubp *hubp, 232 struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 233 struct _vcs_dpi_display_ttu_regs_st *ttu_attr, 234 struct _vcs_dpi_display_rq_regs_st *rq_regs, 235 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest) 236 { 237 /* otg is locked when this func is called. Register are double buffered. 238 * disable the requestors is not needed 239 */ 240 241 hubp2_vready_at_or_After_vsync(hubp, pipe_dest); 242 hubp2_program_requestor(hubp, rq_regs); 243 hubp2_program_deadline(hubp, dlg_attr, ttu_attr); 244 245 } 246 247 void hubp2_setup_interdependent( 248 struct hubp *hubp, 249 struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 250 struct _vcs_dpi_display_ttu_regs_st *ttu_attr) 251 { 252 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 253 254 REG_SET_2(PREFETCH_SETTINGS, 0, 255 DST_Y_PREFETCH, dlg_attr->dst_y_prefetch, 256 VRATIO_PREFETCH, dlg_attr->vratio_prefetch); 257 258 REG_SET(PREFETCH_SETTINGS_C, 0, 259 VRATIO_PREFETCH_C, dlg_attr->vratio_prefetch_c); 260 261 REG_SET_2(VBLANK_PARAMETERS_0, 0, 262 DST_Y_PER_VM_VBLANK, dlg_attr->dst_y_per_vm_vblank, 263 DST_Y_PER_ROW_VBLANK, dlg_attr->dst_y_per_row_vblank); 264 265 REG_SET_2(FLIP_PARAMETERS_0, 0, 266 DST_Y_PER_VM_FLIP, dlg_attr->dst_y_per_vm_flip, 267 DST_Y_PER_ROW_FLIP, dlg_attr->dst_y_per_row_flip); 268 269 REG_SET(VBLANK_PARAMETERS_3, 0, 270 REFCYC_PER_META_CHUNK_VBLANK_L, dlg_attr->refcyc_per_meta_chunk_vblank_l); 271 272 REG_SET(VBLANK_PARAMETERS_4, 0, 273 REFCYC_PER_META_CHUNK_VBLANK_C, dlg_attr->refcyc_per_meta_chunk_vblank_c); 274 275 REG_SET(FLIP_PARAMETERS_2, 0, 276 REFCYC_PER_META_CHUNK_FLIP_L, dlg_attr->refcyc_per_meta_chunk_flip_l); 277 278 REG_SET_2(PER_LINE_DELIVERY_PRE, 0, 279 REFCYC_PER_LINE_DELIVERY_PRE_L, dlg_attr->refcyc_per_line_delivery_pre_l, 280 REFCYC_PER_LINE_DELIVERY_PRE_C, dlg_attr->refcyc_per_line_delivery_pre_c); 281 282 REG_SET(DCN_SURF0_TTU_CNTL1, 0, 283 REFCYC_PER_REQ_DELIVERY_PRE, 284 ttu_attr->refcyc_per_req_delivery_pre_l); 285 REG_SET(DCN_SURF1_TTU_CNTL1, 0, 286 REFCYC_PER_REQ_DELIVERY_PRE, 287 ttu_attr->refcyc_per_req_delivery_pre_c); 288 REG_SET(DCN_CUR0_TTU_CNTL1, 0, 289 REFCYC_PER_REQ_DELIVERY_PRE, ttu_attr->refcyc_per_req_delivery_pre_cur0); 290 REG_SET(DCN_CUR1_TTU_CNTL1, 0, 291 REFCYC_PER_REQ_DELIVERY_PRE, ttu_attr->refcyc_per_req_delivery_pre_cur1); 292 293 REG_SET_2(DCN_GLOBAL_TTU_CNTL, 0, 294 MIN_TTU_VBLANK, ttu_attr->min_ttu_vblank, 295 QoS_LEVEL_FLIP, ttu_attr->qos_level_flip); 296 } 297 298 /* DCN2 (GFX10), the following GFX fields are deprecated. They can be set but they will not be used: 299 * NUM_BANKS 300 * NUM_SE 301 * NUM_RB_PER_SE 302 * RB_ALIGNED 303 * Other things can be defaulted, since they never change: 304 * PIPE_ALIGNED = 0 305 * META_LINEAR = 0 306 * In GFX10, only these apply: 307 * PIPE_INTERLEAVE 308 * NUM_PIPES 309 * MAX_COMPRESSED_FRAGS 310 * SW_MODE 311 */ 312 static void hubp2_program_tiling( 313 struct dcn20_hubp *hubp2, 314 const union dc_tiling_info *info, 315 const enum surface_pixel_format pixel_format) 316 { 317 REG_UPDATE_3(DCSURF_ADDR_CONFIG, 318 NUM_PIPES, log_2(info->gfx9.num_pipes), 319 PIPE_INTERLEAVE, info->gfx9.pipe_interleave, 320 MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags)); 321 322 REG_UPDATE_4(DCSURF_TILING_CONFIG, 323 SW_MODE, info->gfx9.swizzle, 324 META_LINEAR, 0, 325 RB_ALIGNED, 0, 326 PIPE_ALIGNED, 0); 327 } 328 329 void hubp2_program_size( 330 struct hubp *hubp, 331 enum surface_pixel_format format, 332 const struct plane_size *plane_size, 333 struct dc_plane_dcc_param *dcc) 334 { 335 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 336 uint32_t pitch, meta_pitch, pitch_c, meta_pitch_c; 337 bool use_pitch_c = false; 338 339 /* Program data and meta surface pitch (calculation from addrlib) 340 * 444 or 420 luma 341 */ 342 use_pitch_c = format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN 343 && format < SURFACE_PIXEL_FORMAT_SUBSAMPLE_END; 344 if (use_pitch_c) { 345 ASSERT(plane_size->chroma_pitch != 0); 346 /* Chroma pitch zero can cause system hang! */ 347 348 pitch = plane_size->surface_pitch - 1; 349 meta_pitch = dcc->meta_pitch - 1; 350 pitch_c = plane_size->chroma_pitch - 1; 351 meta_pitch_c = dcc->meta_pitch_c - 1; 352 } else { 353 pitch = plane_size->surface_pitch - 1; 354 meta_pitch = dcc->meta_pitch - 1; 355 pitch_c = 0; 356 meta_pitch_c = 0; 357 } 358 359 if (!dcc->enable) { 360 meta_pitch = 0; 361 meta_pitch_c = 0; 362 } 363 364 REG_UPDATE_2(DCSURF_SURFACE_PITCH, 365 PITCH, pitch, META_PITCH, meta_pitch); 366 367 use_pitch_c = format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN; 368 if (use_pitch_c) 369 REG_UPDATE_2(DCSURF_SURFACE_PITCH_C, 370 PITCH_C, pitch_c, META_PITCH_C, meta_pitch_c); 371 } 372 373 void hubp2_program_rotation( 374 struct hubp *hubp, 375 enum dc_rotation_angle rotation, 376 bool horizontal_mirror) 377 { 378 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 379 uint32_t mirror; 380 381 382 if (horizontal_mirror) 383 mirror = 1; 384 else 385 mirror = 0; 386 387 /* Program rotation angle and horz mirror - no mirror */ 388 if (rotation == ROTATION_ANGLE_0) 389 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 390 ROTATION_ANGLE, 0, 391 H_MIRROR_EN, mirror); 392 else if (rotation == ROTATION_ANGLE_90) 393 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 394 ROTATION_ANGLE, 1, 395 H_MIRROR_EN, mirror); 396 else if (rotation == ROTATION_ANGLE_180) 397 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 398 ROTATION_ANGLE, 2, 399 H_MIRROR_EN, mirror); 400 else if (rotation == ROTATION_ANGLE_270) 401 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 402 ROTATION_ANGLE, 3, 403 H_MIRROR_EN, mirror); 404 } 405 406 void hubp2_dcc_control(struct hubp *hubp, bool enable, 407 enum hubp_ind_block_size independent_64b_blks) 408 { 409 uint32_t dcc_en = enable ? 1 : 0; 410 uint32_t dcc_ind_64b_blk = independent_64b_blks ? 1 : 0; 411 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 412 413 REG_UPDATE_4(DCSURF_SURFACE_CONTROL, 414 PRIMARY_SURFACE_DCC_EN, dcc_en, 415 PRIMARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk, 416 SECONDARY_SURFACE_DCC_EN, dcc_en, 417 SECONDARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk); 418 } 419 420 void hubp2_program_pixel_format( 421 struct hubp *hubp, 422 enum surface_pixel_format format) 423 { 424 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 425 uint32_t red_bar = 3; 426 uint32_t blue_bar = 2; 427 428 /* swap for ABGR format */ 429 if (format == SURFACE_PIXEL_FORMAT_GRPH_ABGR8888 430 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010 431 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS 432 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) { 433 red_bar = 2; 434 blue_bar = 3; 435 } 436 437 REG_UPDATE_2(HUBPRET_CONTROL, 438 CROSSBAR_SRC_CB_B, blue_bar, 439 CROSSBAR_SRC_CR_R, red_bar); 440 441 /* Mapping is same as ipp programming (cnvc) */ 442 443 switch (format) { 444 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: 445 REG_UPDATE(DCSURF_SURFACE_CONFIG, 446 SURFACE_PIXEL_FORMAT, 1); 447 break; 448 case SURFACE_PIXEL_FORMAT_GRPH_RGB565: 449 REG_UPDATE(DCSURF_SURFACE_CONFIG, 450 SURFACE_PIXEL_FORMAT, 3); 451 break; 452 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 453 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 454 REG_UPDATE(DCSURF_SURFACE_CONFIG, 455 SURFACE_PIXEL_FORMAT, 8); 456 break; 457 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: 458 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: 459 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS: 460 REG_UPDATE(DCSURF_SURFACE_CONFIG, 461 SURFACE_PIXEL_FORMAT, 10); 462 break; 463 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 464 REG_UPDATE(DCSURF_SURFACE_CONFIG, 465 SURFACE_PIXEL_FORMAT, 22); 466 break; 467 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: 468 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:/*we use crossbar already*/ 469 REG_UPDATE(DCSURF_SURFACE_CONFIG, 470 SURFACE_PIXEL_FORMAT, 24); 471 break; 472 473 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: 474 REG_UPDATE(DCSURF_SURFACE_CONFIG, 475 SURFACE_PIXEL_FORMAT, 65); 476 break; 477 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: 478 REG_UPDATE(DCSURF_SURFACE_CONFIG, 479 SURFACE_PIXEL_FORMAT, 64); 480 break; 481 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: 482 REG_UPDATE(DCSURF_SURFACE_CONFIG, 483 SURFACE_PIXEL_FORMAT, 67); 484 break; 485 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: 486 REG_UPDATE(DCSURF_SURFACE_CONFIG, 487 SURFACE_PIXEL_FORMAT, 66); 488 break; 489 case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888: 490 REG_UPDATE(DCSURF_SURFACE_CONFIG, 491 SURFACE_PIXEL_FORMAT, 12); 492 break; 493 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX: 494 REG_UPDATE(DCSURF_SURFACE_CONFIG, 495 SURFACE_PIXEL_FORMAT, 112); 496 break; 497 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX: 498 REG_UPDATE(DCSURF_SURFACE_CONFIG, 499 SURFACE_PIXEL_FORMAT, 113); 500 break; 501 case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010: 502 REG_UPDATE(DCSURF_SURFACE_CONFIG, 503 SURFACE_PIXEL_FORMAT, 114); 504 break; 505 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT: 506 REG_UPDATE(DCSURF_SURFACE_CONFIG, 507 SURFACE_PIXEL_FORMAT, 118); 508 break; 509 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT: 510 REG_UPDATE(DCSURF_SURFACE_CONFIG, 511 SURFACE_PIXEL_FORMAT, 119); 512 break; 513 default: 514 BREAK_TO_DEBUGGER(); 515 break; 516 } 517 518 /* don't see the need of program the xbar in DCN 1.0 */ 519 } 520 521 void hubp2_program_surface_config( 522 struct hubp *hubp, 523 enum surface_pixel_format format, 524 union dc_tiling_info *tiling_info, 525 struct plane_size *plane_size, 526 enum dc_rotation_angle rotation, 527 struct dc_plane_dcc_param *dcc, 528 bool horizontal_mirror, 529 unsigned int compat_level) 530 { 531 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 532 533 hubp2_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks); 534 hubp2_program_tiling(hubp2, tiling_info, format); 535 hubp2_program_size(hubp, format, plane_size, dcc); 536 hubp2_program_rotation(hubp, rotation, horizontal_mirror); 537 hubp2_program_pixel_format(hubp, format); 538 } 539 540 enum cursor_lines_per_chunk hubp2_get_lines_per_chunk( 541 unsigned int cursor_width, 542 enum dc_cursor_color_format cursor_mode) 543 { 544 enum cursor_lines_per_chunk line_per_chunk = CURSOR_LINE_PER_CHUNK_16; 545 546 if (cursor_mode == CURSOR_MODE_MONO) 547 line_per_chunk = CURSOR_LINE_PER_CHUNK_16; 548 else if (cursor_mode == CURSOR_MODE_COLOR_1BIT_AND || 549 cursor_mode == CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA || 550 cursor_mode == CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA) { 551 if (cursor_width >= 1 && cursor_width <= 32) 552 line_per_chunk = CURSOR_LINE_PER_CHUNK_16; 553 else if (cursor_width >= 33 && cursor_width <= 64) 554 line_per_chunk = CURSOR_LINE_PER_CHUNK_8; 555 else if (cursor_width >= 65 && cursor_width <= 128) 556 line_per_chunk = CURSOR_LINE_PER_CHUNK_4; 557 else if (cursor_width >= 129 && cursor_width <= 256) 558 line_per_chunk = CURSOR_LINE_PER_CHUNK_2; 559 } else if (cursor_mode == CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED || 560 cursor_mode == CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED) { 561 if (cursor_width >= 1 && cursor_width <= 16) 562 line_per_chunk = CURSOR_LINE_PER_CHUNK_16; 563 else if (cursor_width >= 17 && cursor_width <= 32) 564 line_per_chunk = CURSOR_LINE_PER_CHUNK_8; 565 else if (cursor_width >= 33 && cursor_width <= 64) 566 line_per_chunk = CURSOR_LINE_PER_CHUNK_4; 567 else if (cursor_width >= 65 && cursor_width <= 128) 568 line_per_chunk = CURSOR_LINE_PER_CHUNK_2; 569 else if (cursor_width >= 129 && cursor_width <= 256) 570 line_per_chunk = CURSOR_LINE_PER_CHUNK_1; 571 } 572 573 return line_per_chunk; 574 } 575 576 void hubp2_cursor_set_attributes( 577 struct hubp *hubp, 578 const struct dc_cursor_attributes *attr) 579 { 580 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 581 enum cursor_pitch hw_pitch = hubp1_get_cursor_pitch(attr->pitch); 582 enum cursor_lines_per_chunk lpc = hubp2_get_lines_per_chunk( 583 attr->width, attr->color_format); 584 585 hubp->curs_attr = *attr; 586 587 REG_UPDATE(CURSOR_SURFACE_ADDRESS_HIGH, 588 CURSOR_SURFACE_ADDRESS_HIGH, attr->address.high_part); 589 REG_UPDATE(CURSOR_SURFACE_ADDRESS, 590 CURSOR_SURFACE_ADDRESS, attr->address.low_part); 591 592 REG_UPDATE_2(CURSOR_SIZE, 593 CURSOR_WIDTH, attr->width, 594 CURSOR_HEIGHT, attr->height); 595 596 REG_UPDATE_4(CURSOR_CONTROL, 597 CURSOR_MODE, attr->color_format, 598 CURSOR_2X_MAGNIFY, attr->attribute_flags.bits.ENABLE_MAGNIFICATION, 599 CURSOR_PITCH, hw_pitch, 600 CURSOR_LINES_PER_CHUNK, lpc); 601 602 REG_SET_2(CURSOR_SETTINGS, 0, 603 /* no shift of the cursor HDL schedule */ 604 CURSOR0_DST_Y_OFFSET, 0, 605 /* used to shift the cursor chunk request deadline */ 606 CURSOR0_CHUNK_HDL_ADJUST, 3); 607 } 608 609 void hubp2_dmdata_set_attributes( 610 struct hubp *hubp, 611 const struct dc_dmdata_attributes *attr) 612 { 613 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 614 615 if (attr->dmdata_mode == DMDATA_HW_MODE) { 616 /* set to HW mode */ 617 REG_UPDATE(DMDATA_CNTL, 618 DMDATA_MODE, 1); 619 620 /* for DMDATA flip, need to use SURFACE_UPDATE_LOCK */ 621 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, 1); 622 623 /* toggle DMDATA_UPDATED and set repeat and size */ 624 REG_UPDATE(DMDATA_CNTL, 625 DMDATA_UPDATED, 0); 626 REG_UPDATE_3(DMDATA_CNTL, 627 DMDATA_UPDATED, 1, 628 DMDATA_REPEAT, attr->dmdata_repeat, 629 DMDATA_SIZE, attr->dmdata_size); 630 631 /* set DMDATA address */ 632 REG_WRITE(DMDATA_ADDRESS_LOW, attr->address.low_part); 633 REG_UPDATE(DMDATA_ADDRESS_HIGH, 634 DMDATA_ADDRESS_HIGH, attr->address.high_part); 635 636 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, 0); 637 638 } else { 639 /* set to SW mode before loading data */ 640 REG_SET(DMDATA_CNTL, 0, 641 DMDATA_MODE, 0); 642 /* toggle DMDATA_SW_UPDATED to start loading sequence */ 643 REG_UPDATE(DMDATA_SW_CNTL, 644 DMDATA_SW_UPDATED, 0); 645 REG_UPDATE_3(DMDATA_SW_CNTL, 646 DMDATA_SW_UPDATED, 1, 647 DMDATA_SW_REPEAT, attr->dmdata_repeat, 648 DMDATA_SW_SIZE, attr->dmdata_size); 649 /* load data into hubp dmdata buffer */ 650 hubp2_dmdata_load(hubp, attr->dmdata_size, attr->dmdata_sw_data); 651 } 652 653 /* Note that DL_DELTA must be programmed if we want to use TTU mode */ 654 REG_SET_3(DMDATA_QOS_CNTL, 0, 655 DMDATA_QOS_MODE, attr->dmdata_qos_mode, 656 DMDATA_QOS_LEVEL, attr->dmdata_qos_level, 657 DMDATA_DL_DELTA, attr->dmdata_dl_delta); 658 } 659 660 void hubp2_dmdata_load( 661 struct hubp *hubp, 662 uint32_t dmdata_sw_size, 663 const uint32_t *dmdata_sw_data) 664 { 665 int i; 666 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 667 668 /* load dmdata into HUBP buffer in SW mode */ 669 for (i = 0; i < dmdata_sw_size / 4; i++) 670 REG_WRITE(DMDATA_SW_DATA, dmdata_sw_data[i]); 671 } 672 673 bool hubp2_dmdata_status_done(struct hubp *hubp) 674 { 675 uint32_t status; 676 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 677 678 REG_GET(DMDATA_STATUS, DMDATA_DONE, &status); 679 return (status == 1); 680 } 681 682 bool hubp2_program_surface_flip_and_addr( 683 struct hubp *hubp, 684 const struct dc_plane_address *address, 685 bool flip_immediate) 686 { 687 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 688 689 //program flip type 690 REG_UPDATE(DCSURF_FLIP_CONTROL, 691 SURFACE_FLIP_TYPE, flip_immediate); 692 693 // Program VMID reg 694 REG_UPDATE(VMID_SETTINGS_0, 695 VMID, address->vmid); 696 697 if (address->type == PLN_ADDR_TYPE_GRPH_STEREO) { 698 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0x1); 699 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x1); 700 701 } else { 702 // turn off stereo if not in stereo 703 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0x0); 704 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x0); 705 } 706 707 708 709 /* HW automatically latch rest of address register on write to 710 * DCSURF_PRIMARY_SURFACE_ADDRESS if SURFACE_UPDATE_LOCK is not used 711 * 712 * program high first and then the low addr, order matters! 713 */ 714 switch (address->type) { 715 case PLN_ADDR_TYPE_GRAPHICS: 716 /* DCN1.0 does not support const color 717 * TODO: program DCHUBBUB_RET_PATH_DCC_CFGx_0/1 718 * base on address->grph.dcc_const_color 719 * x = 0, 2, 4, 6 for pipe 0, 1, 2, 3 for rgb and luma 720 * x = 1, 3, 5, 7 for pipe 0, 1, 2, 3 for chroma 721 */ 722 723 if (address->grph.addr.quad_part == 0) 724 break; 725 726 REG_UPDATE_2(DCSURF_SURFACE_CONTROL, 727 PRIMARY_SURFACE_TMZ, address->tmz_surface, 728 PRIMARY_META_SURFACE_TMZ, address->tmz_surface); 729 730 if (address->grph.meta_addr.quad_part != 0) { 731 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, 732 PRIMARY_META_SURFACE_ADDRESS_HIGH, 733 address->grph.meta_addr.high_part); 734 735 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, 736 PRIMARY_META_SURFACE_ADDRESS, 737 address->grph.meta_addr.low_part); 738 } 739 740 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, 741 PRIMARY_SURFACE_ADDRESS_HIGH, 742 address->grph.addr.high_part); 743 744 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, 745 PRIMARY_SURFACE_ADDRESS, 746 address->grph.addr.low_part); 747 break; 748 case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE: 749 if (address->video_progressive.luma_addr.quad_part == 0 750 || address->video_progressive.chroma_addr.quad_part == 0) 751 break; 752 753 REG_UPDATE_4(DCSURF_SURFACE_CONTROL, 754 PRIMARY_SURFACE_TMZ, address->tmz_surface, 755 PRIMARY_SURFACE_TMZ_C, address->tmz_surface, 756 PRIMARY_META_SURFACE_TMZ, address->tmz_surface, 757 PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface); 758 759 if (address->video_progressive.luma_meta_addr.quad_part != 0) { 760 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0, 761 PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 762 address->video_progressive.chroma_meta_addr.high_part); 763 764 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0, 765 PRIMARY_META_SURFACE_ADDRESS_C, 766 address->video_progressive.chroma_meta_addr.low_part); 767 768 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, 769 PRIMARY_META_SURFACE_ADDRESS_HIGH, 770 address->video_progressive.luma_meta_addr.high_part); 771 772 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, 773 PRIMARY_META_SURFACE_ADDRESS, 774 address->video_progressive.luma_meta_addr.low_part); 775 } 776 777 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0, 778 PRIMARY_SURFACE_ADDRESS_HIGH_C, 779 address->video_progressive.chroma_addr.high_part); 780 781 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0, 782 PRIMARY_SURFACE_ADDRESS_C, 783 address->video_progressive.chroma_addr.low_part); 784 785 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, 786 PRIMARY_SURFACE_ADDRESS_HIGH, 787 address->video_progressive.luma_addr.high_part); 788 789 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, 790 PRIMARY_SURFACE_ADDRESS, 791 address->video_progressive.luma_addr.low_part); 792 break; 793 case PLN_ADDR_TYPE_GRPH_STEREO: 794 if (address->grph_stereo.left_addr.quad_part == 0) 795 break; 796 if (address->grph_stereo.right_addr.quad_part == 0) 797 break; 798 799 REG_UPDATE_8(DCSURF_SURFACE_CONTROL, 800 PRIMARY_SURFACE_TMZ, address->tmz_surface, 801 PRIMARY_SURFACE_TMZ_C, address->tmz_surface, 802 PRIMARY_META_SURFACE_TMZ, address->tmz_surface, 803 PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface, 804 SECONDARY_SURFACE_TMZ, address->tmz_surface, 805 SECONDARY_SURFACE_TMZ_C, address->tmz_surface, 806 SECONDARY_META_SURFACE_TMZ, address->tmz_surface, 807 SECONDARY_META_SURFACE_TMZ_C, address->tmz_surface); 808 809 if (address->grph_stereo.right_meta_addr.quad_part != 0) { 810 811 REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, 0, 812 SECONDARY_META_SURFACE_ADDRESS_HIGH, 813 address->grph_stereo.right_meta_addr.high_part); 814 815 REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS, 0, 816 SECONDARY_META_SURFACE_ADDRESS, 817 address->grph_stereo.right_meta_addr.low_part); 818 } 819 if (address->grph_stereo.left_meta_addr.quad_part != 0) { 820 821 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, 822 PRIMARY_META_SURFACE_ADDRESS_HIGH, 823 address->grph_stereo.left_meta_addr.high_part); 824 825 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, 826 PRIMARY_META_SURFACE_ADDRESS, 827 address->grph_stereo.left_meta_addr.low_part); 828 } 829 830 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, 0, 831 SECONDARY_SURFACE_ADDRESS_HIGH, 832 address->grph_stereo.right_addr.high_part); 833 834 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0, 835 SECONDARY_SURFACE_ADDRESS, 836 address->grph_stereo.right_addr.low_part); 837 838 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, 839 PRIMARY_SURFACE_ADDRESS_HIGH, 840 address->grph_stereo.left_addr.high_part); 841 842 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, 843 PRIMARY_SURFACE_ADDRESS, 844 address->grph_stereo.left_addr.low_part); 845 break; 846 default: 847 BREAK_TO_DEBUGGER(); 848 break; 849 } 850 851 hubp->request_address = *address; 852 853 return true; 854 } 855 856 void hubp2_enable_triplebuffer( 857 struct hubp *hubp, 858 bool enable) 859 { 860 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 861 uint32_t triple_buffer_en = 0; 862 bool tri_buffer_en; 863 864 REG_GET(DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, &triple_buffer_en); 865 tri_buffer_en = (triple_buffer_en == 1); 866 if (tri_buffer_en != enable) { 867 REG_UPDATE(DCSURF_FLIP_CONTROL2, 868 SURFACE_TRIPLE_BUFFER_ENABLE, enable ? DC_TRIPLEBUFFER_ENABLE : DC_TRIPLEBUFFER_DISABLE); 869 } 870 } 871 872 bool hubp2_is_triplebuffer_enabled( 873 struct hubp *hubp) 874 { 875 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 876 uint32_t triple_buffer_en = 0; 877 878 REG_GET(DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, &triple_buffer_en); 879 880 return (bool)triple_buffer_en; 881 } 882 883 void hubp2_set_flip_control_surface_gsl(struct hubp *hubp, bool enable) 884 { 885 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 886 887 REG_UPDATE(DCSURF_FLIP_CONTROL2, SURFACE_GSL_ENABLE, enable ? 1 : 0); 888 } 889 890 bool hubp2_is_flip_pending(struct hubp *hubp) 891 { 892 uint32_t flip_pending = 0; 893 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 894 struct dc_plane_address earliest_inuse_address; 895 896 REG_GET(DCSURF_FLIP_CONTROL, 897 SURFACE_FLIP_PENDING, &flip_pending); 898 899 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE, 900 SURFACE_EARLIEST_INUSE_ADDRESS, &earliest_inuse_address.grph.addr.low_part); 901 902 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, 903 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &earliest_inuse_address.grph.addr.high_part); 904 905 if (flip_pending) 906 return true; 907 908 if (earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part) 909 return true; 910 911 return false; 912 } 913 914 void hubp2_set_blank(struct hubp *hubp, bool blank) 915 { 916 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 917 uint32_t blank_en = blank ? 1 : 0; 918 919 REG_UPDATE_2(DCHUBP_CNTL, 920 HUBP_BLANK_EN, blank_en, 921 HUBP_TTU_DISABLE, blank_en); 922 923 if (blank) { 924 uint32_t reg_val = REG_READ(DCHUBP_CNTL); 925 926 if (reg_val) { 927 /* init sequence workaround: in case HUBP is 928 * power gated, this wait would timeout. 929 * 930 * we just wrote reg_val to non-0, if it stay 0 931 * it means HUBP is gated 932 */ 933 REG_WAIT(DCHUBP_CNTL, 934 HUBP_NO_OUTSTANDING_REQ, 1, 935 1, 200); 936 } 937 938 hubp->mpcc_id = 0xf; 939 hubp->opp_id = OPP_ID_INVALID; 940 } 941 } 942 943 void hubp2_cursor_set_position( 944 struct hubp *hubp, 945 const struct dc_cursor_position *pos, 946 const struct dc_cursor_mi_param *param) 947 { 948 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 949 int src_x_offset = pos->x - pos->x_hotspot - param->viewport.x; 950 int src_y_offset = pos->y - pos->y_hotspot - param->viewport.y; 951 int x_hotspot = pos->x_hotspot; 952 int y_hotspot = pos->y_hotspot; 953 int cursor_height = (int)hubp->curs_attr.height; 954 int cursor_width = (int)hubp->curs_attr.width; 955 uint32_t dst_x_offset; 956 uint32_t cur_en = pos->enable ? 1 : 0; 957 958 /* 959 * Guard aganst cursor_set_position() from being called with invalid 960 * attributes 961 * 962 * TODO: Look at combining cursor_set_position() and 963 * cursor_set_attributes() into cursor_update() 964 */ 965 if (hubp->curs_attr.address.quad_part == 0) 966 return; 967 968 // Rotated cursor width/height and hotspots tweaks for offset calculation 969 if (param->rotation == ROTATION_ANGLE_90 || param->rotation == ROTATION_ANGLE_270) { 970 swap(cursor_height, cursor_width); 971 if (param->rotation == ROTATION_ANGLE_90) { 972 src_x_offset = pos->x - pos->y_hotspot - param->viewport.x; 973 src_y_offset = pos->y - pos->x_hotspot - param->viewport.y; 974 } 975 } else if (param->rotation == ROTATION_ANGLE_180) { 976 src_x_offset = pos->x - param->viewport.x; 977 src_y_offset = pos->y - param->viewport.y; 978 } 979 980 if (param->mirror) { 981 x_hotspot = param->viewport.width - x_hotspot; 982 src_x_offset = param->viewport.x + param->viewport.width - src_x_offset; 983 } 984 985 dst_x_offset = (src_x_offset >= 0) ? src_x_offset : 0; 986 dst_x_offset *= param->ref_clk_khz; 987 dst_x_offset /= param->pixel_clk_khz; 988 989 ASSERT(param->h_scale_ratio.value); 990 991 if (param->h_scale_ratio.value) 992 dst_x_offset = dc_fixpt_floor(dc_fixpt_div( 993 dc_fixpt_from_int(dst_x_offset), 994 param->h_scale_ratio)); 995 996 if (src_x_offset >= (int)param->viewport.width) 997 cur_en = 0; /* not visible beyond right edge*/ 998 999 if (src_x_offset + cursor_width <= 0) 1000 cur_en = 0; /* not visible beyond left edge*/ 1001 1002 if (src_y_offset >= (int)param->viewport.height) 1003 cur_en = 0; /* not visible beyond bottom edge*/ 1004 1005 if (src_y_offset + cursor_height <= 0) 1006 cur_en = 0; /* not visible beyond top edge*/ 1007 1008 if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0) 1009 hubp->funcs->set_cursor_attributes(hubp, &hubp->curs_attr); 1010 1011 REG_UPDATE(CURSOR_CONTROL, 1012 CURSOR_ENABLE, cur_en); 1013 1014 REG_SET_2(CURSOR_POSITION, 0, 1015 CURSOR_X_POSITION, pos->x, 1016 CURSOR_Y_POSITION, pos->y); 1017 1018 REG_SET_2(CURSOR_HOT_SPOT, 0, 1019 CURSOR_HOT_SPOT_X, x_hotspot, 1020 CURSOR_HOT_SPOT_Y, y_hotspot); 1021 1022 REG_SET(CURSOR_DST_OFFSET, 0, 1023 CURSOR_DST_X_OFFSET, dst_x_offset); 1024 /* TODO Handle surface pixel formats other than 4:4:4 */ 1025 } 1026 1027 void hubp2_clk_cntl(struct hubp *hubp, bool enable) 1028 { 1029 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 1030 uint32_t clk_enable = enable ? 1 : 0; 1031 1032 REG_UPDATE(HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, clk_enable); 1033 } 1034 1035 void hubp2_vtg_sel(struct hubp *hubp, uint32_t otg_inst) 1036 { 1037 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 1038 1039 REG_UPDATE(DCHUBP_CNTL, HUBP_VTG_SEL, otg_inst); 1040 } 1041 1042 void hubp2_clear_underflow(struct hubp *hubp) 1043 { 1044 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 1045 1046 REG_UPDATE(DCHUBP_CNTL, HUBP_UNDERFLOW_CLEAR, 1); 1047 } 1048 1049 void hubp2_read_state_common(struct hubp *hubp) 1050 { 1051 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 1052 struct dcn_hubp_state *s = &hubp2->state; 1053 struct _vcs_dpi_display_dlg_regs_st *dlg_attr = &s->dlg_attr; 1054 struct _vcs_dpi_display_ttu_regs_st *ttu_attr = &s->ttu_attr; 1055 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; 1056 1057 /* Requester */ 1058 REG_GET(HUBPRET_CONTROL, 1059 DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs->plane1_base_address); 1060 REG_GET_4(DCN_EXPANSION_MODE, 1061 DRQ_EXPANSION_MODE, &rq_regs->drq_expansion_mode, 1062 PRQ_EXPANSION_MODE, &rq_regs->prq_expansion_mode, 1063 MRQ_EXPANSION_MODE, &rq_regs->mrq_expansion_mode, 1064 CRQ_EXPANSION_MODE, &rq_regs->crq_expansion_mode); 1065 1066 /* DLG - Per hubp */ 1067 REG_GET_2(BLANK_OFFSET_0, 1068 REFCYC_H_BLANK_END, &dlg_attr->refcyc_h_blank_end, 1069 DLG_V_BLANK_END, &dlg_attr->dlg_vblank_end); 1070 1071 REG_GET(BLANK_OFFSET_1, 1072 MIN_DST_Y_NEXT_START, &dlg_attr->min_dst_y_next_start); 1073 1074 REG_GET(DST_DIMENSIONS, 1075 REFCYC_PER_HTOTAL, &dlg_attr->refcyc_per_htotal); 1076 1077 REG_GET_2(DST_AFTER_SCALER, 1078 REFCYC_X_AFTER_SCALER, &dlg_attr->refcyc_x_after_scaler, 1079 DST_Y_AFTER_SCALER, &dlg_attr->dst_y_after_scaler); 1080 1081 if (REG(PREFETCH_SETTINS)) 1082 REG_GET_2(PREFETCH_SETTINS, 1083 DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch, 1084 VRATIO_PREFETCH, &dlg_attr->vratio_prefetch); 1085 else 1086 REG_GET_2(PREFETCH_SETTINGS, 1087 DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch, 1088 VRATIO_PREFETCH, &dlg_attr->vratio_prefetch); 1089 1090 REG_GET_2(VBLANK_PARAMETERS_0, 1091 DST_Y_PER_VM_VBLANK, &dlg_attr->dst_y_per_vm_vblank, 1092 DST_Y_PER_ROW_VBLANK, &dlg_attr->dst_y_per_row_vblank); 1093 1094 REG_GET(REF_FREQ_TO_PIX_FREQ, 1095 REF_FREQ_TO_PIX_FREQ, &dlg_attr->ref_freq_to_pix_freq); 1096 1097 /* DLG - Per luma/chroma */ 1098 REG_GET(VBLANK_PARAMETERS_1, 1099 REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr->refcyc_per_pte_group_vblank_l); 1100 1101 REG_GET(VBLANK_PARAMETERS_3, 1102 REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr->refcyc_per_meta_chunk_vblank_l); 1103 1104 if (REG(NOM_PARAMETERS_0)) 1105 REG_GET(NOM_PARAMETERS_0, 1106 DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr->dst_y_per_pte_row_nom_l); 1107 1108 if (REG(NOM_PARAMETERS_1)) 1109 REG_GET(NOM_PARAMETERS_1, 1110 REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr->refcyc_per_pte_group_nom_l); 1111 1112 REG_GET(NOM_PARAMETERS_4, 1113 DST_Y_PER_META_ROW_NOM_L, &dlg_attr->dst_y_per_meta_row_nom_l); 1114 1115 REG_GET(NOM_PARAMETERS_5, 1116 REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr->refcyc_per_meta_chunk_nom_l); 1117 1118 REG_GET_2(PER_LINE_DELIVERY_PRE, 1119 REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr->refcyc_per_line_delivery_pre_l, 1120 REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr->refcyc_per_line_delivery_pre_c); 1121 1122 REG_GET_2(PER_LINE_DELIVERY, 1123 REFCYC_PER_LINE_DELIVERY_L, &dlg_attr->refcyc_per_line_delivery_l, 1124 REFCYC_PER_LINE_DELIVERY_C, &dlg_attr->refcyc_per_line_delivery_c); 1125 1126 if (REG(PREFETCH_SETTINS_C)) 1127 REG_GET(PREFETCH_SETTINS_C, 1128 VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c); 1129 else 1130 REG_GET(PREFETCH_SETTINGS_C, 1131 VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c); 1132 1133 REG_GET(VBLANK_PARAMETERS_2, 1134 REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr->refcyc_per_pte_group_vblank_c); 1135 1136 REG_GET(VBLANK_PARAMETERS_4, 1137 REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr->refcyc_per_meta_chunk_vblank_c); 1138 1139 if (REG(NOM_PARAMETERS_2)) 1140 REG_GET(NOM_PARAMETERS_2, 1141 DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr->dst_y_per_pte_row_nom_c); 1142 1143 if (REG(NOM_PARAMETERS_3)) 1144 REG_GET(NOM_PARAMETERS_3, 1145 REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr->refcyc_per_pte_group_nom_c); 1146 1147 REG_GET(NOM_PARAMETERS_6, 1148 DST_Y_PER_META_ROW_NOM_C, &dlg_attr->dst_y_per_meta_row_nom_c); 1149 1150 REG_GET(NOM_PARAMETERS_7, 1151 REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr->refcyc_per_meta_chunk_nom_c); 1152 1153 /* TTU - per hubp */ 1154 REG_GET_2(DCN_TTU_QOS_WM, 1155 QoS_LEVEL_LOW_WM, &ttu_attr->qos_level_low_wm, 1156 QoS_LEVEL_HIGH_WM, &ttu_attr->qos_level_high_wm); 1157 1158 REG_GET_2(DCN_GLOBAL_TTU_CNTL, 1159 MIN_TTU_VBLANK, &ttu_attr->min_ttu_vblank, 1160 QoS_LEVEL_FLIP, &ttu_attr->qos_level_flip); 1161 1162 /* TTU - per luma/chroma */ 1163 /* Assumed surf0 is luma and 1 is chroma */ 1164 1165 REG_GET_3(DCN_SURF0_TTU_CNTL0, 1166 REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_l, 1167 QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_l, 1168 QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_l); 1169 1170 REG_GET(DCN_SURF0_TTU_CNTL1, 1171 REFCYC_PER_REQ_DELIVERY_PRE, 1172 &ttu_attr->refcyc_per_req_delivery_pre_l); 1173 1174 REG_GET_3(DCN_SURF1_TTU_CNTL0, 1175 REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_c, 1176 QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_c, 1177 QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_c); 1178 1179 REG_GET(DCN_SURF1_TTU_CNTL1, 1180 REFCYC_PER_REQ_DELIVERY_PRE, 1181 &ttu_attr->refcyc_per_req_delivery_pre_c); 1182 1183 /* Rest of hubp */ 1184 REG_GET(DCSURF_SURFACE_CONFIG, 1185 SURFACE_PIXEL_FORMAT, &s->pixel_format); 1186 1187 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, 1188 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &s->inuse_addr_hi); 1189 1190 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE, 1191 SURFACE_EARLIEST_INUSE_ADDRESS, &s->inuse_addr_lo); 1192 1193 REG_GET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 1194 PRI_VIEWPORT_WIDTH, &s->viewport_width, 1195 PRI_VIEWPORT_HEIGHT, &s->viewport_height); 1196 1197 REG_GET_2(DCSURF_SURFACE_CONFIG, 1198 ROTATION_ANGLE, &s->rotation_angle, 1199 H_MIRROR_EN, &s->h_mirror_en); 1200 1201 REG_GET(DCSURF_TILING_CONFIG, 1202 SW_MODE, &s->sw_mode); 1203 1204 REG_GET(DCSURF_SURFACE_CONTROL, 1205 PRIMARY_SURFACE_DCC_EN, &s->dcc_en); 1206 1207 REG_GET_3(DCHUBP_CNTL, 1208 HUBP_BLANK_EN, &s->blank_en, 1209 HUBP_TTU_DISABLE, &s->ttu_disable, 1210 HUBP_UNDERFLOW_STATUS, &s->underflow_status); 1211 1212 REG_GET(HUBP_CLK_CNTL, 1213 HUBP_CLOCK_ENABLE, &s->clock_en); 1214 1215 REG_GET(DCN_GLOBAL_TTU_CNTL, 1216 MIN_TTU_VBLANK, &s->min_ttu_vblank); 1217 1218 REG_GET_2(DCN_TTU_QOS_WM, 1219 QoS_LEVEL_LOW_WM, &s->qos_level_low_wm, 1220 QoS_LEVEL_HIGH_WM, &s->qos_level_high_wm); 1221 1222 } 1223 1224 void hubp2_read_state(struct hubp *hubp) 1225 { 1226 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 1227 struct dcn_hubp_state *s = &hubp2->state; 1228 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; 1229 1230 hubp2_read_state_common(hubp); 1231 1232 REG_GET_8(DCHUBP_REQ_SIZE_CONFIG, 1233 CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size, 1234 MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size, 1235 META_CHUNK_SIZE, &rq_regs->rq_regs_l.meta_chunk_size, 1236 MIN_META_CHUNK_SIZE, &rq_regs->rq_regs_l.min_meta_chunk_size, 1237 DPTE_GROUP_SIZE, &rq_regs->rq_regs_l.dpte_group_size, 1238 MPTE_GROUP_SIZE, &rq_regs->rq_regs_l.mpte_group_size, 1239 SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height, 1240 PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear); 1241 1242 REG_GET_8(DCHUBP_REQ_SIZE_CONFIG_C, 1243 CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size, 1244 MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size, 1245 META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.meta_chunk_size, 1246 MIN_META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_meta_chunk_size, 1247 DPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.dpte_group_size, 1248 MPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.mpte_group_size, 1249 SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height, 1250 PTE_ROW_HEIGHT_LINEAR_C, &rq_regs->rq_regs_c.pte_row_height_linear); 1251 1252 } 1253 1254 void hubp2_validate_dml_output(struct hubp *hubp, 1255 struct dc_context *ctx, 1256 struct _vcs_dpi_display_rq_regs_st *dml_rq_regs, 1257 struct _vcs_dpi_display_dlg_regs_st *dml_dlg_attr, 1258 struct _vcs_dpi_display_ttu_regs_st *dml_ttu_attr) 1259 { 1260 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 1261 struct _vcs_dpi_display_rq_regs_st rq_regs = {0}; 1262 struct _vcs_dpi_display_dlg_regs_st dlg_attr = {0}; 1263 struct _vcs_dpi_display_ttu_regs_st ttu_attr = {0}; 1264 DC_LOGGER_INIT(ctx->logger); 1265 DC_LOG_DEBUG("DML Validation | Running Validation"); 1266 1267 /* Requestor Regs */ 1268 REG_GET(HUBPRET_CONTROL, 1269 DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs.plane1_base_address); 1270 REG_GET_4(DCN_EXPANSION_MODE, 1271 DRQ_EXPANSION_MODE, &rq_regs.drq_expansion_mode, 1272 PRQ_EXPANSION_MODE, &rq_regs.prq_expansion_mode, 1273 MRQ_EXPANSION_MODE, &rq_regs.mrq_expansion_mode, 1274 CRQ_EXPANSION_MODE, &rq_regs.crq_expansion_mode); 1275 REG_GET_8(DCHUBP_REQ_SIZE_CONFIG, 1276 CHUNK_SIZE, &rq_regs.rq_regs_l.chunk_size, 1277 MIN_CHUNK_SIZE, &rq_regs.rq_regs_l.min_chunk_size, 1278 META_CHUNK_SIZE, &rq_regs.rq_regs_l.meta_chunk_size, 1279 MIN_META_CHUNK_SIZE, &rq_regs.rq_regs_l.min_meta_chunk_size, 1280 DPTE_GROUP_SIZE, &rq_regs.rq_regs_l.dpte_group_size, 1281 MPTE_GROUP_SIZE, &rq_regs.rq_regs_l.mpte_group_size, 1282 SWATH_HEIGHT, &rq_regs.rq_regs_l.swath_height, 1283 PTE_ROW_HEIGHT_LINEAR, &rq_regs.rq_regs_l.pte_row_height_linear); 1284 REG_GET_8(DCHUBP_REQ_SIZE_CONFIG_C, 1285 CHUNK_SIZE_C, &rq_regs.rq_regs_c.chunk_size, 1286 MIN_CHUNK_SIZE_C, &rq_regs.rq_regs_c.min_chunk_size, 1287 META_CHUNK_SIZE_C, &rq_regs.rq_regs_c.meta_chunk_size, 1288 MIN_META_CHUNK_SIZE_C, &rq_regs.rq_regs_c.min_meta_chunk_size, 1289 DPTE_GROUP_SIZE_C, &rq_regs.rq_regs_c.dpte_group_size, 1290 MPTE_GROUP_SIZE_C, &rq_regs.rq_regs_c.mpte_group_size, 1291 SWATH_HEIGHT_C, &rq_regs.rq_regs_c.swath_height, 1292 PTE_ROW_HEIGHT_LINEAR_C, &rq_regs.rq_regs_c.pte_row_height_linear); 1293 1294 if (rq_regs.plane1_base_address != dml_rq_regs->plane1_base_address) 1295 DC_LOG_DEBUG("DML Validation | HUBPRET_CONTROL:DET_BUF_PLANE1_BASE_ADDRESS - Expected: %u Actual: %u\n", 1296 dml_rq_regs->plane1_base_address, rq_regs.plane1_base_address); 1297 if (rq_regs.drq_expansion_mode != dml_rq_regs->drq_expansion_mode) 1298 DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:DRQ_EXPANSION_MODE - Expected: %u Actual: %u\n", 1299 dml_rq_regs->drq_expansion_mode, rq_regs.drq_expansion_mode); 1300 if (rq_regs.prq_expansion_mode != dml_rq_regs->prq_expansion_mode) 1301 DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:MRQ_EXPANSION_MODE - Expected: %u Actual: %u\n", 1302 dml_rq_regs->prq_expansion_mode, rq_regs.prq_expansion_mode); 1303 if (rq_regs.mrq_expansion_mode != dml_rq_regs->mrq_expansion_mode) 1304 DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:DET_BUF_PLANE1_BASE_ADDRESS - Expected: %u Actual: %u\n", 1305 dml_rq_regs->mrq_expansion_mode, rq_regs.mrq_expansion_mode); 1306 if (rq_regs.crq_expansion_mode != dml_rq_regs->crq_expansion_mode) 1307 DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:CRQ_EXPANSION_MODE - Expected: %u Actual: %u\n", 1308 dml_rq_regs->crq_expansion_mode, rq_regs.crq_expansion_mode); 1309 1310 if (rq_regs.rq_regs_l.chunk_size != dml_rq_regs->rq_regs_l.chunk_size) 1311 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:CHUNK_SIZE - Expected: %u Actual: %u\n", 1312 dml_rq_regs->rq_regs_l.chunk_size, rq_regs.rq_regs_l.chunk_size); 1313 if (rq_regs.rq_regs_l.min_chunk_size != dml_rq_regs->rq_regs_l.min_chunk_size) 1314 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MIN_CHUNK_SIZE - Expected: %u Actual: %u\n", 1315 dml_rq_regs->rq_regs_l.min_chunk_size, rq_regs.rq_regs_l.min_chunk_size); 1316 if (rq_regs.rq_regs_l.meta_chunk_size != dml_rq_regs->rq_regs_l.meta_chunk_size) 1317 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:META_CHUNK_SIZE - Expected: %u Actual: %u\n", 1318 dml_rq_regs->rq_regs_l.meta_chunk_size, rq_regs.rq_regs_l.meta_chunk_size); 1319 if (rq_regs.rq_regs_l.min_meta_chunk_size != dml_rq_regs->rq_regs_l.min_meta_chunk_size) 1320 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MIN_META_CHUNK_SIZE - Expected: %u Actual: %u\n", 1321 dml_rq_regs->rq_regs_l.min_meta_chunk_size, rq_regs.rq_regs_l.min_meta_chunk_size); 1322 if (rq_regs.rq_regs_l.dpte_group_size != dml_rq_regs->rq_regs_l.dpte_group_size) 1323 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:DPTE_GROUP_SIZE - Expected: %u Actual: %u\n", 1324 dml_rq_regs->rq_regs_l.dpte_group_size, rq_regs.rq_regs_l.dpte_group_size); 1325 if (rq_regs.rq_regs_l.mpte_group_size != dml_rq_regs->rq_regs_l.mpte_group_size) 1326 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MPTE_GROUP_SIZE - Expected: %u Actual: %u\n", 1327 dml_rq_regs->rq_regs_l.mpte_group_size, rq_regs.rq_regs_l.mpte_group_size); 1328 if (rq_regs.rq_regs_l.swath_height != dml_rq_regs->rq_regs_l.swath_height) 1329 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:SWATH_HEIGHT - Expected: %u Actual: %u\n", 1330 dml_rq_regs->rq_regs_l.swath_height, rq_regs.rq_regs_l.swath_height); 1331 if (rq_regs.rq_regs_l.pte_row_height_linear != dml_rq_regs->rq_regs_l.pte_row_height_linear) 1332 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:PTE_ROW_HEIGHT_LINEAR - Expected: %u Actual: %u\n", 1333 dml_rq_regs->rq_regs_l.pte_row_height_linear, rq_regs.rq_regs_l.pte_row_height_linear); 1334 1335 if (rq_regs.rq_regs_c.chunk_size != dml_rq_regs->rq_regs_c.chunk_size) 1336 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:CHUNK_SIZE_C - Expected: %u Actual: %u\n", 1337 dml_rq_regs->rq_regs_c.chunk_size, rq_regs.rq_regs_c.chunk_size); 1338 if (rq_regs.rq_regs_c.min_chunk_size != dml_rq_regs->rq_regs_c.min_chunk_size) 1339 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MIN_CHUNK_SIZE_C - Expected: %u Actual: %u\n", 1340 dml_rq_regs->rq_regs_c.min_chunk_size, rq_regs.rq_regs_c.min_chunk_size); 1341 if (rq_regs.rq_regs_c.meta_chunk_size != dml_rq_regs->rq_regs_c.meta_chunk_size) 1342 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:META_CHUNK_SIZE_C - Expected: %u Actual: %u\n", 1343 dml_rq_regs->rq_regs_c.meta_chunk_size, rq_regs.rq_regs_c.meta_chunk_size); 1344 if (rq_regs.rq_regs_c.min_meta_chunk_size != dml_rq_regs->rq_regs_c.min_meta_chunk_size) 1345 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MIN_META_CHUNK_SIZE_C - Expected: %u Actual: %u\n", 1346 dml_rq_regs->rq_regs_c.min_meta_chunk_size, rq_regs.rq_regs_c.min_meta_chunk_size); 1347 if (rq_regs.rq_regs_c.dpte_group_size != dml_rq_regs->rq_regs_c.dpte_group_size) 1348 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:DPTE_GROUP_SIZE_C - Expected: %u Actual: %u\n", 1349 dml_rq_regs->rq_regs_c.dpte_group_size, rq_regs.rq_regs_c.dpte_group_size); 1350 if (rq_regs.rq_regs_c.mpte_group_size != dml_rq_regs->rq_regs_c.mpte_group_size) 1351 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MPTE_GROUP_SIZE_C - Expected: %u Actual: %u\n", 1352 dml_rq_regs->rq_regs_c.mpte_group_size, rq_regs.rq_regs_c.mpte_group_size); 1353 if (rq_regs.rq_regs_c.swath_height != dml_rq_regs->rq_regs_c.swath_height) 1354 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:SWATH_HEIGHT_C - Expected: %u Actual: %u\n", 1355 dml_rq_regs->rq_regs_c.swath_height, rq_regs.rq_regs_c.swath_height); 1356 if (rq_regs.rq_regs_c.pte_row_height_linear != dml_rq_regs->rq_regs_c.pte_row_height_linear) 1357 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:PTE_ROW_HEIGHT_LINEAR_C - Expected: %u Actual: %u\n", 1358 dml_rq_regs->rq_regs_c.pte_row_height_linear, rq_regs.rq_regs_c.pte_row_height_linear); 1359 1360 /* DLG - Per hubp */ 1361 REG_GET_2(BLANK_OFFSET_0, 1362 REFCYC_H_BLANK_END, &dlg_attr.refcyc_h_blank_end, 1363 DLG_V_BLANK_END, &dlg_attr.dlg_vblank_end); 1364 REG_GET(BLANK_OFFSET_1, 1365 MIN_DST_Y_NEXT_START, &dlg_attr.min_dst_y_next_start); 1366 REG_GET(DST_DIMENSIONS, 1367 REFCYC_PER_HTOTAL, &dlg_attr.refcyc_per_htotal); 1368 REG_GET_2(DST_AFTER_SCALER, 1369 REFCYC_X_AFTER_SCALER, &dlg_attr.refcyc_x_after_scaler, 1370 DST_Y_AFTER_SCALER, &dlg_attr.dst_y_after_scaler); 1371 REG_GET(REF_FREQ_TO_PIX_FREQ, 1372 REF_FREQ_TO_PIX_FREQ, &dlg_attr.ref_freq_to_pix_freq); 1373 1374 if (dlg_attr.refcyc_h_blank_end != dml_dlg_attr->refcyc_h_blank_end) 1375 DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_0:REFCYC_H_BLANK_END - Expected: %u Actual: %u\n", 1376 dml_dlg_attr->refcyc_h_blank_end, dlg_attr.refcyc_h_blank_end); 1377 if (dlg_attr.dlg_vblank_end != dml_dlg_attr->dlg_vblank_end) 1378 DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_0:DLG_V_BLANK_END - Expected: %u Actual: %u\n", 1379 dml_dlg_attr->dlg_vblank_end, dlg_attr.dlg_vblank_end); 1380 if (dlg_attr.min_dst_y_next_start != dml_dlg_attr->min_dst_y_next_start) 1381 DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_1:MIN_DST_Y_NEXT_START - Expected: %u Actual: %u\n", 1382 dml_dlg_attr->min_dst_y_next_start, dlg_attr.min_dst_y_next_start); 1383 if (dlg_attr.refcyc_per_htotal != dml_dlg_attr->refcyc_per_htotal) 1384 DC_LOG_DEBUG("DML Validation | DST_DIMENSIONS:REFCYC_PER_HTOTAL - Expected: %u Actual: %u\n", 1385 dml_dlg_attr->refcyc_per_htotal, dlg_attr.refcyc_per_htotal); 1386 if (dlg_attr.refcyc_x_after_scaler != dml_dlg_attr->refcyc_x_after_scaler) 1387 DC_LOG_DEBUG("DML Validation | DST_AFTER_SCALER:REFCYC_X_AFTER_SCALER - Expected: %u Actual: %u\n", 1388 dml_dlg_attr->refcyc_x_after_scaler, dlg_attr.refcyc_x_after_scaler); 1389 if (dlg_attr.dst_y_after_scaler != dml_dlg_attr->dst_y_after_scaler) 1390 DC_LOG_DEBUG("DML Validation | DST_AFTER_SCALER:DST_Y_AFTER_SCALER - Expected: %u Actual: %u\n", 1391 dml_dlg_attr->dst_y_after_scaler, dlg_attr.dst_y_after_scaler); 1392 if (dlg_attr.ref_freq_to_pix_freq != dml_dlg_attr->ref_freq_to_pix_freq) 1393 DC_LOG_DEBUG("DML Validation | REF_FREQ_TO_PIX_FREQ:REF_FREQ_TO_PIX_FREQ - Expected: %u Actual: %u\n", 1394 dml_dlg_attr->ref_freq_to_pix_freq, dlg_attr.ref_freq_to_pix_freq); 1395 1396 /* DLG - Per luma/chroma */ 1397 REG_GET(VBLANK_PARAMETERS_1, 1398 REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr.refcyc_per_pte_group_vblank_l); 1399 if (REG(NOM_PARAMETERS_0)) 1400 REG_GET(NOM_PARAMETERS_0, 1401 DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr.dst_y_per_pte_row_nom_l); 1402 if (REG(NOM_PARAMETERS_1)) 1403 REG_GET(NOM_PARAMETERS_1, 1404 REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr.refcyc_per_pte_group_nom_l); 1405 REG_GET(NOM_PARAMETERS_4, 1406 DST_Y_PER_META_ROW_NOM_L, &dlg_attr.dst_y_per_meta_row_nom_l); 1407 REG_GET(NOM_PARAMETERS_5, 1408 REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr.refcyc_per_meta_chunk_nom_l); 1409 REG_GET_2(PER_LINE_DELIVERY, 1410 REFCYC_PER_LINE_DELIVERY_L, &dlg_attr.refcyc_per_line_delivery_l, 1411 REFCYC_PER_LINE_DELIVERY_C, &dlg_attr.refcyc_per_line_delivery_c); 1412 REG_GET_2(PER_LINE_DELIVERY_PRE, 1413 REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr.refcyc_per_line_delivery_pre_l, 1414 REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr.refcyc_per_line_delivery_pre_c); 1415 REG_GET(VBLANK_PARAMETERS_2, 1416 REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr.refcyc_per_pte_group_vblank_c); 1417 if (REG(NOM_PARAMETERS_2)) 1418 REG_GET(NOM_PARAMETERS_2, 1419 DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr.dst_y_per_pte_row_nom_c); 1420 if (REG(NOM_PARAMETERS_3)) 1421 REG_GET(NOM_PARAMETERS_3, 1422 REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr.refcyc_per_pte_group_nom_c); 1423 REG_GET(NOM_PARAMETERS_6, 1424 DST_Y_PER_META_ROW_NOM_C, &dlg_attr.dst_y_per_meta_row_nom_c); 1425 REG_GET(NOM_PARAMETERS_7, 1426 REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr.refcyc_per_meta_chunk_nom_c); 1427 REG_GET(VBLANK_PARAMETERS_3, 1428 REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr.refcyc_per_meta_chunk_vblank_l); 1429 REG_GET(VBLANK_PARAMETERS_4, 1430 REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr.refcyc_per_meta_chunk_vblank_c); 1431 1432 if (dlg_attr.refcyc_per_pte_group_vblank_l != dml_dlg_attr->refcyc_per_pte_group_vblank_l) 1433 DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_1:REFCYC_PER_PTE_GROUP_VBLANK_L - Expected: %u Actual: %u\n", 1434 dml_dlg_attr->refcyc_per_pte_group_vblank_l, dlg_attr.refcyc_per_pte_group_vblank_l); 1435 if (dlg_attr.dst_y_per_pte_row_nom_l != dml_dlg_attr->dst_y_per_pte_row_nom_l) 1436 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_0:DST_Y_PER_PTE_ROW_NOM_L - Expected: %u Actual: %u\n", 1437 dml_dlg_attr->dst_y_per_pte_row_nom_l, dlg_attr.dst_y_per_pte_row_nom_l); 1438 if (dlg_attr.refcyc_per_pte_group_nom_l != dml_dlg_attr->refcyc_per_pte_group_nom_l) 1439 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_1:REFCYC_PER_PTE_GROUP_NOM_L - Expected: %u Actual: %u\n", 1440 dml_dlg_attr->refcyc_per_pte_group_nom_l, dlg_attr.refcyc_per_pte_group_nom_l); 1441 if (dlg_attr.dst_y_per_meta_row_nom_l != dml_dlg_attr->dst_y_per_meta_row_nom_l) 1442 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_4:DST_Y_PER_META_ROW_NOM_L - Expected: %u Actual: %u\n", 1443 dml_dlg_attr->dst_y_per_meta_row_nom_l, dlg_attr.dst_y_per_meta_row_nom_l); 1444 if (dlg_attr.refcyc_per_meta_chunk_nom_l != dml_dlg_attr->refcyc_per_meta_chunk_nom_l) 1445 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_5:REFCYC_PER_META_CHUNK_NOM_L - Expected: %u Actual: %u\n", 1446 dml_dlg_attr->refcyc_per_meta_chunk_nom_l, dlg_attr.refcyc_per_meta_chunk_nom_l); 1447 if (dlg_attr.refcyc_per_line_delivery_l != dml_dlg_attr->refcyc_per_line_delivery_l) 1448 DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY:REFCYC_PER_LINE_DELIVERY_L - Expected: %u Actual: %u\n", 1449 dml_dlg_attr->refcyc_per_line_delivery_l, dlg_attr.refcyc_per_line_delivery_l); 1450 if (dlg_attr.refcyc_per_line_delivery_c != dml_dlg_attr->refcyc_per_line_delivery_c) 1451 DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY:REFCYC_PER_LINE_DELIVERY_C - Expected: %u Actual: %u\n", 1452 dml_dlg_attr->refcyc_per_line_delivery_c, dlg_attr.refcyc_per_line_delivery_c); 1453 if (dlg_attr.refcyc_per_pte_group_vblank_c != dml_dlg_attr->refcyc_per_pte_group_vblank_c) 1454 DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_2:REFCYC_PER_PTE_GROUP_VBLANK_C - Expected: %u Actual: %u\n", 1455 dml_dlg_attr->refcyc_per_pte_group_vblank_c, dlg_attr.refcyc_per_pte_group_vblank_c); 1456 if (dlg_attr.dst_y_per_pte_row_nom_c != dml_dlg_attr->dst_y_per_pte_row_nom_c) 1457 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_2:DST_Y_PER_PTE_ROW_NOM_C - Expected: %u Actual: %u\n", 1458 dml_dlg_attr->dst_y_per_pte_row_nom_c, dlg_attr.dst_y_per_pte_row_nom_c); 1459 if (dlg_attr.refcyc_per_pte_group_nom_c != dml_dlg_attr->refcyc_per_pte_group_nom_c) 1460 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_3:REFCYC_PER_PTE_GROUP_NOM_C - Expected: %u Actual: %u\n", 1461 dml_dlg_attr->refcyc_per_pte_group_nom_c, dlg_attr.refcyc_per_pte_group_nom_c); 1462 if (dlg_attr.dst_y_per_meta_row_nom_c != dml_dlg_attr->dst_y_per_meta_row_nom_c) 1463 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_6:DST_Y_PER_META_ROW_NOM_C - Expected: %u Actual: %u\n", 1464 dml_dlg_attr->dst_y_per_meta_row_nom_c, dlg_attr.dst_y_per_meta_row_nom_c); 1465 if (dlg_attr.refcyc_per_meta_chunk_nom_c != dml_dlg_attr->refcyc_per_meta_chunk_nom_c) 1466 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_7:REFCYC_PER_META_CHUNK_NOM_C - Expected: %u Actual: %u\n", 1467 dml_dlg_attr->refcyc_per_meta_chunk_nom_c, dlg_attr.refcyc_per_meta_chunk_nom_c); 1468 if (dlg_attr.refcyc_per_line_delivery_pre_l != dml_dlg_attr->refcyc_per_line_delivery_pre_l) 1469 DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY_PRE:REFCYC_PER_LINE_DELIVERY_PRE_L - Expected: %u Actual: %u\n", 1470 dml_dlg_attr->refcyc_per_line_delivery_pre_l, dlg_attr.refcyc_per_line_delivery_pre_l); 1471 if (dlg_attr.refcyc_per_line_delivery_pre_c != dml_dlg_attr->refcyc_per_line_delivery_pre_c) 1472 DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY_PRE:REFCYC_PER_LINE_DELIVERY_PRE_C - Expected: %u Actual: %u\n", 1473 dml_dlg_attr->refcyc_per_line_delivery_pre_c, dlg_attr.refcyc_per_line_delivery_pre_c); 1474 if (dlg_attr.refcyc_per_meta_chunk_vblank_l != dml_dlg_attr->refcyc_per_meta_chunk_vblank_l) 1475 DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_3:REFCYC_PER_META_CHUNK_VBLANK_L - Expected: %u Actual: %u\n", 1476 dml_dlg_attr->refcyc_per_meta_chunk_vblank_l, dlg_attr.refcyc_per_meta_chunk_vblank_l); 1477 if (dlg_attr.refcyc_per_meta_chunk_vblank_c != dml_dlg_attr->refcyc_per_meta_chunk_vblank_c) 1478 DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_4:REFCYC_PER_META_CHUNK_VBLANK_C - Expected: %u Actual: %u\n", 1479 dml_dlg_attr->refcyc_per_meta_chunk_vblank_c, dlg_attr.refcyc_per_meta_chunk_vblank_c); 1480 1481 /* TTU - per hubp */ 1482 REG_GET_2(DCN_TTU_QOS_WM, 1483 QoS_LEVEL_LOW_WM, &ttu_attr.qos_level_low_wm, 1484 QoS_LEVEL_HIGH_WM, &ttu_attr.qos_level_high_wm); 1485 1486 if (ttu_attr.qos_level_low_wm != dml_ttu_attr->qos_level_low_wm) 1487 DC_LOG_DEBUG("DML Validation | DCN_TTU_QOS_WM:QoS_LEVEL_LOW_WM - Expected: %u Actual: %u\n", 1488 dml_ttu_attr->qos_level_low_wm, ttu_attr.qos_level_low_wm); 1489 if (ttu_attr.qos_level_high_wm != dml_ttu_attr->qos_level_high_wm) 1490 DC_LOG_DEBUG("DML Validation | DCN_TTU_QOS_WM:QoS_LEVEL_HIGH_WM - Expected: %u Actual: %u\n", 1491 dml_ttu_attr->qos_level_high_wm, ttu_attr.qos_level_high_wm); 1492 1493 /* TTU - per luma/chroma */ 1494 /* Assumed surf0 is luma and 1 is chroma */ 1495 REG_GET_3(DCN_SURF0_TTU_CNTL0, 1496 REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_l, 1497 QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_l, 1498 QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_l); 1499 REG_GET_3(DCN_SURF1_TTU_CNTL0, 1500 REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_c, 1501 QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_c, 1502 QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_c); 1503 REG_GET_3(DCN_CUR0_TTU_CNTL0, 1504 REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_cur0, 1505 QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_cur0, 1506 QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_cur0); 1507 REG_GET(FLIP_PARAMETERS_1, 1508 REFCYC_PER_PTE_GROUP_FLIP_L, &dlg_attr.refcyc_per_pte_group_flip_l); 1509 REG_GET(DCN_CUR0_TTU_CNTL1, 1510 REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_cur0); 1511 REG_GET(DCN_CUR1_TTU_CNTL1, 1512 REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_cur1); 1513 REG_GET(DCN_SURF0_TTU_CNTL1, 1514 REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_l); 1515 REG_GET(DCN_SURF1_TTU_CNTL1, 1516 REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_c); 1517 1518 if (ttu_attr.refcyc_per_req_delivery_l != dml_ttu_attr->refcyc_per_req_delivery_l) 1519 DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n", 1520 dml_ttu_attr->refcyc_per_req_delivery_l, ttu_attr.refcyc_per_req_delivery_l); 1521 if (ttu_attr.qos_level_fixed_l != dml_ttu_attr->qos_level_fixed_l) 1522 DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n", 1523 dml_ttu_attr->qos_level_fixed_l, ttu_attr.qos_level_fixed_l); 1524 if (ttu_attr.qos_ramp_disable_l != dml_ttu_attr->qos_ramp_disable_l) 1525 DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n", 1526 dml_ttu_attr->qos_ramp_disable_l, ttu_attr.qos_ramp_disable_l); 1527 if (ttu_attr.refcyc_per_req_delivery_c != dml_ttu_attr->refcyc_per_req_delivery_c) 1528 DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n", 1529 dml_ttu_attr->refcyc_per_req_delivery_c, ttu_attr.refcyc_per_req_delivery_c); 1530 if (ttu_attr.qos_level_fixed_c != dml_ttu_attr->qos_level_fixed_c) 1531 DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n", 1532 dml_ttu_attr->qos_level_fixed_c, ttu_attr.qos_level_fixed_c); 1533 if (ttu_attr.qos_ramp_disable_c != dml_ttu_attr->qos_ramp_disable_c) 1534 DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n", 1535 dml_ttu_attr->qos_ramp_disable_c, ttu_attr.qos_ramp_disable_c); 1536 if (ttu_attr.refcyc_per_req_delivery_cur0 != dml_ttu_attr->refcyc_per_req_delivery_cur0) 1537 DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n", 1538 dml_ttu_attr->refcyc_per_req_delivery_cur0, ttu_attr.refcyc_per_req_delivery_cur0); 1539 if (ttu_attr.qos_level_fixed_cur0 != dml_ttu_attr->qos_level_fixed_cur0) 1540 DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n", 1541 dml_ttu_attr->qos_level_fixed_cur0, ttu_attr.qos_level_fixed_cur0); 1542 if (ttu_attr.qos_ramp_disable_cur0 != dml_ttu_attr->qos_ramp_disable_cur0) 1543 DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n", 1544 dml_ttu_attr->qos_ramp_disable_cur0, ttu_attr.qos_ramp_disable_cur0); 1545 if (dlg_attr.refcyc_per_pte_group_flip_l != dml_dlg_attr->refcyc_per_pte_group_flip_l) 1546 DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_1:REFCYC_PER_PTE_GROUP_FLIP_L - Expected: %u Actual: %u\n", 1547 dml_dlg_attr->refcyc_per_pte_group_flip_l, dlg_attr.refcyc_per_pte_group_flip_l); 1548 if (ttu_attr.refcyc_per_req_delivery_pre_cur0 != dml_ttu_attr->refcyc_per_req_delivery_pre_cur0) 1549 DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", 1550 dml_ttu_attr->refcyc_per_req_delivery_pre_cur0, ttu_attr.refcyc_per_req_delivery_pre_cur0); 1551 if (ttu_attr.refcyc_per_req_delivery_pre_cur1 != dml_ttu_attr->refcyc_per_req_delivery_pre_cur1) 1552 DC_LOG_DEBUG("DML Validation | DCN_CUR1_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", 1553 dml_ttu_attr->refcyc_per_req_delivery_pre_cur1, ttu_attr.refcyc_per_req_delivery_pre_cur1); 1554 if (ttu_attr.refcyc_per_req_delivery_pre_l != dml_ttu_attr->refcyc_per_req_delivery_pre_l) 1555 DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", 1556 dml_ttu_attr->refcyc_per_req_delivery_pre_l, ttu_attr.refcyc_per_req_delivery_pre_l); 1557 if (ttu_attr.refcyc_per_req_delivery_pre_c != dml_ttu_attr->refcyc_per_req_delivery_pre_c) 1558 DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", 1559 dml_ttu_attr->refcyc_per_req_delivery_pre_c, ttu_attr.refcyc_per_req_delivery_pre_c); 1560 } 1561 1562 static struct hubp_funcs dcn20_hubp_funcs = { 1563 .hubp_enable_tripleBuffer = hubp2_enable_triplebuffer, 1564 .hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled, 1565 .hubp_program_surface_flip_and_addr = hubp2_program_surface_flip_and_addr, 1566 .hubp_program_surface_config = hubp2_program_surface_config, 1567 .hubp_is_flip_pending = hubp2_is_flip_pending, 1568 .hubp_setup = hubp2_setup, 1569 .hubp_setup_interdependent = hubp2_setup_interdependent, 1570 .hubp_set_vm_system_aperture_settings = hubp2_set_vm_system_aperture_settings, 1571 .set_blank = hubp2_set_blank, 1572 .dcc_control = hubp2_dcc_control, 1573 .mem_program_viewport = min_set_viewport, 1574 .set_cursor_attributes = hubp2_cursor_set_attributes, 1575 .set_cursor_position = hubp2_cursor_set_position, 1576 .hubp_clk_cntl = hubp2_clk_cntl, 1577 .hubp_vtg_sel = hubp2_vtg_sel, 1578 .dmdata_set_attributes = hubp2_dmdata_set_attributes, 1579 .dmdata_load = hubp2_dmdata_load, 1580 .dmdata_status_done = hubp2_dmdata_status_done, 1581 .hubp_read_state = hubp2_read_state, 1582 .hubp_clear_underflow = hubp2_clear_underflow, 1583 .hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl, 1584 .hubp_init = hubp1_init, 1585 .validate_dml_output = hubp2_validate_dml_output, 1586 }; 1587 1588 1589 bool hubp2_construct( 1590 struct dcn20_hubp *hubp2, 1591 struct dc_context *ctx, 1592 uint32_t inst, 1593 const struct dcn_hubp2_registers *hubp_regs, 1594 const struct dcn_hubp2_shift *hubp_shift, 1595 const struct dcn_hubp2_mask *hubp_mask) 1596 { 1597 hubp2->base.funcs = &dcn20_hubp_funcs; 1598 hubp2->base.ctx = ctx; 1599 hubp2->hubp_regs = hubp_regs; 1600 hubp2->hubp_shift = hubp_shift; 1601 hubp2->hubp_mask = hubp_mask; 1602 hubp2->base.inst = inst; 1603 hubp2->base.opp_id = OPP_ID_INVALID; 1604 hubp2->base.mpcc_id = 0xf; 1605 1606 return true; 1607 } 1608
Indexes created Sat Sep 20 22:09:52 GMT 2025