1 /* $NetBSD: hvcall.S,v 1.5 2021/04/27 19:09:56 palle Exp $ */ 2 /* $OpenBSD: hvcall.S,v 1.10 2011/06/25 20:45:00 kettenis Exp $ */ 3 4 /* 5 * Copyright (c) 2008 Mark Kettenis 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #include <machine/asm.h> 21 #include <machine/trap.h> 22 23 24 #define MACH_EXIT 0x00 25 #define MACH_DESC 0x01 26 #define MACH_SIR 0x02 27 #define MACH_SET_WATCHDOG 0x05 28 29 #define CPU_START 0x10 30 #define CPU_STOP 0x11 31 #define CPU_YIELD 0x12 32 #define CPU_QCONF 0x14 33 #define CPU_QINFO 0x15 34 #define CPU_MYID 0x16 35 #define CPU_STATE 0x17 36 #define CPU_SET_RTBA 0x18 37 #define CPU_GET_RTBA 0x19 38 39 #define MMU_TSB_CTX0 0x20 40 #define MMU_TSB_CTXNON0 0x21 41 #define MMU_DEMAP_PAGE 0x22 42 #define MMU_DEMAP_CTX 0x23 43 #define MMU_DEMAP_ALL 0x24 44 #define MMU_MAP_PERM_ADDR 0x25 45 #define MMU_FAULT_AREA_CONF 0x26 46 #define MMU_ENABLE 0x27 47 #define MMU_UNMAP_PERM_ADDR 0x28 48 #define MMU_TSB_CTX0_INFO 0x29 49 #define MMU_TSB_CTXNON0_INFO 0x2a 50 #define MMU_FAULT_AREA_INFO 0x2b 51 52 #define MEM_SCRUB 0x30 53 #define MEM_SYNC 0x31 54 55 #define CPU_MONDO_SEND 0x42 56 57 #define TOD_GET 0x50 58 #define TOD_SET 0x51 59 60 #define CONS_GETCHAR 0x60 61 #define CONS_PUTCHAR 0x61 62 63 #define SOFT_STATE_SET 0x70 64 #define SOFT_STATE_GET 0x71 65 66 #define INTR_DEVINO2SYSINO 0xa0 67 #define INTR_GETENABLED 0xa1 68 #define INTR_SETENABLED 0xa2 69 #define INTR_GETSTATE 0xa3 70 #define INTR_SETSTATE 0xa4 71 #define INTR_GETTARGET 0xa5 72 #define INTR_SETTARGET 0xa6 73 74 #define VINTR_GETCOOKIE 0xa7 75 #define VINTR_SETCOOKIE 0xa8 76 #define VINTR_GETENABLED 0xa9 77 #define VINTR_SETENABLED 0xaa 78 #define VINTR_GETSTATE 0xab 79 #define VINTR_SETSTATE 0xac 80 #define VINTR_GETTARGET 0xad 81 #define VINTR_SETTARGET 0xae 82 83 #define PCI_IOMMU_MAP 0xb0 84 #define PCI_IOMMU_DEMAP 0xb1 85 #define PCI_IOMMU_GETMAP 0xb2 86 #define PCI_IOMMU_GETBYPASS 0xb3 87 #define PCI_CONFIG_GET 0xb4 88 #define PCI_CONFIG_PUT 0xb5 89 90 #define PCI_MSIQ_CONF 0xc0 91 #define PCI_MSIQ_INFO 0xc1 92 #define PCI_MSIQ_GETVALID 0xc2 93 #define PCI_MSIQ_SETVALID 0xc3 94 #define PCI_MSIQ_GETSTATE 0xc4 95 #define PCI_MSIQ_SETSTATE 0xc5 96 #define PCI_MSIQ_GETHEAD 0xc6 97 #define PCI_MSIQ_SETHEAD 0xc7 98 #define PCI_MSIQ_GETTAIL 0xc8 99 #define PCI_MSI_GETVALID 0xc9 100 #define PCI_MSI_SETVALID 0xca 101 #define PCI_MSI_GETMSIQ 0xcb 102 #define PCI_MSI_SETMSIQ 0xcc 103 #define PCI_MSI_GETSTATE 0xcd 104 #define PCI_MSI_SETSTATE 0xce 105 #define PCI_MSG_GETMSIQ 0xd0 106 #define PCI_MSG_SETMSIQ 0xd1 107 #define PCI_MSG_GETSTATE 0xd2 108 #define PCI_MSG_SETSTATE 0xd3 109 110 #define LDC_TX_QCONF 0xe0 111 #define LDC_TX_QINFO 0xe1 112 #define LDC_TX_GET_STATE 0xe2 113 #define LDC_TX_SET_QTAIL 0xe3 114 #define LDC_RX_QCONF 0xe4 115 #define LDC_RX_QINFO 0xe5 116 #define LDC_RX_GET_STATE 0xe6 117 #define LDC_RX_SET_QHEAD 0xe7 118 119 #define LDC_SET_MAP_TABLE 0xea 120 #define LDC_GET_MAP_TABLE 0xeb 121 #define LDC_COPY 0xec 122 123 #define LDC_MAPIN 0xed 124 #define LDC_UNMAP 0xee 125 #define LDC_REVOKE 0xef 126 127 #define RNG_GET_DIAG_CONTROL 0x130 128 #define RNG_CTL_READ 0x131 129 #define RNG_CTL_WRITE 0x132 130 #define RNG_DATA_READ_DIAG 0x133 131 #define RNG_DATA_READ 0x134 132 133 #define API_SET_VERSION 0x00 134 #define API_PUTCHAR 0x01 135 #define API_EXIT 0x02 136 #define API_GET_VERSION 0x03 137 138 139 ENTRY(hv_api_putchar) 140 mov API_PUTCHAR, %o5 141 ta ST_CORE_TRAP 142 retl 143 nop 144 145 ENTRY(hv_api_get_version) 146 mov %o2, %o4 147 mov %o1, %o3 148 mov API_GET_VERSION, %o5 149 ta ST_CORE_TRAP 150 stx %o1, [%o3] 151 retl 152 stx %o2, [%o4] 153 154 ENTRY(hv_api_set_version) 155 mov %o3, %o4 156 mov API_SET_VERSION, %o5 157 ta ST_CORE_TRAP 158 retl 159 stx %o1, [%o4] 160 161 ENTRY(hv_mach_desc) 162 mov %o1, %o2 163 ldx [%o2], %o1 164 mov MACH_DESC, %o5 165 ta ST_FAST_TRAP 166 retl 167 stx %o1, [%o2] 168 169 ENTRY(hv_cpu_yield) 170 mov CPU_YIELD, %o5 171 ta ST_FAST_TRAP 172 retl 173 nop 174 175 ENTRY(hv_cpu_qconf) 176 mov CPU_QCONF, %o5 177 ta ST_FAST_TRAP 178 retl 179 nop 180 181 ENTRY(hv_cpu_mondo_send) 182 mov CPU_MONDO_SEND, %o5 183 ta ST_FAST_TRAP 184 retl 185 nop 186 187 ENTRY(hv_cpu_myid) 188 mov %o0, %o2 189 mov CPU_MYID, %o5 190 ta ST_FAST_TRAP 191 retl 192 stx %o1, [%o2] 193 194 ENTRY(hv_mmu_tsb_ctx0) 195 mov MMU_TSB_CTX0, %o5 196 ta ST_FAST_TRAP 197 retl 198 nop 199 200 ENTRY(hv_mmu_tsb_ctxnon0) 201 mov MMU_TSB_CTXNON0, %o5 202 ta ST_FAST_TRAP 203 retl 204 nop 205 206 ENTRY(hv_mmu_demap_page) 207 mov %o2, %o4 208 mov %o1, %o3 209 mov %o0, %o2 210 clr %o1 211 clr %o0 212 mov MMU_DEMAP_PAGE, %o5 213 ta ST_FAST_TRAP 214 retl 215 nop 216 217 ENTRY(hv_mmu_demap_ctx) 218 mov %o1, %o3 219 mov %o0, %o2 220 clr %o1 221 clr %o0 222 mov MMU_DEMAP_CTX, %o5 223 ta ST_FAST_TRAP 224 retl 225 nop 226 227 ENTRY(hv_mmu_demap_all) 228 mov %o1, %o3 229 mov %o0, %o2 230 clr %o1 231 clr %o0 232 mov MMU_DEMAP_CTX, %o5 233 ta ST_FAST_TRAP 234 retl 235 nop 236 237 ENTRY(hv_mmu_map_perm_addr) 238 mov %o2, %o3 239 mov %o1, %o2 240 clr %o1 241 mov MMU_MAP_PERM_ADDR, %o5 242 ta ST_FAST_TRAP 243 retl 244 nop 245 246 ENTRY(hv_mmu_unmap_perm_addr) 247 mov %o1, %o2 248 clr %o1 249 mov MMU_UNMAP_PERM_ADDR, %o5 250 ta ST_FAST_TRAP 251 retl 252 nop 253 254 ENTRY(hv_mmu_map_addr) 255 ta ST_MMU_MAP_ADDR 256 retl 257 nop 258 259 ENTRY(hv_mmu_unmap_addr) 260 ta ST_MMU_UNMAP_ADDR 261 retl 262 nop 263 264 ENTRY(hv_mem_scrub) 265 mov MEM_SCRUB, %o5 266 ta ST_FAST_TRAP 267 retl 268 nop 269 270 ENTRY(hv_mem_sync) 271 mov MEM_SYNC, %o5 272 ta ST_FAST_TRAP 273 retl 274 nop 275 276 ENTRY(hv_tod_get) 277 mov %o0, %o2 278 mov TOD_GET, %o5 279 ta ST_FAST_TRAP 280 retl 281 stx %o1, [%o2] 282 283 ENTRY(hv_tod_set) 284 mov TOD_SET, %o5 285 ta ST_FAST_TRAP 286 retl 287 nop 288 289 ENTRY(hv_cons_getchar) 290 mov %o0, %o2 291 mov CONS_GETCHAR, %o5 292 ta ST_FAST_TRAP 293 retl 294 stx %o1, [%o2] 295 296 ENTRY(hv_cons_putchar) 297 mov CONS_PUTCHAR, %o5 298 ta ST_FAST_TRAP 299 retl 300 nop 301 302 ENTRY(hv_soft_state_set) 303 mov SOFT_STATE_SET, %o5 304 ta ST_FAST_TRAP 305 retl 306 nop 307 308 ENTRY(hv_intr_devino_to_sysino) 309 mov INTR_DEVINO2SYSINO, %o5 310 ta ST_FAST_TRAP 311 retl 312 stx %o1, [%o2] 313 314 ENTRY(hv_intr_getenabled) 315 mov %o1, %o2 316 mov INTR_GETENABLED, %o5 317 ta ST_FAST_TRAP 318 retl 319 stx %o1, [%o2] 320 321 ENTRY(hv_intr_setenabled) 322 mov INTR_SETENABLED, %o5 323 ta ST_FAST_TRAP 324 retl 325 nop 326 327 ENTRY(hv_intr_getstate) 328 mov %o1, %o2 329 mov INTR_GETSTATE, %o5 330 ta ST_FAST_TRAP 331 retl 332 stx %o1, [%o2] 333 334 ENTRY(hv_intr_setstate) 335 mov INTR_SETSTATE, %o5 336 ta ST_FAST_TRAP 337 retl 338 nop 339 340 ENTRY(hv_intr_gettarget) 341 mov %o1, %o2 342 mov INTR_GETTARGET, %o5 343 ta ST_FAST_TRAP 344 retl 345 stx %o1, [%o2] 346 347 ENTRY(hv_intr_settarget) 348 mov INTR_SETTARGET, %o5 349 ta ST_FAST_TRAP 350 retl 351 nop 352 353 ENTRY(hv_vintr_getcookie) 354 mov VINTR_GETCOOKIE, %o5 355 ta ST_FAST_TRAP 356 retl 357 stx %o1, [%o2] 358 359 ENTRY(hv_vintr_setcookie) 360 mov VINTR_SETCOOKIE, %o5 361 ta ST_FAST_TRAP 362 retl 363 nop 364 365 ENTRY(hv_vintr_getenabled) 366 mov VINTR_GETENABLED, %o5 367 ta ST_FAST_TRAP 368 retl 369 stx %o1, [%o2] 370 371 ENTRY(hv_vintr_setenabled) 372 mov VINTR_SETENABLED, %o5 373 ta ST_FAST_TRAP 374 retl 375 nop 376 377 ENTRY(hv_vintr_getstate) 378 mov VINTR_GETSTATE, %o5 379 ta ST_FAST_TRAP 380 retl 381 stx %o1, [%o2] 382 383 ENTRY(hv_vintr_setstate) 384 mov VINTR_SETSTATE, %o5 385 ta ST_FAST_TRAP 386 retl 387 nop 388 389 ENTRY(hv_vintr_gettarget) 390 mov VINTR_GETTARGET, %o5 391 ta ST_FAST_TRAP 392 retl 393 stx %o1, [%o2] 394 395 ENTRY(hv_vintr_settarget) 396 mov VINTR_SETTARGET, %o5 397 ta ST_FAST_TRAP 398 retl 399 nop 400 401 ENTRY(hv_pci_iommu_map) 402 mov %o5, %g5 403 mov PCI_IOMMU_MAP, %o5 404 ta ST_FAST_TRAP 405 retl 406 stx %o1, [%g5] 407 408 ENTRY(hv_pci_iommu_demap) 409 mov PCI_IOMMU_DEMAP, %o5 410 ta ST_FAST_TRAP 411 retl 412 stx %o1, [%o3] 413 414 ENTRY(hv_pci_iommu_getmap) 415 mov %o2, %o4 416 mov PCI_IOMMU_GETMAP, %o5 417 ta ST_FAST_TRAP 418 stx %o1, [%o4] 419 retl 420 stx %o2, [%o3] 421 422 ENTRY(hv_pci_iommu_getbypass) 423 mov PCI_IOMMU_GETBYPASS, %o5 424 ta ST_FAST_TRAP 425 retl 426 stx %o1, [%o3] 427 428 ENTRY(hv_pci_config_get) 429 mov %o5, %g5 430 mov PCI_CONFIG_GET, %o5 431 ta ST_FAST_TRAP 432 stx %o1, [%o4] 433 retl 434 stx %o2, [%g5] 435 436 ENTRY(hv_pci_config_put) 437 mov %o5, %g5 438 mov PCI_CONFIG_PUT, %o5 439 ta ST_FAST_TRAP 440 retl 441 stx %o1, [%g5] 442 443 ENTRY(hv_pci_msiq_conf) 444 mov PCI_MSIQ_CONF, %o5 445 ta ST_FAST_TRAP 446 retl 447 nop 448 449 ENTRY(hv_pci_msiq_info) 450 mov %o2, %o4 451 mov PCI_MSIQ_INFO, %o5 452 ta ST_FAST_TRAP 453 stx %o1, [%o4] 454 retl 455 stx %o2, [%o3] 456 457 ENTRY(hv_pci_msiq_getvalid) 458 mov PCI_MSIQ_GETVALID, %o5 459 ta ST_FAST_TRAP 460 retl 461 stx %o1, [%o2] 462 463 ENTRY(hv_pci_msiq_setvalid) 464 mov PCI_MSIQ_SETVALID, %o5 465 ta ST_FAST_TRAP 466 retl 467 nop 468 469 ENTRY(hv_pci_msiq_getstate) 470 mov PCI_MSIQ_GETSTATE, %o5 471 ta ST_FAST_TRAP 472 retl 473 stx %o1, [%o2] 474 475 ENTRY(hv_pci_msiq_setstate) 476 mov PCI_MSIQ_SETSTATE, %o5 477 ta ST_FAST_TRAP 478 retl 479 nop 480 481 ENTRY(hv_pci_msiq_gethead) 482 mov PCI_MSIQ_GETHEAD, %o5 483 ta ST_FAST_TRAP 484 retl 485 stx %o1, [%o2] 486 487 ENTRY(hv_pci_msiq_sethead) 488 mov PCI_MSIQ_SETHEAD, %o5 489 ta ST_FAST_TRAP 490 retl 491 nop 492 493 ENTRY(hv_pci_msiq_gettail) 494 mov PCI_MSIQ_GETTAIL, %o5 495 ta ST_FAST_TRAP 496 retl 497 stx %o1, [%o2] 498 499 ENTRY(hv_pci_msi_getvalid) 500 mov PCI_MSI_GETVALID, %o5 501 ta ST_FAST_TRAP 502 retl 503 stx %o1, [%o2] 504 505 ENTRY(hv_pci_msi_setvalid) 506 mov PCI_MSI_SETVALID, %o5 507 ta ST_FAST_TRAP 508 retl 509 nop 510 511 ENTRY(hv_pci_msi_getmsiq) 512 mov PCI_MSI_GETMSIQ, %o5 513 ta ST_FAST_TRAP 514 retl 515 stx %o1, [%o2] 516 517 ENTRY(hv_pci_msi_setmsiq) 518 mov PCI_MSI_SETMSIQ, %o5 519 ta ST_FAST_TRAP 520 retl 521 nop 522 523 ENTRY(hv_pci_msi_getstate) 524 mov PCI_MSI_GETSTATE, %o5 525 ta ST_FAST_TRAP 526 retl 527 stx %o1, [%o2] 528 529 ENTRY(hv_pci_msi_setstate) 530 mov PCI_MSI_SETSTATE, %o5 531 ta ST_FAST_TRAP 532 retl 533 nop 534 535 ENTRY(hv_pci_msg_getmsiq) 536 mov PCI_MSG_GETMSIQ, %o5 537 ta ST_FAST_TRAP 538 retl 539 stx %o1, [%o2] 540 541 ENTRY(hv_pci_msg_setmsiq) 542 mov PCI_MSG_SETMSIQ, %o5 543 ta ST_FAST_TRAP 544 retl 545 nop 546 547 ENTRY(hv_pci_msg_getstate) 548 mov PCI_MSG_GETSTATE, %o5 549 ta ST_FAST_TRAP 550 retl 551 stx %o1, [%o2] 552 553 ENTRY(hv_pci_msg_setstate) 554 mov PCI_MSG_SETSTATE, %o5 555 ta ST_FAST_TRAP 556 retl 557 nop 558 559 ENTRY(hv_ldc_tx_qconf) 560 mov LDC_TX_QCONF, %o5 561 ta ST_FAST_TRAP 562 retl 563 nop 564 565 ENTRY(hv_ldc_tx_qinfo) 566 mov %o2, %o4 567 mov %o1, %o3 568 mov LDC_TX_QINFO, %o5 569 ta ST_FAST_TRAP 570 stx %o1, [%o3] 571 retl 572 stx %o2, [%o4] 573 574 ENTRY(hv_ldc_tx_get_state) 575 mov %o3, %g5 576 mov %o2, %g4 577 mov %o1, %o4 578 mov LDC_TX_GET_STATE, %o5 579 ta ST_FAST_TRAP 580 stx %o1, [%o4] 581 stx %o2, [%g4] 582 retl 583 stx %o3, [%g5] 584 585 ENTRY(hv_ldc_tx_set_qtail) 586 mov LDC_TX_SET_QTAIL, %o5 587 ta ST_FAST_TRAP 588 retl 589 nop 590 591 ENTRY(hv_ldc_rx_qconf) 592 mov LDC_RX_QCONF, %o5 593 ta ST_FAST_TRAP 594 retl 595 nop 596 597 ENTRY(hv_ldc_rx_qinfo) 598 mov %o2, %o4 599 mov %o1, %o3 600 mov LDC_RX_QINFO, %o5 601 ta ST_FAST_TRAP 602 stx %o1, [%o3] 603 retl 604 stx %o2, [%o4] 605 606 ENTRY(hv_ldc_rx_get_state) 607 mov %o3, %g5 608 mov %o2, %g4 609 mov %o1, %o4 610 mov LDC_RX_GET_STATE, %o5 611 ta ST_FAST_TRAP 612 stx %o1, [%o4] 613 stx %o2, [%g4] 614 retl 615 stx %o3, [%g5] 616 617 ENTRY(hv_ldc_rx_set_qhead) 618 mov LDC_RX_SET_QHEAD, %o5 619 ta ST_FAST_TRAP 620 retl 621 nop 622 623 ENTRY(hv_ldc_set_map_table) 624 mov LDC_SET_MAP_TABLE, %o5 625 ta ST_FAST_TRAP 626 retl 627 nop 628 629 ENTRY(hv_ldc_get_map_table) 630 mov %o2, %o4 631 mov %o1, %o3 632 mov LDC_GET_MAP_TABLE, %o5 633 ta ST_FAST_TRAP 634 stx %o1, [%o3] 635 retl 636 stx %o2, [%o4] 637 638 ENTRY(hv_ldc_copy) 639 mov %o5, %g5 640 mov LDC_COPY, %o5 641 ta ST_FAST_TRAP 642 retl 643 stx %o1, [%g5] 644 645 ENTRY(hv_ldc_mapin) 646 mov %o2, %o4 647 mov LDC_MAPIN, %o5 648 ta ST_FAST_TRAP 649 stx %o1, [%o4] 650 retl 651 stx %o2, [%o3] 652 653 ENTRY(hv_ldc_unmap) 654 mov %o1, %o2 655 mov LDC_UNMAP, %o5 656 ta ST_FAST_TRAP 657 retl 658 stx %o1, [%o2] 659 660 ENTRY(hv_rng_get_diag_control) 661 mov RNG_GET_DIAG_CONTROL, %o5 662 ta ST_FAST_TRAP 663 retl 664 nop 665 666 ENTRY(hv_rng_ctl_read) 667 mov %o2, %o4 668 mov %o1, %o3 669 mov RNG_CTL_READ, %o5 670 ta ST_FAST_TRAP 671 stx %o1, [%o3] 672 retl 673 stx %o2, [%o4] 674 675 ENTRY(hv_rng_ctl_write) 676 mov RNG_CTL_WRITE, %o5 677 ta ST_FAST_TRAP 678 retl 679 stx %o1, [%o3] 680 681 ENTRY(hv_rng_data_read_diag) 682 mov RNG_DATA_READ_DIAG, %o5 683 ta ST_FAST_TRAP 684 retl 685 stx %o1, [%o2] 686 687 ENTRY(hv_rng_data_read) 688 mov %o1, %o2 689 mov RNG_DATA_READ, %o5 690 ta ST_FAST_TRAP 691 retl 692 stx %o1, [%o2] 693
Indexes created Sun Sep 21 14:09:52 GMT 2025