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      1 // SPDX-License-Identifier: GPL-2.0
      2 #include "bcm283x.dtsi"
      3 
      4 #include <dt-bindings/interrupt-controller/arm-gic.h>
      5 #include <dt-bindings/soc/bcm2835-pm.h>
      6 
      7 / {
      8 	compatible = "brcm,bcm2711";
      9 
     10 	#address-cells = <2>;
     11 	#size-cells = <1>;
     12 
     13 	interrupt-parent = <&gicv2>;
     14 
     15 	vc4: gpu {
     16 		compatible = "brcm,bcm2711-vc5";
     17 		status = "disabled";
     18 	};
     19 
     20 	clk_27MHz: clk-27M {
     21 		#clock-cells = <0>;
     22 		compatible = "fixed-clock";
     23 		clock-frequency = <27000000>;
     24 		clock-output-names = "27MHz-clock";
     25 	};
     26 
     27 	clk_108MHz: clk-108M {
     28 		#clock-cells = <0>;
     29 		compatible = "fixed-clock";
     30 		clock-frequency = <108000000>;
     31 		clock-output-names = "108MHz-clock";
     32 	};
     33 
     34 	soc {
     35 		/*
     36 		 * Defined ranges:
     37 		 *   Common BCM283x peripherals
     38 		 *   BCM2711-specific peripherals
     39 		 *   ARM-local peripherals
     40 		 */
     41 		ranges = <0x7e000000  0x0 0xfe000000  0x01800000>,
     42 			 <0x7c000000  0x0 0xfc000000  0x02000000>,
     43 			 <0x40000000  0x0 0xff800000  0x00800000>;
     44 		/* Emulate a contiguous 30-bit address range for DMA */
     45 		dma-ranges = <0xc0000000  0x0 0x00000000  0x40000000>;
     46 
     47 		/*
     48 		 * This node is the provider for the enable-method for
     49 		 * bringing up secondary cores.
     50 		 */
     51 		local_intc: local_intc@40000000 {
     52 			compatible = "brcm,bcm2836-l1-intc";
     53 			reg = <0x40000000 0x100>;
     54 		};
     55 
     56 		gicv2: interrupt-controller@40041000 {
     57 			interrupt-controller;
     58 			#interrupt-cells = <3>;
     59 			compatible = "arm,gic-400";
     60 			reg =	<0x40041000 0x1000>,
     61 				<0x40042000 0x2000>,
     62 				<0x40044000 0x2000>,
     63 				<0x40046000 0x2000>;
     64 			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
     65 						 IRQ_TYPE_LEVEL_HIGH)>;
     66 		};
     67 
     68 		avs_monitor: avs-monitor@7d5d2000 {
     69 			compatible = "brcm,bcm2711-avs-monitor",
     70 				     "syscon", "simple-mfd";
     71 			reg = <0x7d5d2000 0xf00>;
     72 
     73 			thermal: thermal {
     74 				compatible = "brcm,bcm2711-thermal";
     75 				#thermal-sensor-cells = <0>;
     76 			};
     77 		};
     78 
     79 		dma: dma@7e007000 {
     80 			compatible = "brcm,bcm2835-dma";
     81 			reg = <0x7e007000 0xb00>;
     82 			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
     83 				     <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
     84 				     <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
     85 				     <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
     86 				     <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
     87 				     <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
     88 				     <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
     89 				     /* DMA lite 7 - 10 */
     90 				     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
     91 				     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
     92 				     <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
     93 				     <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
     94 			interrupt-names = "dma0",
     95 					  "dma1",
     96 					  "dma2",
     97 					  "dma3",
     98 					  "dma4",
     99 					  "dma5",
    100 					  "dma6",
    101 					  "dma7",
    102 					  "dma8",
    103 					  "dma9",
    104 					  "dma10";
    105 			#dma-cells = <1>;
    106 			brcm,dma-channel-mask = <0x07f5>;
    107 		};
    108 
    109 		pm: watchdog@7e100000 {
    110 			compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt";
    111 			#power-domain-cells = <1>;
    112 			#reset-cells = <1>;
    113 			reg = <0x7e100000 0x114>,
    114 			      <0x7e00a000 0x24>,
    115 			      <0x7ec11000 0x20>;
    116 			clocks = <&clocks BCM2835_CLOCK_V3D>,
    117 				 <&clocks BCM2835_CLOCK_PERI_IMAGE>,
    118 				 <&clocks BCM2835_CLOCK_H264>,
    119 				 <&clocks BCM2835_CLOCK_ISP>;
    120 			clock-names = "v3d", "peri_image", "h264", "isp";
    121 			system-power-controller;
    122 		};
    123 
    124 		rng@7e104000 {
    125 			compatible = "brcm,bcm2711-rng200";
    126 			reg = <0x7e104000 0x28>;
    127 		};
    128 
    129 		uart2: serial@7e201400 {
    130 			compatible = "arm,pl011", "arm,primecell";
    131 			reg = <0x7e201400 0x200>;
    132 			interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
    133 			clocks = <&clocks BCM2835_CLOCK_UART>,
    134 				 <&clocks BCM2835_CLOCK_VPU>;
    135 			clock-names = "uartclk", "apb_pclk";
    136 			arm,primecell-periphid = <0x00241011>;
    137 			status = "disabled";
    138 		};
    139 
    140 		uart3: serial@7e201600 {
    141 			compatible = "arm,pl011", "arm,primecell";
    142 			reg = <0x7e201600 0x200>;
    143 			interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
    144 			clocks = <&clocks BCM2835_CLOCK_UART>,
    145 				 <&clocks BCM2835_CLOCK_VPU>;
    146 			clock-names = "uartclk", "apb_pclk";
    147 			arm,primecell-periphid = <0x00241011>;
    148 			status = "disabled";
    149 		};
    150 
    151 		uart4: serial@7e201800 {
    152 			compatible = "arm,pl011", "arm,primecell";
    153 			reg = <0x7e201800 0x200>;
    154 			interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
    155 			clocks = <&clocks BCM2835_CLOCK_UART>,
    156 				 <&clocks BCM2835_CLOCK_VPU>;
    157 			clock-names = "uartclk", "apb_pclk";
    158 			arm,primecell-periphid = <0x00241011>;
    159 			status = "disabled";
    160 		};
    161 
    162 		uart5: serial@7e201a00 {
    163 			compatible = "arm,pl011", "arm,primecell";
    164 			reg = <0x7e201a00 0x200>;
    165 			interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
    166 			clocks = <&clocks BCM2835_CLOCK_UART>,
    167 				 <&clocks BCM2835_CLOCK_VPU>;
    168 			clock-names = "uartclk", "apb_pclk";
    169 			arm,primecell-periphid = <0x00241011>;
    170 			status = "disabled";
    171 		};
    172 
    173 		spi3: spi@7e204600 {
    174 			compatible = "brcm,bcm2835-spi";
    175 			reg = <0x7e204600 0x0200>;
    176 			interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
    177 			clocks = <&clocks BCM2835_CLOCK_VPU>;
    178 			#address-cells = <1>;
    179 			#size-cells = <0>;
    180 			status = "disabled";
    181 		};
    182 
    183 		spi4: spi@7e204800 {
    184 			compatible = "brcm,bcm2835-spi";
    185 			reg = <0x7e204800 0x0200>;
    186 			interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
    187 			clocks = <&clocks BCM2835_CLOCK_VPU>;
    188 			#address-cells = <1>;
    189 			#size-cells = <0>;
    190 			status = "disabled";
    191 		};
    192 
    193 		spi5: spi@7e204a00 {
    194 			compatible = "brcm,bcm2835-spi";
    195 			reg = <0x7e204a00 0x0200>;
    196 			interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
    197 			clocks = <&clocks BCM2835_CLOCK_VPU>;
    198 			#address-cells = <1>;
    199 			#size-cells = <0>;
    200 			status = "disabled";
    201 		};
    202 
    203 		spi6: spi@7e204c00 {
    204 			compatible = "brcm,bcm2835-spi";
    205 			reg = <0x7e204c00 0x0200>;
    206 			interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
    207 			clocks = <&clocks BCM2835_CLOCK_VPU>;
    208 			#address-cells = <1>;
    209 			#size-cells = <0>;
    210 			status = "disabled";
    211 		};
    212 
    213 		i2c3: i2c@7e205600 {
    214 			compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
    215 			reg = <0x7e205600 0x200>;
    216 			interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
    217 			clocks = <&clocks BCM2835_CLOCK_VPU>;
    218 			#address-cells = <1>;
    219 			#size-cells = <0>;
    220 			status = "disabled";
    221 		};
    222 
    223 		i2c4: i2c@7e205800 {
    224 			compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
    225 			reg = <0x7e205800 0x200>;
    226 			interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
    227 			clocks = <&clocks BCM2835_CLOCK_VPU>;
    228 			#address-cells = <1>;
    229 			#size-cells = <0>;
    230 			status = "disabled";
    231 		};
    232 
    233 		i2c5: i2c@7e205a00 {
    234 			compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
    235 			reg = <0x7e205a00 0x200>;
    236 			interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
    237 			clocks = <&clocks BCM2835_CLOCK_VPU>;
    238 			#address-cells = <1>;
    239 			#size-cells = <0>;
    240 			status = "disabled";
    241 		};
    242 
    243 		i2c6: i2c@7e205c00 {
    244 			compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
    245 			reg = <0x7e205c00 0x200>;
    246 			interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
    247 			clocks = <&clocks BCM2835_CLOCK_VPU>;
    248 			#address-cells = <1>;
    249 			#size-cells = <0>;
    250 			status = "disabled";
    251 		};
    252 
    253 		pixelvalve0: pixelvalve@7e206000 {
    254 			compatible = "brcm,bcm2711-pixelvalve0";
    255 			reg = <0x7e206000 0x100>;
    256 			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
    257 			status = "disabled";
    258 		};
    259 
    260 		pixelvalve1: pixelvalve@7e207000 {
    261 			compatible = "brcm,bcm2711-pixelvalve1";
    262 			reg = <0x7e207000 0x100>;
    263 			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
    264 			status = "disabled";
    265 		};
    266 
    267 		pixelvalve2: pixelvalve@7e20a000 {
    268 			compatible = "brcm,bcm2711-pixelvalve2";
    269 			reg = <0x7e20a000 0x100>;
    270 			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
    271 			status = "disabled";
    272 		};
    273 
    274 		pwm1: pwm@7e20c800 {
    275 			compatible = "brcm,bcm2835-pwm";
    276 			reg = <0x7e20c800 0x28>;
    277 			clocks = <&clocks BCM2835_CLOCK_PWM>;
    278 			assigned-clocks = <&clocks BCM2835_CLOCK_PWM>;
    279 			assigned-clock-rates = <10000000>;
    280 			#pwm-cells = <2>;
    281 			status = "disabled";
    282 		};
    283 
    284 		pixelvalve4: pixelvalve@7e216000 {
    285 			compatible = "brcm,bcm2711-pixelvalve4";
    286 			reg = <0x7e216000 0x100>;
    287 			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
    288 			status = "disabled";
    289 		};
    290 
    291 		hvs: hvs@7e400000 {
    292 			compatible = "brcm,bcm2711-hvs";
    293 			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
    294 		};
    295 
    296 		pixelvalve3: pixelvalve@7ec12000 {
    297 			compatible = "brcm,bcm2711-pixelvalve3";
    298 			reg = <0x7ec12000 0x100>;
    299 			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
    300 			status = "disabled";
    301 		};
    302 
    303 		vec: vec@7ec13000 {
    304 			compatible = "brcm,bcm2711-vec";
    305 			reg = <0x7ec13000 0x1000>;
    306 			clocks = <&clocks BCM2835_CLOCK_VEC>;
    307 			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
    308 			status = "disabled";
    309 		};
    310 
    311 		dvp: clock@7ef00000 {
    312 			compatible = "brcm,brcm2711-dvp";
    313 			reg = <0x7ef00000 0x10>;
    314 			clocks = <&clk_108MHz>;
    315 			#clock-cells = <1>;
    316 			#reset-cells = <1>;
    317 		};
    318 
    319 		aon_intr: interrupt-controller@7ef00100 {
    320 			compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc";
    321 			reg = <0x7ef00100 0x30>;
    322 			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
    323 			interrupt-controller;
    324 			#interrupt-cells = <1>;
    325 		};
    326 
    327 		hdmi0: hdmi@7ef00700 {
    328 			compatible = "brcm,bcm2711-hdmi0";
    329 			reg = <0x7ef00700 0x300>,
    330 			      <0x7ef00300 0x200>,
    331 			      <0x7ef00f00 0x80>,
    332 			      <0x7ef00f80 0x80>,
    333 			      <0x7ef01b00 0x200>,
    334 			      <0x7ef01f00 0x400>,
    335 			      <0x7ef00200 0x80>,
    336 			      <0x7ef04300 0x100>,
    337 			      <0x7ef20000 0x100>;
    338 			reg-names = "hdmi",
    339 				    "dvp",
    340 				    "phy",
    341 				    "rm",
    342 				    "packet",
    343 				    "metadata",
    344 				    "csc",
    345 				    "cec",
    346 				    "hd";
    347 			clock-names = "hdmi", "bvb", "audio", "cec";
    348 			resets = <&dvp 0>;
    349 			interrupt-parent = <&aon_intr>;
    350 			interrupts = <0>, <1>, <2>,
    351 				     <3>, <4>, <5>;
    352 			interrupt-names = "cec-tx", "cec-rx", "cec-low",
    353 					  "wakeup", "hpd-connected", "hpd-removed";
    354 			ddc = <&ddc0>;
    355 			dmas = <&dma 10>;
    356 			dma-names = "audio-rx";
    357 			status = "disabled";
    358 		};
    359 
    360 		ddc0: i2c@7ef04500 {
    361 			compatible = "brcm,bcm2711-hdmi-i2c";
    362 			reg = <0x7ef04500 0x100>, <0x7ef00b00 0x300>;
    363 			reg-names = "bsc", "auto-i2c";
    364 			clock-frequency = <97500>;
    365 			status = "disabled";
    366 		};
    367 
    368 		hdmi1: hdmi@7ef05700 {
    369 			compatible = "brcm,bcm2711-hdmi1";
    370 			reg = <0x7ef05700 0x300>,
    371 			      <0x7ef05300 0x200>,
    372 			      <0x7ef05f00 0x80>,
    373 			      <0x7ef05f80 0x80>,
    374 			      <0x7ef06b00 0x200>,
    375 			      <0x7ef06f00 0x400>,
    376 			      <0x7ef00280 0x80>,
    377 			      <0x7ef09300 0x100>,
    378 			      <0x7ef20000 0x100>;
    379 			reg-names = "hdmi",
    380 				    "dvp",
    381 				    "phy",
    382 				    "rm",
    383 				    "packet",
    384 				    "metadata",
    385 				    "csc",
    386 				    "cec",
    387 				    "hd";
    388 			ddc = <&ddc1>;
    389 			clock-names = "hdmi", "bvb", "audio", "cec";
    390 			resets = <&dvp 1>;
    391 			interrupt-parent = <&aon_intr>;
    392 			interrupts = <8>, <7>, <6>,
    393 				     <9>, <10>, <11>;
    394 			interrupt-names = "cec-tx", "cec-rx", "cec-low",
    395 					  "wakeup", "hpd-connected", "hpd-removed";
    396 			dmas = <&dma 17>;
    397 			dma-names = "audio-rx";
    398 			status = "disabled";
    399 		};
    400 
    401 		ddc1: i2c@7ef09500 {
    402 			compatible = "brcm,bcm2711-hdmi-i2c";
    403 			reg = <0x7ef09500 0x100>, <0x7ef05b00 0x300>;
    404 			reg-names = "bsc", "auto-i2c";
    405 			clock-frequency = <97500>;
    406 			status = "disabled";
    407 		};
    408 	};
    409 
    410 	/*
    411 	 * emmc2 has different DMA constraints based on SoC revisions. It was
    412 	 * moved into its own bus, so as for RPi4's firmware to update them.
    413 	 * The firmware will find whether the emmc2bus alias is defined, and if
    414 	 * so, it'll edit the dma-ranges property below accordingly.
    415 	 */
    416 	emmc2bus: emmc2bus {
    417 		compatible = "simple-bus";
    418 		#address-cells = <2>;
    419 		#size-cells = <1>;
    420 
    421 		ranges = <0x0 0x7e000000  0x0 0xfe000000  0x01800000>;
    422 		dma-ranges = <0x0 0xc0000000  0x0 0x00000000  0x40000000>;
    423 
    424 		emmc2: mmc@7e340000 {
    425 			compatible = "brcm,bcm2711-emmc2";
    426 			reg = <0x0 0x7e340000 0x100>;
    427 			interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
    428 			clocks = <&clocks BCM2711_CLOCK_EMMC2>;
    429 			status = "disabled";
    430 		};
    431 	};
    432 
    433 	arm-pmu {
    434 		compatible = "arm,cortex-a72-pmu", "arm,armv8-pmuv3";
    435 		interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
    436 			<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
    437 			<GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
    438 			<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
    439 		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
    440 	};
    441 
    442 	timer {
    443 		compatible = "arm,armv8-timer";
    444 		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
    445 					  IRQ_TYPE_LEVEL_LOW)>,
    446 			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
    447 					  IRQ_TYPE_LEVEL_LOW)>,
    448 			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
    449 					  IRQ_TYPE_LEVEL_LOW)>,
    450 			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
    451 					  IRQ_TYPE_LEVEL_LOW)>;
    452 		/* This only applies to the ARMv7 stub */
    453 		arm,cpu-registers-not-fw-configured;
    454 	};
    455 
    456 	cpus: cpus {
    457 		#address-cells = <1>;
    458 		#size-cells = <0>;
    459 		enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit
    460 
    461 		cpu0: cpu@0 {
    462 			device_type = "cpu";
    463 			compatible = "arm,cortex-a72";
    464 			reg = <0>;
    465 			enable-method = "spin-table";
    466 			cpu-release-addr = <0x0 0x000000d8>;
    467 		};
    468 
    469 		cpu1: cpu@1 {
    470 			device_type = "cpu";
    471 			compatible = "arm,cortex-a72";
    472 			reg = <1>;
    473 			enable-method = "spin-table";
    474 			cpu-release-addr = <0x0 0x000000e0>;
    475 		};
    476 
    477 		cpu2: cpu@2 {
    478 			device_type = "cpu";
    479 			compatible = "arm,cortex-a72";
    480 			reg = <2>;
    481 			enable-method = "spin-table";
    482 			cpu-release-addr = <0x0 0x000000e8>;
    483 		};
    484 
    485 		cpu3: cpu@3 {
    486 			device_type = "cpu";
    487 			compatible = "arm,cortex-a72";
    488 			reg = <3>;
    489 			enable-method = "spin-table";
    490 			cpu-release-addr = <0x0 0x000000f0>;
    491 		};
    492 	};
    493 
    494 	scb {
    495 		compatible = "simple-bus";
    496 		#address-cells = <2>;
    497 		#size-cells = <1>;
    498 
    499 		ranges = <0x0 0x7c000000  0x0 0xfc000000  0x03800000>,
    500 			 <0x6 0x00000000  0x6 0x00000000  0x40000000>;
    501 
    502 		pcie0: pcie@7d500000 {
    503 			compatible = "brcm,bcm2711-pcie";
    504 			reg = <0x0 0x7d500000 0x9310>;
    505 			device_type = "pci";
    506 			#address-cells = <3>;
    507 			#interrupt-cells = <1>;
    508 			#size-cells = <2>;
    509 			interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
    510 				     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
    511 			interrupt-names = "pcie", "msi";
    512 			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
    513 			interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143
    514 							IRQ_TYPE_LEVEL_HIGH>;
    515 			msi-controller;
    516 			msi-parent = <&pcie0>;
    517 
    518 			ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000
    519 				  0x0 0x04000000>;
    520 			/*
    521 			 * The wrapper around the PCIe block has a bug
    522 			 * preventing it from accessing beyond the first 3GB of
    523 			 * memory.
    524 			 */
    525 			dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000
    526 				      0x0 0xc0000000>;
    527 			brcm,enable-ssc;
    528 		};
    529 
    530 		genet: ethernet@7d580000 {
    531 			compatible = "brcm,bcm2711-genet-v5";
    532 			reg = <0x0 0x7d580000 0x10000>;
    533 			#address-cells = <0x1>;
    534 			#size-cells = <0x1>;
    535 			interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
    536 				     <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
    537 			status = "disabled";
    538 
    539 			genet_mdio: mdio@e14 {
    540 				compatible = "brcm,genet-mdio-v5";
    541 				reg = <0xe14 0x8>;
    542 				reg-names = "mdio";
    543 				#address-cells = <0x1>;
    544 				#size-cells = <0x0>;
    545 			};
    546 		};
    547 	};
    548 };
    549 
    550 &clk_osc {
    551 	clock-frequency = <54000000>;
    552 };
    553 
    554 &clocks {
    555 	compatible = "brcm,bcm2711-cprman";
    556 };
    557 
    558 &cpu_thermal {
    559 	coefficients = <(-487) 410040>;
    560 	thermal-sensors = <&thermal>;
    561 };
    562 
    563 &dsi0 {
    564 	interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
    565 };
    566 
    567 &dsi1 {
    568 	interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
    569 	compatible = "brcm,bcm2711-dsi1";
    570 };
    571 
    572 &gpio {
    573 	compatible = "brcm,bcm2711-gpio";
    574 	interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
    575 		     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
    576 		     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
    577 		     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
    578 
    579 	gpclk0_gpio49: gpclk0_gpio49 {
    580 		pin-gpclk {
    581 			pins = "gpio49";
    582 			function = "alt1";
    583 			bias-disable;
    584 		};
    585 	};
    586 	gpclk1_gpio50: gpclk1_gpio50 {
    587 		pin-gpclk {
    588 			pins = "gpio50";
    589 			function = "alt1";
    590 			bias-disable;
    591 		};
    592 	};
    593 	gpclk2_gpio51: gpclk2_gpio51 {
    594 		pin-gpclk {
    595 			pins = "gpio51";
    596 			function = "alt1";
    597 			bias-disable;
    598 		};
    599 	};
    600 
    601 	i2c0_gpio46: i2c0_gpio46 {
    602 		pin-sda {
    603 			function = "alt0";
    604 			pins = "gpio46";
    605 			bias-pull-up;
    606 		};
    607 		pin-scl {
    608 			function = "alt0";
    609 			pins = "gpio47";
    610 			bias-disable;
    611 		};
    612 	};
    613 	i2c1_gpio46: i2c1_gpio46 {
    614 		pin-sda {
    615 			function = "alt1";
    616 			pins = "gpio46";
    617 			bias-pull-up;
    618 		};
    619 		pin-scl {
    620 			function = "alt1";
    621 			pins = "gpio47";
    622 			bias-disable;
    623 		};
    624 	};
    625 	i2c3_gpio2: i2c3_gpio2 {
    626 		pin-sda {
    627 			function = "alt5";
    628 			pins = "gpio2";
    629 			bias-pull-up;
    630 		};
    631 		pin-scl {
    632 			function = "alt5";
    633 			pins = "gpio3";
    634 			bias-disable;
    635 		};
    636 	};
    637 	i2c3_gpio4: i2c3_gpio4 {
    638 		pin-sda {
    639 			function = "alt5";
    640 			pins = "gpio4";
    641 			bias-pull-up;
    642 		};
    643 		pin-scl {
    644 			function = "alt5";
    645 			pins = "gpio5";
    646 			bias-disable;
    647 		};
    648 	};
    649 	i2c4_gpio6: i2c4_gpio6 {
    650 		pin-sda {
    651 			function = "alt5";
    652 			pins = "gpio6";
    653 			bias-pull-up;
    654 		};
    655 		pin-scl {
    656 			function = "alt5";
    657 			pins = "gpio7";
    658 			bias-disable;
    659 		};
    660 	};
    661 	i2c4_gpio8: i2c4_gpio8 {
    662 		pin-sda {
    663 			function = "alt5";
    664 			pins = "gpio8";
    665 			bias-pull-up;
    666 		};
    667 		pin-scl {
    668 			function = "alt5";
    669 			pins = "gpio9";
    670 			bias-disable;
    671 		};
    672 	};
    673 	i2c5_gpio10: i2c5_gpio10 {
    674 		pin-sda {
    675 			function = "alt5";
    676 			pins = "gpio10";
    677 			bias-pull-up;
    678 		};
    679 		pin-scl {
    680 			function = "alt5";
    681 			pins = "gpio11";
    682 			bias-disable;
    683 		};
    684 	};
    685 	i2c5_gpio12: i2c5_gpio12 {
    686 		pin-sda {
    687 			function = "alt5";
    688 			pins = "gpio12";
    689 			bias-pull-up;
    690 		};
    691 		pin-scl {
    692 			function = "alt5";
    693 			pins = "gpio13";
    694 			bias-disable;
    695 		};
    696 	};
    697 	i2c6_gpio0: i2c6_gpio0 {
    698 		pin-sda {
    699 			function = "alt5";
    700 			pins = "gpio0";
    701 			bias-pull-up;
    702 		};
    703 		pin-scl {
    704 			function = "alt5";
    705 			pins = "gpio1";
    706 			bias-disable;
    707 		};
    708 	};
    709 	i2c6_gpio22: i2c6_gpio22 {
    710 		pin-sda {
    711 			function = "alt5";
    712 			pins = "gpio22";
    713 			bias-pull-up;
    714 		};
    715 		pin-scl {
    716 			function = "alt5";
    717 			pins = "gpio23";
    718 			bias-disable;
    719 		};
    720 	};
    721 	i2c_slave_gpio8: i2c_slave_gpio8 {
    722 		pins-i2c-slave {
    723 			pins = "gpio8",
    724 			       "gpio9",
    725 			       "gpio10",
    726 			       "gpio11";
    727 			function = "alt3";
    728 		};
    729 	};
    730 
    731 	jtag_gpio48: jtag_gpio48 {
    732 		pins-jtag {
    733 			pins = "gpio48",
    734 			       "gpio49",
    735 			       "gpio50",
    736 			       "gpio51",
    737 			       "gpio52",
    738 			       "gpio53";
    739 			function = "alt4";
    740 		};
    741 	};
    742 
    743 	mii_gpio28: mii_gpio28 {
    744 		pins-mii {
    745 			pins = "gpio28",
    746 			       "gpio29",
    747 			       "gpio30",
    748 			       "gpio31";
    749 			function = "alt4";
    750 		};
    751 	};
    752 	mii_gpio36: mii_gpio36 {
    753 		pins-mii {
    754 			pins = "gpio36",
    755 			       "gpio37",
    756 			       "gpio38",
    757 			       "gpio39";
    758 			function = "alt5";
    759 		};
    760 	};
    761 
    762 	pcm_gpio50: pcm_gpio50 {
    763 		pins-pcm {
    764 			pins = "gpio50",
    765 			       "gpio51",
    766 			       "gpio52",
    767 			       "gpio53";
    768 			function = "alt2";
    769 		};
    770 	};
    771 
    772 	pwm0_0_gpio12: pwm0_0_gpio12 {
    773 		pin-pwm {
    774 			pins = "gpio12";
    775 			function = "alt0";
    776 			bias-disable;
    777 		};
    778 	};
    779 	pwm0_0_gpio18: pwm0_0_gpio18 {
    780 		pin-pwm {
    781 			pins = "gpio18";
    782 			function = "alt5";
    783 			bias-disable;
    784 		};
    785 	};
    786 	pwm1_0_gpio40: pwm1_0_gpio40 {
    787 		pin-pwm {
    788 			pins = "gpio40";
    789 			function = "alt0";
    790 			bias-disable;
    791 		};
    792 	};
    793 	pwm0_1_gpio13: pwm0_1_gpio13 {
    794 		pin-pwm {
    795 			pins = "gpio13";
    796 			function = "alt0";
    797 			bias-disable;
    798 		};
    799 	};
    800 	pwm0_1_gpio19: pwm0_1_gpio19 {
    801 		pin-pwm {
    802 			pins = "gpio19";
    803 			function = "alt5";
    804 			bias-disable;
    805 		};
    806 	};
    807 	pwm1_1_gpio41: pwm1_1_gpio41 {
    808 		pin-pwm {
    809 			pins = "gpio41";
    810 			function = "alt0";
    811 			bias-disable;
    812 		};
    813 	};
    814 	pwm0_1_gpio45: pwm0_1_gpio45 {
    815 		pin-pwm {
    816 			pins = "gpio45";
    817 			function = "alt0";
    818 			bias-disable;
    819 		};
    820 	};
    821 	pwm0_0_gpio52: pwm0_0_gpio52 {
    822 		pin-pwm {
    823 			pins = "gpio52";
    824 			function = "alt1";
    825 			bias-disable;
    826 		};
    827 	};
    828 	pwm0_1_gpio53: pwm0_1_gpio53 {
    829 		pin-pwm {
    830 			pins = "gpio53";
    831 			function = "alt1";
    832 			bias-disable;
    833 		};
    834 	};
    835 
    836 	rgmii_gpio35: rgmii_gpio35 {
    837 		pin-start-stop {
    838 			pins = "gpio35";
    839 			function = "alt4";
    840 		};
    841 		pin-rx-ok {
    842 			pins = "gpio36";
    843 			function = "alt4";
    844 		};
    845 	};
    846 	rgmii_irq_gpio34: rgmii_irq_gpio34 {
    847 		pin-irq {
    848 			pins = "gpio34";
    849 			function = "alt5";
    850 		};
    851 	};
    852 	rgmii_irq_gpio39: rgmii_irq_gpio39 {
    853 		pin-irq {
    854 			pins = "gpio39";
    855 			function = "alt4";
    856 		};
    857 	};
    858 	rgmii_mdio_gpio28: rgmii_mdio_gpio28 {
    859 		pins-mdio {
    860 			pins = "gpio28",
    861 			       "gpio29";
    862 			function = "alt5";
    863 		};
    864 	};
    865 	rgmii_mdio_gpio37: rgmii_mdio_gpio37 {
    866 		pins-mdio {
    867 			pins = "gpio37",
    868 			       "gpio38";
    869 			function = "alt4";
    870 		};
    871 	};
    872 
    873 	spi0_gpio46: spi0_gpio46 {
    874 		pins-spi {
    875 			pins = "gpio46",
    876 			       "gpio47",
    877 			       "gpio48",
    878 			       "gpio49";
    879 			function = "alt2";
    880 		};
    881 	};
    882 	spi2_gpio46: spi2_gpio46 {
    883 		pins-spi {
    884 			pins = "gpio46",
    885 			       "gpio47",
    886 			       "gpio48",
    887 			       "gpio49",
    888 			       "gpio50";
    889 			function = "alt5";
    890 		};
    891 	};
    892 	spi3_gpio0: spi3_gpio0 {
    893 		pins-spi {
    894 			pins = "gpio0",
    895 			       "gpio1",
    896 			       "gpio2",
    897 			       "gpio3";
    898 			function = "alt3";
    899 		};
    900 	};
    901 	spi4_gpio4: spi4_gpio4 {
    902 		pins-spi {
    903 			pins = "gpio4",
    904 			       "gpio5",
    905 			       "gpio6",
    906 			       "gpio7";
    907 			function = "alt3";
    908 		};
    909 	};
    910 	spi5_gpio12: spi5_gpio12 {
    911 		pins-spi {
    912 			pins = "gpio12",
    913 			       "gpio13",
    914 			       "gpio14",
    915 			       "gpio15";
    916 			function = "alt3";
    917 		};
    918 	};
    919 	spi6_gpio18: spi6_gpio18 {
    920 		pins-spi {
    921 			pins = "gpio18",
    922 			       "gpio19",
    923 			       "gpio20",
    924 			       "gpio21";
    925 			function = "alt3";
    926 		};
    927 	};
    928 
    929 	uart2_gpio0: uart2_gpio0 {
    930 		pin-tx {
    931 			pins = "gpio0";
    932 			function = "alt4";
    933 			bias-disable;
    934 		};
    935 		pin-rx {
    936 			pins = "gpio1";
    937 			function = "alt4";
    938 			bias-pull-up;
    939 		};
    940 	};
    941 	uart2_ctsrts_gpio2: uart2_ctsrts_gpio2 {
    942 		pin-cts {
    943 			pins = "gpio2";
    944 			function = "alt4";
    945 			bias-pull-up;
    946 		};
    947 		pin-rts {
    948 			pins = "gpio3";
    949 			function = "alt4";
    950 			bias-disable;
    951 		};
    952 	};
    953 	uart3_gpio4: uart3_gpio4 {
    954 		pin-tx {
    955 			pins = "gpio4";
    956 			function = "alt4";
    957 			bias-disable;
    958 		};
    959 		pin-rx {
    960 			pins = "gpio5";
    961 			function = "alt4";
    962 			bias-pull-up;
    963 		};
    964 	};
    965 	uart3_ctsrts_gpio6: uart3_ctsrts_gpio6 {
    966 		pin-cts {
    967 			pins = "gpio6";
    968 			function = "alt4";
    969 			bias-pull-up;
    970 		};
    971 		pin-rts {
    972 			pins = "gpio7";
    973 			function = "alt4";
    974 			bias-disable;
    975 		};
    976 	};
    977 	uart4_gpio8: uart4_gpio8 {
    978 		pin-tx {
    979 			pins = "gpio8";
    980 			function = "alt4";
    981 			bias-disable;
    982 		};
    983 		pin-rx {
    984 			pins = "gpio9";
    985 			function = "alt4";
    986 			bias-pull-up;
    987 		};
    988 	};
    989 	uart4_ctsrts_gpio10: uart4_ctsrts_gpio10 {
    990 		pin-cts {
    991 			pins = "gpio10";
    992 			function = "alt4";
    993 			bias-pull-up;
    994 		};
    995 		pin-rts {
    996 			pins = "gpio11";
    997 			function = "alt4";
    998 			bias-disable;
    999 		};
   1000 	};
   1001 	uart5_gpio12: uart5_gpio12 {
   1002 		pin-tx {
   1003 			pins = "gpio12";
   1004 			function = "alt4";
   1005 			bias-disable;
   1006 		};
   1007 		pin-rx {
   1008 			pins = "gpio13";
   1009 			function = "alt4";
   1010 			bias-pull-up;
   1011 		};
   1012 	};
   1013 	uart5_ctsrts_gpio14: uart5_ctsrts_gpio14 {
   1014 		pin-cts {
   1015 			pins = "gpio14";
   1016 			function = "alt4";
   1017 			bias-pull-up;
   1018 		};
   1019 		pin-rts {
   1020 			pins = "gpio15";
   1021 			function = "alt4";
   1022 			bias-disable;
   1023 		};
   1024 	};
   1025 };
   1026 
   1027 &rmem {
   1028 	#address-cells = <2>;
   1029 };
   1030 
   1031 &cma {
   1032 	/*
   1033 	 * arm64 reserves the CMA by default somewhere in ZONE_DMA32,
   1034 	 * that's not good enough for the BCM2711 as some devices can
   1035 	 * only address the lower 1G of memory (ZONE_DMA).
   1036 	 */
   1037 	alloc-ranges = <0x0 0x00000000 0x40000000>;
   1038 };
   1039 
   1040 &i2c0 {
   1041 	compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
   1042 	interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
   1043 };
   1044 
   1045 &i2c1 {
   1046 	compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
   1047 	interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
   1048 };
   1049 
   1050 &mailbox {
   1051 	interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
   1052 };
   1053 
   1054 &sdhci {
   1055 	interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
   1056 };
   1057 
   1058 &sdhost {
   1059 	interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
   1060 };
   1061 
   1062 &spi {
   1063 	interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
   1064 };
   1065 
   1066 &spi1 {
   1067 	interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
   1068 };
   1069 
   1070 &spi2 {
   1071 	interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
   1072 };
   1073 
   1074 &system_timer {
   1075 	interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
   1076 		     <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
   1077 		     <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
   1078 		     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
   1079 };
   1080 
   1081 &txp {
   1082 	interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
   1083 };
   1084 
   1085 &uart0 {
   1086 	interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
   1087 };
   1088 
   1089 &uart1 {
   1090 	interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
   1091 };
   1092 
   1093 &usb {
   1094 	interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
   1095 };
   1096 
   1097 &vec {
   1098 	compatible = "brcm,bcm2711-vec";
   1099 	interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
   1100 };
   1101